JPH02216839A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02216839A
JPH02216839A JP1037514A JP3751489A JPH02216839A JP H02216839 A JPH02216839 A JP H02216839A JP 1037514 A JP1037514 A JP 1037514A JP 3751489 A JP3751489 A JP 3751489A JP H02216839 A JPH02216839 A JP H02216839A
Authority
JP
Japan
Prior art keywords
relay
chip
bonding
bonding wire
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1037514A
Other languages
Japanese (ja)
Inventor
Katsuo Takei
武井　勝男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1037514A priority Critical patent/JPH02216839A/en
Publication of JPH02216839A publication Critical patent/JPH02216839A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/481—Disposition
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/494—Connecting portions
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    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
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    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
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    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To realize multipin actualization without enlarging the size of a chip by arranging relay chips where a plurality of relay pads are provided at the outside position of a semiconductor chip having a circuit function, and connecting a part of the middle of a bonding wire, which connects an electrode pad with an outer lead, to the relay pad. CONSTITUTION:The relay chip 6 is a semiconductor chip which does not have a circuit function and has only relay pads 7 being electrically insulated from each other and capable of wire bonding. And the island 4 of a lead frame has an area capable of mounting a main chip 1 and relay chips 6 specified distance apart, and the main chip 1, to nearly the center of the island 4, and the relay chips 6, onto the islands 4 on both sides of the main chip 1, are stuck respectively. On the other hand, through the inner electrode pad 2 of the main chip 1 and the outer lead 3 are connected by a bonding wire 5, hereupon a part of the middle of the bonding wire 5 is connected to the relay pad 7 of the relay chip 6.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に半導体チップの内部電
極パッドと外部リードとをワイヤにより接続する構造に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a structure in which internal electrode pads and external leads of a semiconductor chip are connected by wires.

〔従来の技術〕[Conventional technology]

従来、半導体チップの内部電極パッドと外部リードとの
接続をワイヤーボンディングにより行う半導体装置では
、第５図に示すように、リードフレームもしくはパッケ
ージのアイランド４に固定された半導体チップ１の内部
電極パッド２と外部リード３の２箇所にわたってボンデ
ィングワイヤ５を接続した構成となっている。Conventionally, in a semiconductor device in which internal electrode pads of a semiconductor chip and external leads are connected by wire bonding, internal electrode pads 2 of a semiconductor chip 1 fixed to a lead frame or an island 4 of a package are connected as shown in FIG. The bonding wire 5 is connected to the external lead 3 at two locations.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところで、最近の半導体装置にあっては、高機能化、動
作させる為のソフト設計の容易化等の理由より入出力ピ
ン数が数百ビンにも及ぶいわゆる多ピン化が必要とされ
てきている。このような状況の下で、ワイヤーボンディ
ングによって内部電極パッドと外部リードとを接続する
半導体装置の多ビン化を図る際には、次にあげる２つの
制約を受ける。By the way, in recent semiconductor devices, it has become necessary to increase the number of input/output pins to several hundred pins for reasons such as higher functionality and easier software design for operation. . Under these circumstances, when attempting to increase the number of bins in a semiconductor device that connects internal electrode pads and external leads by wire bonding, the following two constraints are encountered.

まず第１に外部リードのピッチ及び幅である。First of all, the pitch and width of the external leads.

第６図に示す外部リード３のピッチＬＰおよび幅ＬＷは
、現在最小のものでＬ　Ｐ　−０，２２ｍｍ、　　Ｌ　
Ｗ　＝０．１１ｍｍ程度である。外部リード３は通常金
属板をプレス加工やエツチング加工により成形している
が、リード側のボンディング性を損なうことなしにピッ
チおよび幅をこれ以上狭く加工することば事実上不可能
になってきている。The pitch LP and width LW of the external leads 3 shown in FIG. 6 are currently minimum, L P -0.22 mm, L
W = approximately 0.11 mm. The external leads 3 are usually formed from a metal plate by pressing or etching, but it has become virtually impossible to further reduce the pitch and width without impairing the bonding properties of the leads.

制約の第２は半導体チップのチップサイズの問題である
。チップサイズが太き（なるとシリコンウニへ当りの収
率が減りコスト高となる。このためチップサイズは、機
能を満たすに必要なだけの最小寸法にすることが望まし
い。The second constraint is the problem of the chip size of the semiconductor chip. If the chip size is large, the yield per silicon urchin will decrease and the cost will increase. Therefore, it is desirable that the chip size be the minimum size necessary to satisfy the function.

以上の２つの制約から、従来の半導体装置でチップサイ
ズを小さ（抑え、しかも外部リードの寸法を変えること
なく多ピン化を図る場合には、第６図に示す半導体チッ
プ１の内部電極パッド２と外部リード３との間の距離り
を長くとり、外部リードが配置される領域を広くして外
部リードの数を増やすという対策が必要になる。Due to the above two constraints, in order to reduce the chip size of a conventional semiconductor device and increase the number of pins without changing the dimensions of the external leads, the internal electrode pad 2 of the semiconductor chip 1 shown in FIG. It is necessary to take measures to increase the number of external leads by increasing the distance between the external lead 3 and the external lead 3, and by widening the area where the external leads are arranged.

ところが、この距離りが長くなるに従い、ワイヤーボン
ディングによって結線されるワイヤは第６図のＡに示す
ようなカール形状やリード面よりワイヤが下方に垂れ下
がった形状になり易くなる。However, as this distance becomes longer, the wires connected by wire bonding tend to have a curled shape as shown in A in FIG. 6 or a shape in which the wires hang downward from the lead surface.

また、ボンディング時には支障なく結線されたワイヤで
あっても、樹脂封止によって封止される半導体装置では
ワイヤが長い分圧入さ軌る樹脂によってワイヤが容易に
変形するようになる。そして、このようなワイヤの変形
は内部ショートの原因となる。Further, even if the wires are connected without any problem during bonding, in a semiconductor device sealed with resin, the wires are easily deformed by the resin that is press-fitted in a long portion. Such deformation of the wire causes an internal short circuit.

以上のように、内部電極パッドと外部リードとの距離が
長くなるとワイヤの結線不良が生じ易いため、従来の半
導体装置で多ピン化を図る場合には内部電極パッドと外
部リードとの距離が長く取れない分、チップの機能とは
無関係にチップサイズを大きくしなくてはならずコスト
高になるという問題があった。As described above, when the distance between the internal electrode pad and the external lead becomes long, wire connection defects are likely to occur, so when increasing the number of pins in a conventional semiconductor device, the distance between the internal electrode pad and the external lead is long. The problem is that the chip size must be increased regardless of the chip's function, resulting in higher costs.

本発明はチップサイズを大きくすることなく多ビン化を
実現する半導体装置を提供することを目的とする。An object of the present invention is to provide a semiconductor device that can realize multiple bins without increasing the chip size.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、回路機能を有する半導体チップ
の外側位置に複数個の中継パッドを設けた中継チップを
配設し、半導体チップの電極パッドと外部リードとを接
続するボンディングワイヤの中間一部をこの中継パッド
に接続している。In the semiconductor device of the present invention, a relay chip having a plurality of relay pads is disposed outside a semiconductor chip having a circuit function, and a middle part of a bonding wire connecting an electrode pad of the semiconductor chip and an external lead is provided. is connected to this relay pad.

〔作用］ 上述した構成では、ボンディングワイヤは中間一部が中
継パッドにより支持されるため、その機械的な強度が増
大され、ボンディングワイヤの変形による内部ショート
を防止する。[Function] In the above-described configuration, since the intermediate portion of the bonding wire is supported by the relay pad, its mechanical strength is increased and internal short circuits due to deformation of the bonding wire are prevented.

〔実施例］ 次に、本発明を図面を参照して説明する。〔Example] Next, the present invention will be explained with reference to the drawings.

第１図（ａ）は本発明の第１実施例の要部の平面図、第
１図（ｂ）はその全体縦断面図である。FIG. 1(a) is a plan view of a main part of a first embodiment of the present invention, and FIG. 1(b) is a longitudinal cross-sectional view of the whole.

これらの図において、主チップｌは回路機能を存する従
来の半導体チップである。また、中継チップ６は、それ
自体は回路機能を持たずその内部には、相互に電気的に
絶縁されたワイヤーボンディング可能な中継パッド７の
みを有する半導体チップである。そして、リードフレー
ムのアイランド４は、主チップ１と中継チップ６を所定
の距１離して搭載可能な面積を有しており、前記主チッ
プ１をアイランド４の略中夫に、中継チップ６を主チッ
プ１の両側のアイランド４上に夫々固着している。なお
、主チップｌと中継チップ６は電気的に絶縁されている
。In these figures, the main chip l is a conventional semiconductor chip containing circuit functions. Further, the relay chip 6 is a semiconductor chip that does not itself have a circuit function and has only relay pads 7 therein which are electrically insulated from each other and capable of wire bonding. The island 4 of the lead frame has an area capable of mounting the main chip 1 and the relay chip 6 at a predetermined distance of 1. They are fixed on the islands 4 on both sides of the main chip 1, respectively. Note that the main chip 1 and the relay chip 6 are electrically insulated.

一方、主チップ１の内部電極パッド２と外部リード３と
はボンディングワイヤ５によって接続されているが、こ
こではボンディングワイヤ５の中間一部を前記中継チッ
プ６の中継パッド７に接続している。On the other hand, the internal electrode pads 2 of the main chip 1 and the external leads 3 are connected by a bonding wire 5, and here, a middle part of the bonding wire 5 is connected to the relay pad 7 of the relay chip 6.

このボンディングワイヤ５の接続方法としては、例えば
第２図（ａ）に示すように、キャピラリ（ボンディング
ツール）Ｔを用いて主チップ１の内部電極バッド２にボ
ンディングワイヤ５の先端を接続した後、ボンディング
ワイヤ５を移動させて今度は中継チップ６の中継パッド
７にボンディングを行う。更に、同図（ｂ）のように、
ボンディングワイヤ５を延長させて外部リード３にも接
続を行う。その後、同図（ｃ）のように、ボンディング
ワイヤ５を切断し、ボンディングが完了される。The method for connecting the bonding wire 5 is, for example, as shown in FIG. 2(a), after connecting the tip of the bonding wire 5 to the internal electrode pad 2 of the main chip 1 using a capillary (bonding tool) T. The bonding wire 5 is moved and bonding is now performed to the relay pad 7 of the relay chip 6. Furthermore, as shown in the same figure (b),
The bonding wire 5 is extended and connected to the external lead 3 as well. Thereafter, as shown in FIG. 3(c), the bonding wire 5 is cut to complete the bonding.

なお、ボンディングワイヤの他の接続方法としては、第
３図（ａ）のように、最初に主チップ１の内部電極バッ
ド２と中継チップ６の中継パッド７とのボンディングを
行い、−旦ボンディングワイヤ５を切断する。その後、
再びボンディングボール５ａを形成後、同図（ｂ）のよ
うに、中継パッド７と外部リード３とのボンディングを
行う。In addition, as another method for connecting bonding wires, as shown in FIG. Cut 5. after that,
After forming the bonding ball 5a again, the relay pad 7 and the external lead 3 are bonded to each other as shown in FIG. 3(b).

その後、同図（Ｃ）ようにボンディングワイヤ５を切断
してボンディングが完了される。Thereafter, the bonding wire 5 is cut as shown in FIG. 2C to complete the bonding.

したがって、この構成では、ボンディングワイヤ５はそ
の中間の一部において中継チップ６により支持されるこ
とになり、ボンディングワイヤ５を長くした場合でもそ
の機械的な強度が向上される。これにより、半導体チッ
プ（主チップ）を小型化し、かつ一方で外部リードを他
ピン化して両者間の距離を大きくした場合でも、ボンデ
ィングワイヤ５の変形が防止され、内部シａ　−トの発
生を抑制することができる。Therefore, in this configuration, the bonding wire 5 is supported by the relay chip 6 at a portion in the middle thereof, and even when the bonding wire 5 is made long, its mechanical strength is improved. As a result, even if the semiconductor chip (main chip) is miniaturized and the external leads are made into separate pins to increase the distance between them, deformation of the bonding wire 5 is prevented and the generation of internal sheets is prevented. Can be suppressed.

第４図は本発明の第２実施例を示しており、半導体装置
の内部構造の一部平面図である。FIG. 4 shows a second embodiment of the present invention, and is a partial plan view of the internal structure of a semiconductor device.

この実施例では、第４図（ａ）のように、中継チップ６
に設けた複数個の中継パッド７のうち、所定のものにつ
いては中継チップ６内に設けた内部配線８により相互に
電気接続した構成としている。ここでは、中継パッド７
ａと中継パッド７ｂが電気接続されている。In this embodiment, as shown in FIG. 4(a), the relay chip 6
Of the plurality of relay pads 7 provided in the relay chip 6, predetermined ones are electrically connected to each other by internal wiring 8 provided in the relay chip 6. Here, relay pad 7
a and relay pad 7b are electrically connected.

したがって、第２図（ａ）のように、ボンディングワイ
ヤ５の中間を中継パッド７ａに接続し、更にこのワイヤ
５をそのまま延長して外部リード３に接続する構成とす
るのは勿論であるが、第２図（ｂ）のように、ボンディ
ングワイヤ５で内部電極パッド２と中継パッド７ａとを
接続する一方で、別のボンディングワイヤ５Ａで中継パ
ッド７ｂと外部リード３を接続する構成とすることも可
能である。Therefore, as shown in FIG. 2(a), it is of course possible to connect the middle of the bonding wire 5 to the relay pad 7a, and then extend this wire 5 as it is and connect it to the external lead 3. As shown in FIG. 2(b), a structure may be adopted in which the bonding wire 5 connects the internal electrode pad 2 and the relay pad 7a, while another bonding wire 5A connects the relay pad 7b and the external lead 3. It is possible.

これにより、同一の主チップ１を異種のリードフレーム
に容易に搭載することができ、主チップ１及びリードフ
レームの汎用性を高めることができるという利点がある
。This has the advantage that the same main chip 1 can be easily mounted on different types of lead frames, and the versatility of the main chip 1 and the lead frame can be increased.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ボンディングワイヤを中
継支持する中継チップを設けることにより、電極パッド
と外部リードとの距離が長くなってもワイヤの接続不良
を防止でき、半導体チップの小型化を図る一方で他ビン
化が実現できる。また、中継チップには中継パッドのみ
を設ければよいため、製造に必要な工程数は非常に少な
くてよく、しかも半導体装置の組立に際しても特別な設
備を必要としないため、上述した他ピン化された半導体
装置を低コストで実現できる効果がある。As explained above, by providing a relay chip that relays and supports bonding wires, the present invention can prevent poor connection of wires even when the distance between an electrode pad and an external lead becomes long, thereby reducing the size of a semiconductor chip. On the other hand, it is possible to create other bins. In addition, since only relay pads need to be provided on the relay chip, the number of manufacturing steps required is extremely small, and no special equipment is required when assembling the semiconductor device. This has the effect of making it possible to realize an integrated semiconductor device at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）は本発明の半導体装置の第１実施例の一部
の平面図、第１図（ｂ）はその全体構成の縦断面図、第
２図（ａ）乃至第２図（ｃ）はワイヤのボンディング方
法を説明するための一部の縦断面図、第３図（ａ）乃至
第３図（Ｃ）は他のワイヤボンディング方法を説明する
ための一部の縦断面図、第４図（ａ）および第４図（ｂ
）は本発明の第２実施例の夫々異なる態様を示す一部の
平面図、第５図は従来の半導体装置の縦断面図、第６図
は従来の半導体装置の問題を説明するための一部の平面
図である。 １・・・主チップ（半導体チップ）、２・・・内部電極
パッド、３・・・外部リード、４・・・アイランド、５
．５Ａ・・・ボンディングワイヤ、５ａ・・・ボール、
６・・・中継チップ、７．７ａ、７ｂ・・・中継パッド
、８・・・内部配線、Ｔ・・・キャピラリ（ボンディン
グツール）。 第 図 （ａ） （ｂ） 第３ 図 （ａ） （ｂ） （Ｃ） 第２ 図 （ａ） （Ｃ） 第４ 図 （ａ） （ｂ）FIG. 1(a) is a plan view of a part of the first embodiment of the semiconductor device of the present invention, FIG. 1(b) is a vertical sectional view of the overall configuration, and FIGS. c) is a partial vertical cross-sectional view for explaining the wire bonding method; FIGS. 3(a) to 3(C) are partial vertical cross-sectional views for explaining other wire bonding methods; Figures 4(a) and 4(b)
) are partial plan views showing different aspects of the second embodiment of the present invention, FIG. 5 is a vertical cross-sectional view of a conventional semiconductor device, and FIG. 6 is a partial plan view for explaining the problems of the conventional semiconductor device. FIG. 1... Main chip (semiconductor chip), 2... Internal electrode pad, 3... External lead, 4... Island, 5
．． 5A...bonding wire, 5a...ball,
6... Relay chip, 7.7a, 7b... Relay pad, 8... Internal wiring, T... Capillary (bonding tool). Figures (a) (b) Figure 3 (a) (b) (C) Figure 2 (a) (C) Figure 4 (a) (b)

Claims (1)

【特許請求の範囲】[Claims] １、半導体チップの電極パッドと外部リードとをボンデ
ィングワイヤにより接続する半導体装置において、回路
機能を有する半導体チップの外側位置に複数個の中継パ
ッドを設けた中継チップを配設し、前記ボンディングワ
イヤの中間一部をこの中継パッドに接続したことを特徴
とする半導体装置。1. In a semiconductor device in which an electrode pad of a semiconductor chip and an external lead are connected by a bonding wire, a relay chip having a plurality of relay pads is disposed outside a semiconductor chip having a circuit function, and A semiconductor device characterized in that a middle portion is connected to the relay pad.
JP1037514A 1989-02-17 1989-02-17 Semiconductor device Pending JPH02216839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1037514A JPH02216839A (en) 1989-02-17 1989-02-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1037514A JPH02216839A (en) 1989-02-17 1989-02-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02216839A true JPH02216839A (en) 1990-08-29

Family

ID=12499647

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1037514A Pending JPH02216839A (en) 1989-02-17 1989-02-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02216839A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115977B2 (en) * 2000-09-28 2006-10-03 Oki Electric Industry Co., Ltd. Multi-chip package type semiconductor device
US8404980B2 (en) 2005-09-30 2013-03-26 Fujitsu Semiconductor Limited Relay board and semiconductor device having the relay board
WO2013140928A1 (en) * 2012-03-21 2013-09-26 住友電気工業株式会社 Semiconductor device
CN108269792A (en) * 2011-05-18 2018-07-10 晟碟半导体（上海）有限公司 Waterfall wire bonding

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115977B2 (en) * 2000-09-28 2006-10-03 Oki Electric Industry Co., Ltd. Multi-chip package type semiconductor device
US8053278B2 (en) 2000-09-28 2011-11-08 Oki Semiconductor Co., Ltd. Multi-chip package type semiconductor device
US8404980B2 (en) 2005-09-30 2013-03-26 Fujitsu Semiconductor Limited Relay board and semiconductor device having the relay board
CN108269792A (en) * 2011-05-18 2018-07-10 晟碟半导体（上海）有限公司 Waterfall wire bonding
WO2013140928A1 (en) * 2012-03-21 2013-09-26 住友電気工業株式会社 Semiconductor device

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