JPS63104437A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63104437A JPS63104437A JP25231286A JP25231286A JPS63104437A JP S63104437 A JPS63104437 A JP S63104437A JP 25231286 A JP25231286 A JP 25231286A JP 25231286 A JP25231286 A JP 25231286A JP S63104437 A JPS63104437 A JP S63104437A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- semiconductor chip
- external lead
- surface electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 238000005452 bending Methods 0.000 claims description 2
- 238000007781 pre-processing Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に半導体チ・
ンブ側の表面電極を外部リードに接続するだめのワイヤ
ポンディング部構造を改良してなる半導体装置の製造方
法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a semiconductor device by improving the structure of a wire bonding part for connecting a surface electrode on the side of a semiconductor wafer to an external lead.
従来この種の半導体装置において一ヒ述したワイヤボン
ディング部は、概略第３図に示すような構成とされてい
た。これを簡単に説明すると、図中符号１は半導体チッ
プ、２はこの半導体チップ１が搭載されはんだ付は等で
固着されるダイパッドｓ２ａを有するフレームで、かつ
このフレーム２側に形成されている外部リード２ｂ 、
２ｂに対して前記半導体チップ１側の表面電極１ａ、ｌ
ａが、符号３で示す金線等による金属細線（以下ワイヤ
という）で接続されている。ここで、このワイヤ３は、
前記表面電極１ａに対し一端がポールポンド法で、また
他端は外部リード２ｂに対しスティッチポンド法でそれ
ぞれ接続することが一般に行なわれていた。Conventionally, in this type of semiconductor device, the wire bonding section described above has a structure as schematically shown in FIG. 3. To explain this simply, reference numeral 1 in the figure is a semiconductor chip, 2 is a frame having a die pad s2a on which the semiconductor chip 1 is mounted and fixed by soldering, etc., and an external part formed on the side of the frame 2. Lead 2b,
surface electrodes 1a, l on the semiconductor chip 1 side with respect to 2b;
a are connected by a thin metal wire (hereinafter referred to as wire) such as a gold wire indicated by reference numeral 3. Here, this wire 3 is
Generally, one end is connected to the surface electrode 1a by the pole-pond method, and the other end is connected to the external lead 2b by the stitch-pond method.
ところで、上述した従来構造による半導体装置では、ワ
イヤ３によって半導体チップ１側の表面電極１ａと外部
リード２ｂとを結線するにあたって、ワイヤ３が半導体
チップ１側縁の角部に接触するといった問題をもつもの
であった。そして、これを解消するためには、半導体チ
ップ１側の表面電極１ａと外部リード２ｂとの間隔を犬
きく必要とし、接続に必要なワイヤ３の長さが長くなる
ものであり、実用上での問題が大きく、何らかの対策を
講じることが必要とされている。By the way, the semiconductor device having the conventional structure described above has a problem in that when the wire 3 connects the surface electrode 1a on the semiconductor chip 1 side and the external lead 2b, the wire 3 comes into contact with the corner of the side edge of the semiconductor chip 1. It was something. In order to solve this problem, it is necessary to increase the distance between the surface electrode 1a on the semiconductor chip 1 side and the external lead 2b, which increases the length of the wire 3 required for connection, which is not practical. This is a serious problem, and it is necessary to take some measures.
本発明は上述した事情に鑑みてなされたもので、ワイヤ
の半導体チップ角部への接触等といった問題を防止する
とともに、ワイヤの接続に必要な長さを短くすることが
可能となる半導体装置の製造方法を得ることを目的とし
ている。The present invention has been made in view of the above-mentioned circumstances, and is a semiconductor device that prevents problems such as wires coming into contact with the corners of semiconductor chips, and also reduces the length required for wire connection. The purpose is to obtain a manufacturing method.
本発明に係る半導体装置の製造方法は、半導体チップ側
の表面電極と外部リードとをワイヤで結線するにあたっ
ての前処理工程として、外部リードまたはこの外部リー
ドおよび半導体チップ搭載用のダイパッド部に、外部リ
ードと前記表面電極の高さ位置との差が小さくなるよう
な曲げ加工を施すようにしたものである。In the method for manufacturing a semiconductor device according to the present invention, as a preprocessing step for connecting the surface electrode on the semiconductor chip side and the external lead with a wire, the external lead or the external lead and the die pad portion for mounting the semiconductor chip are The bending process is performed to reduce the difference in height between the lead and the surface electrode.
本発明によれば、半導体チップ側の表面電極の高さ位置
と、外部リード側の接続部表面の高さ位置とをほとんど
差がないように構成することが可能で、これによりワイ
ヤ結線時において、ワイヤが半導体チップ側の角部に接
触することを防止できるとともに、ワイヤの接続に必要
な長さを短くすることが可能となるものである。According to the present invention, it is possible to configure the height position of the surface electrode on the semiconductor chip side and the height position of the connection part surface on the external lead side so that there is almost no difference. In addition, it is possible to prevent the wire from coming into contact with the corner of the semiconductor chip, and to shorten the length required for the wire connection.
以下、本発明を図面に示した実施例を用いて詳細に説明
する。Hereinafter, the present invention will be explained in detail using embodiments shown in the drawings.
第１図は本発明に係る半導体装置の製造方法の一実施例
を示すものであり、図において前述した第３図と同一ま
たは相当する部分には同一番号を付してその説明は省略
する。FIG. 1 shows an embodiment of the method for manufacturing a semiconductor device according to the present invention, and in the figure, the same or corresponding parts as in FIG.
さて、本発明によれば、半導体チップ１側の表面電極１
ａと外部リード２ｂとをワイヤで結線するにあたっての
前処理工程として、前記外部り−ド２ｂに対し、前記表
面電極１ａの高さ位置との差が小さくなるような上方へ
の曲げ加工を施すようにしたところに特徴を有している
。Now, according to the present invention, the surface electrode 1 on the semiconductor chip 1 side
As a pre-processing step for connecting the outer lead 2b and the outer lead 2b with a wire, the outer lead 2b is bent upward so as to reduce the difference in height from the surface electrode 1a. It is characterized by the fact that it is made as follows.
そして、このような前処理工程を行なうと、半導体チッ
プ１側の表面電極１ａに対して、外部リード２ｂ側の接
続部表面の高さ位置をほとんど差がないようにすること
が可能で、これによりワイヤ３による結線時において、
ワイヤ３が半導体チップ１側縁の角部に接触するといっ
た問題を防止し得るもので、またこのワイヤ３の接続に
必要な長さを短くし得る等といった利点もある。By performing such a pretreatment process, it is possible to make there be almost no difference in height between the surface electrode 1a on the side of the semiconductor chip 1 and the surface of the connection part on the side of the external lead 2b. When connecting with wire 3,
This can prevent the problem of the wire 3 coming into contact with the corner of the side edge of the semiconductor chip 1, and has the advantage that the length required for connection of the wire 3 can be shortened.
ここで、上述した以外の半導体装置の製造方法は従来と
同様で、その詳細な説明は省略する。Here, the manufacturing method of the semiconductor device other than those described above is the same as the conventional method, and detailed explanation thereof will be omitted.
第２図は本発明の別の実施例を示すものであって、この
実施例では、上述した外部リード２ｂに上方への曲げ加
工を、一方前記半導体チツブｌが搭載して固着されるダ
イパッド部２ａ（実際にはフレーム２に対するこのダイ
パッド部２ａの支持部）に下方への曲げ加工を施すこと
で、外部り−ド２ｂと前記表面電極１ａの高さ位置との
差が小さくなるようにした場合で、このようにしても、
−上述した実施例と同等の作用効果が得られることは容
易に理解されよう。FIG. 2 shows another embodiment of the present invention. In this embodiment, the above-mentioned external lead 2b is bent upward, while the die pad portion on which the semiconductor chip l is mounted and fixed. 2a (actually, the supporting portion of this die pad portion 2a relative to the frame 2) is bent downward to reduce the difference in height between the outer wire 2b and the surface electrode 1a. In this case, even if you do this,
- It will be easily understood that the same effects as those of the above-mentioned embodiments can be obtained.
なお、本発明は上述した実施例構造に限定されず、各部
の形状、構造等を、適宜変形、変更することは自由で、
種々の変形例が考えられる。Note that the present invention is not limited to the structure of the embodiments described above, and the shape and structure of each part may be modified or changed as appropriate.
Various modifications are possible.
以上説明したように、本発明に係る半導体装置の製造方
法によれば、半導体チップ側の表面電極と外部リードと
をワイヤで結線するにあたっての前処理工程として、外
部リードまたは外部リードおよび半導体チップ搭載用の
ダイパッド部に曲げ加工を施すようにしたので、簡単な
方法にもかかわらず、半導体チップ側の表面電極の高さ
位置と、外部リード側の接続部表面の高さ位置とをほと
んど差がないようにすることが可能で、これによりワイ
ヤ結線時において、ワイヤが半導体チップ側の角部に接
触することを防止し得るとともに、このワイヤの接続に
必要な長さを短くすることが可能となる等の種々優れた
効果がある。As explained above, according to the method for manufacturing a semiconductor device according to the present invention, as a pre-processing step for connecting the surface electrode on the semiconductor chip side and the external lead with a wire, the external lead or the external lead and the semiconductor chip mounting Although it is a simple method, there is almost no difference between the height position of the surface electrode on the semiconductor chip side and the height position of the connection part surface on the external lead side. This makes it possible to prevent the wire from coming into contact with the corner of the semiconductor chip during wire connection, and to shorten the length of the wire required for connection. There are various excellent effects such as:
第１図は本発明に係る半導体装置の製造方法の一実施例
を示す要部断面図、第２図は本発明の別の実施例を示す
要部断面図、第３図は従来例を示す要部断面図である。
１・・・・半導体チップ、１ａ・・・・表面電極、２・
・・・フ１／−ム、２ａ・・・・ダイパッド部、２ｂ・
・・・外部リード、３・・・・ワイヤ（金属細線）。FIG. 1 is a sectional view of a main part showing one embodiment of the method for manufacturing a semiconductor device according to the present invention, FIG. 2 is a sectional view of a main part showing another embodiment of the invention, and FIG. 3 is a conventional example. It is a sectional view of the main part. 1... Semiconductor chip, 1a... Surface electrode, 2...
...Frame 1/- frame, 2a...Die pad part, 2b.
...External lead, 3...Wire (thin metal wire).
Claims (2)
細線で結線するにあたっての前処理工程として、前記外
部リードに対し、前記表面電極の高さ位置との差が小さ
くなるような曲げ加工を施すことを特徴とする半導体装
置の製造方法。(1) As a pretreatment process for connecting the surface electrode on the semiconductor chip side and the external lead with a thin metal wire, the external lead is bent so that the difference in height from the surface electrode is reduced. 1. A method for manufacturing a semiconductor device, comprising:
細線で結線するにあたっての前処理工程として、前記外
部リードおよび前記半導体チップが搭載されるダイパッ
ド部に対し、外部リードと前記表面電極の高さ位置との
差が小さくなるような曲げ加工を施すことを特徴とする
半導体装置の製造方法。(2) As a pretreatment process for connecting the surface electrodes on the semiconductor chip side and the external leads with thin metal wires, the height of the external leads and the surface electrodes is 1. A method for manufacturing a semiconductor device, characterized in that a bending process is performed so that the difference between the vertical position and the vertical position is reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25231286A JPS63104437A (en) | 1986-10-22 | 1986-10-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25231286A JPS63104437A (en) | 1986-10-22 | 1986-10-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63104437A true JPS63104437A (en) | 1988-05-09 |
Family
ID=17235498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25231286A Pending JPS63104437A (en) | 1986-10-22 | 1986-10-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63104437A (en) |
-
1986
- 1986-10-22 JP JP25231286A patent/JPS63104437A/en active Pending
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