JPS621239A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS621239A
JPS621239A JP60139863A JP13986385A JPS621239A JP S621239 A JPS621239 A JP S621239A JP 60139863 A JP60139863 A JP 60139863A JP 13986385 A JP13986385 A JP 13986385A JP S621239 A JPS621239 A JP S621239A
Authority
JP
Japan
Prior art keywords
inner leads
lead
leads
adjacent
bonding wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60139863A
Other languages
Japanese (ja)
Inventor
Mitsumasa Tsutsui
筒井　光正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Priority to JP60139863A priority Critical patent/JPS621239A/en
Publication of JPS621239A publication Critical patent/JPS621239A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To scale down the external shape, and to improve reliability by vertically moving the height of other adjacent inner leads alternately to an inner lead, reducing the pitches of the inner leads and preventing contacts among adjacent bonding wires. CONSTITUTION:Other inner leads 12b are formed on the same plane as a bed 13 for a lead frame, and the nose section of one inner lead 12a is shaped where higher than the bed 13. The nose section of one bent inner lead 12a is positioned where more separate from a semiconductor chip 14 than another adjacent inner lead 12b, and each inner lead 12a, 12b is connected to an electrode for the semiconductor chip 14 by bonding wires 15, but the height of adjacent inner leads and the bonding wires differ because the inner leads 12a, 12b are arranged at a stepped section, thus reducing possibility that the inner leads are brought into contact mutually. Accordingly, the spaces of the leads can be made narrower than conventional devices.

Description

【発明の詳細な説明】 （発明の技術分野〕 本発明はリードフレームにマウントされた半導体素子を
樹脂で封止した樹脂封止型の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a resin-sealed semiconductor device in which a semiconductor element mounted on a lead frame is sealed with resin.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

第３図および第４図に従来の樹脂封止型半導体装置を示
す。第３図は樹脂封止の模様を示す透視平面図、第４図
はその断面図である。リードフレームのベッド３上に導
電性接着剤等によって半導体チップ（素子）がマウント
され、リードフレームのベッド３と所定の間隔を有して
放射状に離隔配設されたリードフレームのインナリード
２と半導体チップ４の電極とが金線、アルミニウム線等
のボンディングワイヤ５で接続されている。そして、半
導体チップ４、ボンディングワイヤ５およびインナリー
ド２を含む領域が封止樹脂１によって封止され、インナ
リード２に連設するアウタリード６が封止樹脂１から水
平に突出してフラットパッケージ型の半導体装置が構成
される。FIGS. 3 and 4 show conventional resin-sealed semiconductor devices. FIG. 3 is a perspective plan view showing the pattern of resin sealing, and FIG. 4 is a sectional view thereof. A semiconductor chip (element) is mounted on the bed 3 of the lead frame with a conductive adhesive or the like, and the inner leads 2 of the lead frame and the semiconductor are arranged radially apart from the bed 3 of the lead frame at a predetermined distance. The electrodes of the chip 4 are connected with bonding wires 5 such as gold wires or aluminum wires. Then, a region including the semiconductor chip 4, bonding wires 5, and inner leads 2 is sealed with a sealing resin 1, and outer leads 6 connected to the inner leads 2 protrude horizontally from the sealing resin 1 to form a flat package type semiconductor. The device is configured.

しかしながら、この従来装置においては、インナリード
先端ピッチは強度上の要求から非常に微小にすることは
困難であり、一般に半導体チップ４の電極の間隔に比べ
て大きくなる。したがって電極の数と同数のインナリー
ドを具備するためには、半導体チップの大きさを大きく
しなければならず、パッケージの外形が大きくなる。又
、すべてのインナリードが同一平面上に位置するため、
インナリードの曲り等による隣接するインナリード先端
どうしの接触不良および隣接するボンディングワイヤど
うしの接触不良が多く、歩留りの低下、信頼性低下の原
因となっているという問題がある。However, in this conventional device, it is difficult to make the inner lead tip pitch very small due to strength requirements, and it is generally larger than the spacing between the electrodes of the semiconductor chip 4. Therefore, in order to provide the same number of inner leads as the number of electrodes, the size of the semiconductor chip must be increased, which increases the external size of the package. Also, since all inner leads are located on the same plane,
There are problems in that there are many poor contacts between the tips of adjacent inner leads and poor contacts between adjacent bonding wires due to bending of the inner leads, etc., which causes a decrease in yield and reliability.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情を考慮してなされたもので、パッケー
ジ外形の縮小化とボンディングワイヤ等の接触防止を可
能とした半導体装置を提供することを目的とする。The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor device that can reduce the external size of a package and prevent contact with bonding wires and the like.

〔発明の概要〕[Summary of the invention]

上記目的を達成するため、本発明による半導体装置は、
−のインナリードに対して隣接する他のインナリードの
＾さを交互に上下させて、インナリードのピッチを小さ
くし、又、隣接するボンディングワイヤの接触を防止し
たことを特徴としている。このため外形の縮小化と信頼
性の向上を図ることができる。In order to achieve the above object, a semiconductor device according to the present invention includes:
It is characterized in that the pitch of the other inner leads adjacent to the - inner lead is alternately raised and lowered to reduce the pitch of the inner leads and to prevent adjacent bonding wires from coming into contact with each other. Therefore, it is possible to reduce the external size and improve reliability.

（発明の実施例〕 以下、本発明の一実施例を添付図面を参照して具体的に
説明する。第１図は本発明の一実施例の透視平面図、第
２図はその断面図である。この実施例の装置は、リード
フレームのベッド１３上に導電性接着剤を介してマウン
トされた半導体チップ１４と、ベッド１３と一定の間隔
で配設されたリードフレームのインナリード１２ａ、１
２ｂと、このインナリード１２ａ、１２ｂと半導体チッ
プ１４の電極とを接続するボンディングワイヤ１５とを
具備している。そして、半導体チップ１４、ボンディン
グワイヤ１５およびインナリード１２ａ、１２ｂを含む
領域が封止樹脂１１で封止され、インナリード１２ａ、
１２ｂに連設するアウタリード１６が封止樹脂１１から
突出して引出し端子となっている。このような半導体装
置において、−のインナリード１２ａは第２図に図示さ
れるようにその先端部が隣接する他のインナリード１２
ｂよりも高くなっており、この高低が隣接するインナリ
ード間で交互にくり返されている。(Embodiments of the Invention) Hereinafter, an embodiment of the present invention will be specifically described with reference to the accompanying drawings. Fig. 1 is a perspective plan view of an embodiment of the present invention, and Fig. 2 is a sectional view thereof. The device of this embodiment includes a semiconductor chip 14 mounted on a bed 13 of a lead frame via a conductive adhesive, and inner leads 12a and 1 of the lead frame arranged at a constant distance from the bed 13.
2b, and bonding wires 15 that connect the inner leads 12a, 12b and the electrodes of the semiconductor chip 14. Then, a region including the semiconductor chip 14, the bonding wires 15, and the inner leads 12a, 12b is sealed with the sealing resin 11, and the inner leads 12a, 12b are sealed with the sealing resin 11.
An outer lead 16 connected to the outer lead 12b protrudes from the sealing resin 11 and serves as a lead terminal. In such a semiconductor device, as shown in FIG.
b, and this height is repeated alternately between adjacent inner leads.

すなわち、他のインナリード１２ｂはリードフレームの
ベッド１３と同一平面上に位置しており、−のインナリ
ード１２ａの先端部はベッド１３よりも高い位置に存在
する。このような段差は例えばリードフレームの打抜き
の際、高い位置のインナリード７ａをプレス加工で折曲
させることで形成することができる。このような加工に
より、折曲されたーのインナリード１２ａの先端部は隣
接する他のインナリード１２ｂよりも半導体チップ１４
から離隔された位置となっている。そして、各インナリ
ード１２ａ、１２ｂはボンディングワイヤ１５によって
半導体チップ１４の電極と接続されるが、インナリード
１２ａ、１２ｂが段差をもって配設されるだめ、隣接す
るインナリードどうしおよびボンディングワイヤとは高
さが異なり、インナリードどうしが接触する危険が少な
くなる他、封止樹脂の際にワイヤ流れを起こしても隣接
するボンディングワイヤが相互に接触することがない。That is, the other inner leads 12b are located on the same plane as the bed 13 of the lead frame, and the tip of the negative inner lead 12a is located at a higher position than the bed 13. Such a step can be formed, for example, by bending the inner lead 7a at a higher position by press working when punching the lead frame. By such processing, the tip of the bent inner lead 12a is closer to the semiconductor chip 14 than the other adjacent inner lead 12b.
It is located far away from. Each inner lead 12a, 12b is connected to an electrode of the semiconductor chip 14 by a bonding wire 15, but since the inner leads 12a, 12b are disposed with a difference in level, adjacent inner leads and bonding wires are at a different height. This reduces the risk of the inner leads coming into contact with each other, and also prevents adjacent bonding wires from coming into contact with each other even if the wires flow during sealing resin.

したがってリード間隔を従来よりも狭めることが可能と
なる。Therefore, the lead spacing can be narrower than before.

このようなワイヤボンディングにおいては、低い位置の
インナリード１２ｂをまず接続し、次いで、高い位置の
インナリード１２ａを接続するのが作業を安全にかつ効
率的に行う上で好ましい。In such wire bonding, it is preferable to connect the lower inner leads 12b first and then connect the higher inner leads 12a in order to perform the work safely and efficiently.

また高い位置のインナリードのワイヤボンディングを安
定に行うためにインナリードの高低に合致した支持部を
備えた支持冶具を使用することができる。Further, in order to stably perform wire bonding of inner leads located at high positions, a support jig having a support portion that matches the height of the inner leads can be used.

なお、本発明においては、−のインナリード１２−ａと
屈曲された他のインナリード１２ｂとをそれらの先端が
半導体素子１４の外端から等距離になるように配設して
もよく、この場合には折曲される分だけ−のインナリー
ド１２を予め、長く形成しておくことによって可能とな
る。又、−のインナリード１２ａを他のインナリード１
２ｂよりも低い位置に形成してもよい。In the present invention, the negative inner lead 12-a and the other bent inner lead 12b may be arranged such that their tips are equidistant from the outer end of the semiconductor element 14. In some cases, this can be made possible by forming the inner lead 12 long enough to be bent in advance. In addition, the negative inner lead 12a is connected to the other inner lead 1.
It may be formed at a position lower than 2b.

また、実施例ではフラットパッケージについて本発明を
適用しているが、リードフレームを用いる他のパッケー
ジについても同様に本発明を適用することができる。Further, although the present invention is applied to a flat package in the embodiment, the present invention can be similarly applied to other packages using lead frames.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明にかかる半導体装置によれば
隣接づるインナリード間のワイヤ接続部を交互に高さを
異ならせて配設しているのでインナリード間のピッチを
小さくすることができると共に、隣接するインナリード
どうし、隣接するボンディングワイＶどうしが接触する
ことを有効に防止でき、不良率を低減させることができ
る。As explained above, according to the semiconductor device according to the present invention, since the wire connection parts between adjacent inner leads are arranged at different heights alternately, it is possible to reduce the pitch between the inner leads, and also to reduce the pitch between the inner leads. It is possible to effectively prevent adjacent inner leads from coming into contact with each other and between adjacent bonding wires V, thereby reducing the defective rate.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の透視平面図、第２図はその
断面図、第３図は従来装置の透視平面図、第４図の断面
図である。 ３．１３・・・ベッド、４．１４・・・半導体素子、５
゜１５・・・ボンディングワイヤ、１２ａ、１２ｂ・・
・インナリード。 出願人代理人　　猪　　股　　　　消 馬　１　図 ６２　図 も　３　図 ５４　図FIG. 1 is a perspective plan view of an embodiment of the present invention, FIG. 2 is a sectional view thereof, FIG. 3 is a perspective plan view of a conventional device, and FIG. 4 is a sectional view. 3.13...Bed, 4.14...Semiconductor element, 5
゜15...Bonding wire, 12a, 12b...
・Inner lead. Applicant's agent Inomata Masuma 1 Figure 62 Figure also 3 Figure 54 Figure

Claims (1)

【特許請求の範囲】 １、リードフレームのベッドにマウントされた半導体素
子と、この半導体素子の電極とボンディングワイヤで接
続され、前記ベッドの周囲に配設されたリードフレーム
の複数のインナリードとを具備してなる半導体装置にお
いて、 前記複数のインナリードのうち互いに隣接するインナリ
ード間でワイヤボンディング接続部の高さが交互に異な
っていることを特徴とする半導体装置。 ２、高い位置のインナリード先端部が低い位置のインナ
リード先端部よりも半導体素子外端からの距離が大きく
形成された特許請求の範囲第１項記載の半導体装置。[Claims] 1. A semiconductor device mounted on a bed of a lead frame, and a plurality of inner leads of the lead frame connected to electrodes of the semiconductor device with bonding wires and arranged around the bed. What is claimed is: 1. A semiconductor device comprising: a wire bonding connection portion having heights that are alternately different between adjacent inner leads among the plurality of inner leads. 2. The semiconductor device according to claim 1, wherein the inner lead tip portion at a higher position is formed at a greater distance from the outer end of the semiconductor element than the tip portion of the inner lead at a lower position.
JP60139863A 1985-06-26 1985-06-26 Semiconductor device Pending JPS621239A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60139863A JPS621239A (en) 1985-06-26 1985-06-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60139863A JPS621239A (en) 1985-06-26 1985-06-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS621239A true JPS621239A (en) 1987-01-07

Family

ID=15255296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60139863A Pending JPS621239A (en) 1985-06-26 1985-06-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS621239A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0320997A2 (en) * 1987-12-17 1989-06-21 Kabushiki Kaisha Toshiba Semiconductor device having a lead frame
WO1996019828A1 (en) * 1994-12-21 1996-06-27 Vlsi Technology, Inc. Wirebond lead system with improved wire separation
US7102216B1 (en) * 2001-08-17 2006-09-05 Amkor Technology, Inc. Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0320997A2 (en) * 1987-12-17 1989-06-21 Kabushiki Kaisha Toshiba Semiconductor device having a lead frame
WO1996019828A1 (en) * 1994-12-21 1996-06-27 Vlsi Technology, Inc. Wirebond lead system with improved wire separation
US7102216B1 (en) * 2001-08-17 2006-09-05 Amkor Technology, Inc. Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making

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