JPH0496356A - Lead frame for resin seal type semiconductor device - Google Patents

Lead frame for resin seal type semiconductor device

Info

Publication number
JPH0496356A
JPH0496356A JP2213857A JP21385790A JPH0496356A JP H0496356 A JPH0496356 A JP H0496356A JP 2213857 A JP2213857 A JP 2213857A JP 21385790 A JP21385790 A JP 21385790A JP H0496356 A JPH0496356 A JP H0496356A
Authority
JP
Japan
Prior art keywords
leads
semiconductor element
lead
island
thin metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2213857A
Other languages
Japanese (ja)
Inventor
Kenji Ooyachi
賢治 大谷内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2213857A priority Critical patent/JPH0496356A/en
Publication of JPH0496356A publication Critical patent/JPH0496356A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To decrease the manhours for correction, to lower manufacturing cost, to relax the limitation of the arrangement of pads on a semiconductor element and leads and to facilitate a design by forming a groove for supporting a metallic small-gage wire at the front end of the bent lead. CONSTITUTION:A lead frame is composed of an island 1, on which a semiconductor element 6 is loaded, and a plurality of leads 2, which are disposed around the island 1 and front end sections 2A are bent upward. V-shaped grooves 7 are formed particularly at the front end sections 2A of the leads so as to support metallic small-gage wires for connecting the pads of the semiconductor element 6 and the leads 2. According to such constitution, the metallic small- gage wires bonding the pads of the semiconductor element 6 loaded on the island 1 and the leads 2 are supported by the V-shaped grooves 7 formed at the front end sections 2A of the leads 2. Consequently even when the number of the leads 2 is increased, the metallic small-gage wires can be supported positively, thus preventing contacts among the metallic small-gage wires and the end sections of the semiconductor element 6.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型半導体装置用リードフレームに関し
、特にリード先端部の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for a resin-sealed semiconductor device, and particularly to the structure of a lead tip.

〔従来の技術〕[Conventional technology]

従来の樹脂封止型半導体装置用リードフレーム（以下単
にリードフレームという）を用いた半導体装置は第２図
に示すように、中央のアイランド１上に配置される半導
体素子６の周囲に、複数のリード２の一端を並べた構造
になっている。そして、このリード２は、半導体素子６
に近い端と他の部分とも同じ高さとなっている。このよ
うな構造でリード２の一端と、このリード２に対応する
半導体素子６のパッド５とを金属細線３で接続し、この
構造体をリード２の他端を露出させて樹脂４で封止して
半導体装置を完成させていた。As shown in FIG. 2, a semiconductor device using a conventional lead frame for a resin-sealed semiconductor device (hereinafter simply referred to as a lead frame) has a plurality of semiconductor elements 6 arranged on a central island 1. It has a structure in which one end of the lead 2 is lined up. This lead 2 is connected to the semiconductor element 6.
The end closest to the top and the other parts are at the same height. With this structure, one end of the lead 2 and the pad 5 of the semiconductor element 6 corresponding to this lead 2 are connected with a thin metal wire 3, and this structure is sealed with a resin 4 with the other end of the lead 2 exposed. He completed the semiconductor device.

この場合、パッド５が半導体素子６の周辺部から離れた
位置にあるか、あるいは金属細！３が長いと、金属細線
３が半導体素子６の端部に接触し易くなるため、第３図
に示すように、リード２の半導体素子６に近い先端部２
Ａを上方に折り曲げて金属細線を高くし、接触を防止す
る構造のものもあった。In this case, the pad 5 may be located away from the periphery of the semiconductor element 6, or it may be a thin metal pad. If lead 3 is long, the thin metal wire 3 will easily come into contact with the end of the semiconductor element 6, so as shown in FIG.
Some had a structure in which A was bent upward to raise the height of the thin metal wire to prevent contact.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のリードフレームを用いた樹脂封止型半導
体装置では、半導体素子６上のパッド５とリード２を金
属細線３で接続する際に、パッド５が半導体素子６の周
辺部から３００μｍ以上離れた位置にあるか、あるいは
金属細線が長い場合には、第２図に示したように、半導
体素子の端部と金属細線３が接触し易いという問題があ
った。In the resin-sealed semiconductor device using the conventional lead frame described above, when connecting the pads 5 on the semiconductor element 6 and the leads 2 with the thin metal wires 3, the pads 5 are separated from the periphery of the semiconductor element 6 by 300 μm or more. If the thin metal wire 3 is located at a lower position or the thin metal wire 3 is long, as shown in FIG.

このため金属細線にて結線後、金属細線の状態を検査し
修正を行う必要があるが、この修正工数の為製造原価が
高くなると共に、修正作業中に金属細線３を破壊し歩留
りを低下させるという欠点がある。さらに、半導体素子
設計にあたって電極の配置の制限が厳しくなるため、設
計の自由度が少なくなるという欠点もあった。For this reason, after connecting with thin metal wires, it is necessary to inspect the condition of the thin metal wires and make corrections, but this correction process increases manufacturing costs and also destroys the thin metal wires 3 during the correction work, reducing yield. There is a drawback. Furthermore, there is a drawback that the degree of freedom in design is reduced because restrictions on the arrangement of electrodes are severely restricted when designing a semiconductor device.

また、第３図に示したように、リード２の先端部を高く
した場合においても、パッド５の数及びリード２の数が
増加するのに伴なって、金属細線３がリードの先端部２
Ａを通る様に設計するのが困難となり、さらに設計の自
由度が少なくなるという欠点があった。Further, as shown in FIG. 3, even when the tip of the lead 2 is made higher, as the number of pads 5 and the number of leads 2 increase, the thin metal wire 3 increases the height of the tip of the lead.
There was a drawback that it became difficult to design so as to pass through A, and the degree of freedom in design was further reduced.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の樹脂封止型半導体装置用リードフレームは、半
導体素子を搭載するアイランドと、このアイランドの周
囲に配置され先端が上方に折り曲げられた複数のリード
とを有する樹脂封止型半導体装置用リードフレームにお
いて、前記リードの先端部に金属細線を支持するための
溝を設けたものである。A lead frame for a resin-sealed semiconductor device according to the present invention includes an island on which a semiconductor element is mounted, and a plurality of leads arranged around the island and whose tips are bent upward. In the frame, a groove for supporting a thin metal wire is provided at the tip of the lead.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図（ａ）、（ｂ）は本発明の一実施例の断面図及び
リード先端部の正面図である。FIGS. 1(a) and 1(b) are a sectional view and a front view of a lead tip of an embodiment of the present invention.

第１図（ａ）、（ｂ）において、リードフレームは半導
体素子６を搭載するアイランド１と、このアイランド１
の周囲に配置され先端部２Ａが上方に折り曲げられた複
数のり−ド２とから主に構成され、特にこのリードの先
端部２Ａには、半導体素子６のパッドとリード２とを接
続するための金属細線を支持できるように、■字型の渭
７が設けである。In FIGS. 1(a) and 1(b), the lead frame includes an island 1 on which a semiconductor element 6 is mounted, and an island 1 on which a semiconductor element 6 is mounted.
It is mainly composed of a plurality of leads 2 arranged around the lead 2 and having a tip 2A bent upward.In particular, the tip 2A of the lead has a wire for connecting the pad of the semiconductor element 6 and the lead 2. ■-shaped arms 7 are provided to support the thin metal wire.

このように構成された本実施例によれば、アイランド１
上に搭載された半導体素子６のパッドとり−ド２とを接
続する金属細線は、リード２の先端部２Ａに形成された
Ｖ字型の渭７により支持されるため、リード２の数が増
えた場合でも金属細線を確実に支持できるため、金属細
線と半導体素子６の端部との接触をなくすことができる
。According to this embodiment configured in this way, the island 1
The thin metal wire connecting the pad lead 2 of the semiconductor element 6 mounted above is supported by the V-shaped arm 7 formed at the tip 2A of the lead 2, so the number of leads 2 increases. Since the thin metal wire can be reliably supported even when the thin metal wire is exposed, contact between the thin metal wire and the end of the semiconductor element 6 can be eliminated.

尚、上記実施例においては、リードの先端部に形成する
渭をＶ字型の溝とした場合について説明したが、これに
限定されるものではなく、Ｕ字型等金属細線を支持でき
るものであれば、どんな形の溝であってもよい。In the above embodiment, the case where the edge formed at the tip of the lead is a V-shaped groove has been described, but the groove is not limited to this, and it may be a U-shaped groove that can support a thin metal wire. If there is a groove, it can be of any shape.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、折り曲げたリードの先端
部に金属細線を支持するための溝を設けることにより、
パッドが半導体素子の周辺部がら離れた位置に存在する
場合や、金属細線が長い場合においても、半導体素子の
端部と金属細線が接触することを防止できるため、金属
細線にて結線した後金属細線が接触しているか否かを検
査する必要がなくなり、またそれに伴い金属細線の修正
作業も必要でなくなるため、修正工数が削減でき製造原
価を下げることができる。また修正が不要となる為修正
時に金属細線を破壊することによる歩留りの低下を皆無
とすることができる。As explained above, the present invention provides a groove for supporting a fine metal wire at the tip of a bent lead.
Even if the pad is located far away from the periphery of the semiconductor element or the thin metal wire is long, contact between the edge of the semiconductor element and the thin metal wire can be prevented. There is no need to inspect whether the thin wires are in contact with each other, and there is also no need to repair the thin metal wires, so the number of repair steps can be reduced and manufacturing costs can be lowered. Further, since no correction is required, there is no reduction in yield due to destruction of the thin metal wire during correction.

さらに、溝に金属細線が入り込むため、後工程で振動等
により金属細線がたれ下がることがない為、取り扱いが
簡単になり振動防止を考える必要のない安価な半導体装
置が得られる。Furthermore, since the thin metal wires are inserted into the grooves, the thin metal wires do not sag due to vibrations or the like in the subsequent process, so that handling becomes easy and an inexpensive semiconductor device that does not require consideration of vibration prevention can be obtained.

またパッド及びリードの数が多い場合においても、金属
細線がリードの先端部を通るように設計する必要がなく
、パッドとリードが位置的に離れていても問題とならな
い為、半導体素子上のバットの配置の制限及びリードの
配置の制限が大幅に緩和され、半導体装置の設計が容易
になるという効果もある。In addition, even when there are a large number of pads and leads, there is no need to design so that the thin metal wire passes through the tip of the lead, and there is no problem even if the pads and leads are located apart, so the batts on the semiconductor element This also has the effect that the restrictions on the arrangement of the leads and the restrictions on the arrangement of the leads are significantly relaxed, making it easier to design the semiconductor device.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ＞、（ｂ）は大発明の一実施例の断面図及び
リード先端部の正面図、第２図及び第３図は従来のリー
ドフレームを用いた場合の樹脂封正型半導体装置の断面
図である。 １・・・アイランド、２・・・リード、２Ａ・・・先端
部、３・・・金属細線、４・・・樹脂、５・・・パッド
、６・・・半導体素子、７・・・Ｖ字型の渭。Figure 1 (a>, (b) is a cross-sectional view of an embodiment of the great invention and a front view of the lead tip, and Figures 2 and 3 are resin-sealed semiconductors using a conventional lead frame. It is a sectional view of the device. 1... Island, 2... Lead, 2A... Tip, 3... Metal thin wire, 4... Resin, 5... Pad, 6... Semiconductor. Element, 7...V-shaped wave.

Claims (1)

【特許請求の範囲】[Claims] 　半導体素子を搭載するアイランドと、このアイランド
の周囲に配置され先端が上方に折り曲げられた複数のリ
ードとを有する樹脂封止型半導体装置用リードフレーム
において、前記リードの先端部に金属細線を支持するた
めの溝を設けたことを特徴とする樹脂封止型半導体装置
用リードフレーム。In a lead frame for a resin-sealed semiconductor device that has an island on which a semiconductor element is mounted and a plurality of leads arranged around the island and whose tips are bent upward, thin metal wires are supported at the tips of the leads. A lead frame for a resin-sealed semiconductor device, characterized by having a groove for cleaning.
JP2213857A 1990-08-13 1990-08-13 Lead frame for resin seal type semiconductor device Pending JPH0496356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2213857A JPH0496356A (en) 1990-08-13 1990-08-13 Lead frame for resin seal type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2213857A JPH0496356A (en) 1990-08-13 1990-08-13 Lead frame for resin seal type semiconductor device

Publications (1)

Publication Number Publication Date
JPH0496356A true JPH0496356A (en) 1992-03-27

Family

ID=16646172

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2213857A Pending JPH0496356A (en) 1990-08-13 1990-08-13 Lead frame for resin seal type semiconductor device

Country Status (1)

Country Link
JP (1) JPH0496356A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5955778A (en) * 1996-10-08 1999-09-21 Nec Corporation Lead frame with notched lead ends
WO2005067041A1 (en) * 2003-08-13 2005-07-21 Tian Siang Yip Wire-bonded integrated circuit package and manufacturing method thereof
US7898067B2 (en) * 2008-10-31 2011-03-01 Fairchild Semiconductor Corporaton Pre-molded, clip-bonded multi-die semiconductor package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5955778A (en) * 1996-10-08 1999-09-21 Nec Corporation Lead frame with notched lead ends
WO2005067041A1 (en) * 2003-08-13 2005-07-21 Tian Siang Yip Wire-bonded integrated circuit package and manufacturing method thereof
US7898067B2 (en) * 2008-10-31 2011-03-01 Fairchild Semiconductor Corporaton Pre-molded, clip-bonded multi-die semiconductor package

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