JPH04188660A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPH04188660A
JPH04188660A JP2313603A JP31360390A JPH04188660A JP H04188660 A JPH04188660 A JP H04188660A JP 2313603 A JP2313603 A JP 2313603A JP 31360390 A JP31360390 A JP 31360390A JP H04188660 A JPH04188660 A JP H04188660A
Authority
JP
Japan
Prior art keywords
island
semiconductor chip
side wall
lead frame
brazing material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2313603A
Other languages
Japanese (ja)
Inventor
Takashi Okumura
奥村　敬司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP2313603A priority Critical patent/JPH04188660A/en
Publication of JPH04188660A publication Critical patent/JPH04188660A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent brazing material from flowing out to the back of an island and to enable a bonding wire to be prevented from coming into contact with the end of a semiconductor chip by a method wherein the island is provided with a side wall at its peripheral part and an insulator formed at the upper end of the side wall concerned. CONSTITUTION:An island 3 is supported by suspension pins 4 connected to the upper end of a side wall 6 at the outer frame of a lead frame, and inner leads 7 are arranged around the island 3 to constitute the lead frame. At this point, the front side of an insulator 1 is formed higher than that of a semiconductor chip 2 mounted on the island 3. By this setup, the semiconductor chip 2 is mounted on the inner base of the island 3 with a brazing material 5, and when the semiconductor chip 2 is electrically connected to the inner leads 7 with bonding wires 8 to assemble a semiconductor device, brazing material can be prevented from flowing to the back of the island 3 and the bonding wires 8 can be prevented from coming into contact with the end of a semiconductor chip or each other even if the bonding wires 8 sag.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用リードフレームに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to lead frames for semiconductor devices.

〔従来の技術〕[Conventional technology]

従来のリードフレームは板状のアイランドとアイランド
の周囲に配列して設けた内部リードを外枠により支持す
るように金属板よりプレスで打抜き形成していた。A conventional lead frame is formed by stamping a metal plate using a press so that a plate-shaped island and internal leads arranged around the island are supported by an outer frame.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のリードフレームのアイランドは平坦な板
状に形成されているので、半導体チップをアイランド上
ヘマウントする際に使用するろう材がアイランドの裏面
へ回り込むという欠点がある。Since the island of the above-mentioned conventional lead frame is formed into a flat plate shape, there is a drawback that the brazing material used when mounting a semiconductor chip onto the island wraps around to the back surface of the island.

また、従来のリードフレームはワイヤーボンディングの
際ボンディング線のたるみ等が発生した場合、ホンディ
ング線と半導体チップの端部との接触または内部リード
相互間の接触による短絡を生ずるという問題点があった
。In addition, conventional lead frames have had the problem that if slack in the bonding wire occurs during wire bonding, short circuits may occur due to contact between the bonding wire and the edge of the semiconductor chip or contact between internal leads. .

〔課題を解決するための手段〕[Means to solve the problem]

本発明のリードフレームは、外枠に吊りピンで支持され
たアイランドと、前記アイランドの周囲に配置された内
部リードとを有する半導体装置用のリードフレームにお
いて、前記アイランドが周縁部に設けた側壁と前記側壁
の上端部に設けた絶縁体を備えている。The lead frame of the present invention is a lead frame for a semiconductor device having an island supported by hanging pins on an outer frame, and internal leads disposed around the island, wherein the island has a side wall provided at a peripheral portion thereof. An insulator is provided at the upper end of the side wall.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図（ａ）、（ｂ）は本発明の平面図及びＡ−Ａ′線
断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line A-A' of the present invention.

第１図（ａ＞、（ｂ）に示すように、周縁部に設けた側
壁６の上端部にポンチインク線と側壁の接触を防ぐため
の絶縁体１を設けた箱形のアイランド３が吊りピン４に
よりリードフレームの外枠（図示せず）に支持され、ア
イランド３の周囲に内部リード７を配置してリードフレ
ームを構成する。ここで、絶縁体１の上面はマウントさ
れる半導体チップの上面よりも高く形成する。As shown in FIGS. 1(a) and 1(b), a box-shaped island 3 is suspended from the upper end of a side wall 6 provided at the periphery and is provided with an insulator 1 to prevent contact between the punch ink line and the side wall. It is supported by an outer frame (not shown) of the lead frame by pins 4, and internal leads 7 are arranged around the island 3 to form the lead frame. Form higher than the top surface.

アイランド３の内部底面にろう材５を用いて半導体チッ
プ２をマウントし、半導体チップ２と内部リード７との
間をボンディング線８で電気的に接続して半導体装置の
組立を行う場合に、ボンディング線８のたるみが生じて
もボンディング線８は半導体チップ２よりも高い位置に
ある絶縁体１により半導体チップ２の端部に接触するこ
とを防止することができる。Bonding is used when assembling a semiconductor device by mounting the semiconductor chip 2 on the inner bottom surface of the island 3 using a brazing material 5 and electrically connecting the semiconductor chip 2 and the internal leads 7 with bonding wires 8. Even if the wire 8 becomes slack, the bonding wire 8 can be prevented from contacting the end of the semiconductor chip 2 by the insulator 1 located at a higher position than the semiconductor chip 2.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明はアイランド周縁部に側壁
を設け、側壁の上端部に絶縁体を設けることにより、ろ
う材のアイランド裏面への回り込みを防止でき、 また、ボンディング線のたるみが発生した場合にもボン
ティング線と半導体チップの端部との接触やボンディン
グ線相互間の接触を防止することができるという効果を
有する。As explained above, in the present invention, by providing a side wall at the peripheral edge of the island and providing an insulator at the upper end of the side wall, it is possible to prevent the brazing material from going around to the back surface of the island, and also to prevent the occurrence of slack in the bonding wire. Even in such cases, it is possible to prevent contact between the bonding wires and the ends of the semiconductor chip or between the bonding wires.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）、（ｂ）は本発明の平面図、及びＡ−Ａ’
線断面図である。 １・・・絶縁体、２・・・半導体チップ、３・・・アイ
ランド、４・・・吊りビン、５・・・ろう材、６・・・
側壁、７・・・内部リード、８・・・ホンディング線。FIGS. 1(a) and 1(b) are plan views of the present invention, and A-A'
FIG. DESCRIPTION OF SYMBOLS 1... Insulator, 2... Semiconductor chip, 3... Island, 4... Hanging bottle, 5... Brazing material, 6...
Side wall, 7...internal lead, 8...honding wire.

Claims (1)

【特許請求の範囲】[Claims] 外枠に吊りピンで支持たれたアイランドと、前記アイラ
ンドの周囲に配置された内部リードとを有する半導体装
置用のリードフレームにおいて、前記アイランドが周縁
部に設けた側壁と、前記側壁の上端部に設けた絶縁体を
備えていることを特徴とするリードフレーム。In a lead frame for a semiconductor device having an island supported by hanging pins on an outer frame and internal leads arranged around the island, the island has a side wall provided at a peripheral edge and an upper end of the side wall. A lead frame comprising an insulator provided therein.
JP2313603A 1990-11-19 1990-11-19 Lead frame Pending JPH04188660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2313603A JPH04188660A (en) 1990-11-19 1990-11-19 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2313603A JPH04188660A (en) 1990-11-19 1990-11-19 Lead frame

Publications (1)

Publication Number Publication Date
JPH04188660A true JPH04188660A (en) 1992-07-07

Family

ID=18043306

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2313603A Pending JPH04188660A (en) 1990-11-19 1990-11-19 Lead frame

Country Status (1)

Country Link
JP (1) JPH04188660A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07221250A (en) * 1994-01-31 1995-08-18 Nec Kyushu Ltd Lead frame
WO2016182425A1 (en) * 2015-05-14 2016-11-17 Chee Yang Ng A lead frame for selective soldering

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07221250A (en) * 1994-01-31 1995-08-18 Nec Kyushu Ltd Lead frame
WO2016182425A1 (en) * 2015-05-14 2016-11-17 Chee Yang Ng A lead frame for selective soldering

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