JPS6173344A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6173344A JPS6173344A JP59195349A JP19534984A JPS6173344A JP S6173344 A JPS6173344 A JP S6173344A JP 59195349 A JP59195349 A JP 59195349A JP 19534984 A JP19534984 A JP 19534984A JP S6173344 A JPS6173344 A JP S6173344A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- semiconductor element
- island
- ring
- sagging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
この発明はダイボンディングされた半導体素子とインナ
ーリードとの間を例えば、極細の金線でワイヤボンディ
ングされる半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a semiconductor device in which wire bonding is performed between a die-bonded semiconductor element and an inner lead using, for example, a very thin gold wire.
（ロ）従来技術
この種の半導体装置において、半導体素子とインナーリ
ード先端までの距離が長くなると、これに伴いワイヤボ
ンディングされる金線の長さも長くなる。その結果、ワ
イヤボンディングの際に金線が垂れて半導体素子のコー
ナや、半導体素子がダイボンディングされている金属片
（アイランド）のコーナに接触することがある。このよ
うなワイヤ・タッチが発生するとショート不良となるた
め、半導体装置の歩留り低下を招来する。また、ワイヤ
・タッチを生じたものをトランスファーモールドすると
、その接触部分が周囲温度によって導通あるいは遮断状
態となる。そのためこのようなワイヤー・タッチを測定
試験で完全に除去することは困難である。測定で除去さ
れなかった装置は、市場で不良となる場合もあるから、
ワイヤー・タッチは半導体装置の歩留りのみならず、そ
の信頼性を著しく低下させる原因となる。(B) Prior Art In this type of semiconductor device, as the distance between the semiconductor element and the tip of the inner lead increases, the length of the gold wire used for wire bonding also increases. As a result, during wire bonding, the gold wire may hang down and come into contact with the corner of the semiconductor element or the corner of the metal piece (island) to which the semiconductor element is die-bonded. When such a wire touch occurs, a short circuit occurs, resulting in a decrease in the yield of semiconductor devices. Furthermore, when a wire touch is applied to a wire by transfer molding, the contact portion becomes conductive or disconnected depending on the ambient temperature. Therefore, it is difficult to completely eliminate such wire touches in measurement tests. Devices that are not removed during measurement may become defective on the market.
Wire touching causes not only a decrease in the yield of semiconductor devices but also a significant decrease in their reliability.
そこで、従来ワイヤータッチを防止する種々の手段が提
案実施されている。例えば、
■ リードフレームのアイランド部分がインナーリード
先端よりも下になるように、アイランド・サポートを折
り曲げ加工したもの、
■ いわゆるチンプキアリアＩＣ等のようにセラミック
パッケージを使用するものにあっては、基板表面のグイ
ボンデング部分に凹部を形成したもの等がある。Therefore, various means for preventing wire touch have been proposed and implemented. For example, ■ The island support is bent so that the island part of the lead frame is below the tip of the inner lead. ■ In the case of a ceramic package such as a so-called Chimpchiaria IC, the board surface There are some that have a recess formed in the guibondeng part.
このようにグイボンデングされた状態で半導体表面とイ
ンナーリードとの落差が小さいと、ワイヤが多少型れて
も素子のコーナ等にワイヤが接触することが少なくなる
。If the height difference between the semiconductor surface and the inner lead is small in the bonded state as described above, even if the wire is slightly bent, the wire is less likely to come into contact with the corners of the element.
しかしながら、このようなリードフレームやパッケージ
であっても、製造コストをおさえるために、形状の異な
る多種類の半導体素子を積載できるように、前記アイラ
ンド等の寸法を太き（しておくのが普通である。そのた
め、かかるリードフレーム等に寸法の小さい半導体素子
が積載されると必然的にワイヤーが長くなる結果、ワイ
ヤの垂れが著しくなる。そのため、前述した手段だけで
は充分ワイヤー・タッチを防止することができない。However, even in such lead frames and packages, in order to reduce manufacturing costs, the dimensions of the islands, etc. are usually made thicker so that many types of semiconductor elements with different shapes can be loaded. Therefore, when small-sized semiconductor elements are mounted on such a lead frame, etc., the wires inevitably become long, resulting in significant wire sagging.Therefore, the above-mentioned measures alone are not sufficient to prevent wire touching. I can't.
（ハ）目的
この発明はワイヤ垂れによるワイヤと半導体素子コーナ
等との接触を有効に防止できる半導体装置を提供するこ
とを目的としている。(C) Objective The object of the present invention is to provide a semiconductor device that can effectively prevent contact between a wire and a corner of a semiconductor element due to wire sagging.
（ニ）構成
この発明に係る半導体装置は、グイボンデングされた半
導体素子と、前記半導体素子の周囲に配設されるインナ
ーリード先端部との間に、その半導体素子表面と略同じ
高さの絶縁リングを固着し、この半導体素子とインナー
リードとの間をワイヤーボンディングしてなることを特
徴としている。(D) Structure The semiconductor device according to the present invention is provided with an insulating ring approximately at the same height as the surface of the semiconductor element, between a semiconductor element that has been bonded and an inner lead tip disposed around the semiconductor element. The semiconductor element is fixed to the inner lead, and wire bonding is performed between the semiconductor element and the inner lead.
（ホ）実施例
第１図はこの発明に係る半導体装置の一実施例の構成を
略示した説明図であり、同図（ａ）はその断面図、同図
（ｂｌは平面図を示している。(E) Embodiment FIG. 1 is an explanatory diagram schematically showing the structure of an embodiment of a semiconductor device according to the present invention, in which FIG. 1A is a sectional view thereof, and FIG. There is.
同図において、■はアイランドであり、このアイランド
１には例えば、金シリコン合金、根ペースト等のプリフ
ォーム剤２を介在させて半導体素子３がグイボンディン
グされる。In the figure, ■ is an island, and a semiconductor element 3 is bonded to this island 1 with a preform agent 2 such as a gold-silicon alloy or root paste interposed therebetween.
４はアイランド１の周囲に配設され、半導体素子３との
間を極細の金線５でワイヤボンディングされるインナー
リードである。このインナーリード４及びアイランド１
等は例えば、４２Ｎ ｉ合金あるいは銅合金等の薄板を
打抜き等によって一体に形成される。また、アイランド
１はインナーリード４よりも低くなるように、その支持
部材が下方に折り曲げられている。Reference numeral 4 denotes an inner lead arranged around the island 1 and wire-bonded to the semiconductor element 3 using a very thin gold wire 5. This inner lead 4 and island 1
For example, they are integrally formed by punching a thin plate of 42N i alloy or copper alloy. Further, the supporting member of the island 1 is bent downward so that it is lower than the inner lead 4.
６は半導体素子３とインナーリード４との間に固着され
る絶縁リングである。この絶縁り°フグ６は耐熱性のあ
る例えば絶縁性エポキシ系樹脂等で形成される。垂れた
金線にＴＭ （Ｉｉを与えないようにするために絶縁リ
ング６の上面角部には面取りが施されている。また、ワ
イヤボンディングの際にキャピラリの先端と接触するの
を防止するために、絶縁リング６の高さは半導体素子３
の表面と略同じ高さに設定するのが望ましい。この絶縁
リング６は半導体素子３がグイポンディグされた後、耐
熱性のあるエポキシ系接着剤でアイランド１に固着され
る。Reference numeral 6 denotes an insulating ring fixed between the semiconductor element 3 and the inner lead 4. The insulating puffer fish 6 is made of a heat-resistant material such as an insulating epoxy resin. The top corner of the insulating ring 6 is chamfered to prevent TM (Ii) from being applied to the hanging gold wire. Also, to prevent it from coming into contact with the tip of the capillary during wire bonding. The height of the insulating ring 6 is the height of the semiconductor element 3.
It is desirable to set it at approximately the same height as the surface. After the semiconductor element 3 is bonded, the insulating ring 6 is fixed to the island 1 with a heat-resistant epoxy adhesive.
しかして、ワイヤボンディングの際に金線５′が同図（
ａｌのように垂れても、絶縁リング６の角部で支持され
るから、それ以上型れるのを防止される。なお、この絶
縁リング６は丸形だけでなく、多角形でもよい。However, during wire bonding, the gold wire 5' is
Even if it sag like Al, it is supported by the corners of the insulating ring 6, so it is prevented from further deforming. Note that this insulating ring 6 may be not only round but also polygonal.
第２図はその他の実施例を示す説明図である。FIG. 2 is an explanatory diagram showing another embodiment.
同図において第１図と同一部分は同一符号で示している
。In this figure, the same parts as in FIG. 1 are indicated by the same reference numerals.
同図（ａｌは、厚膜印刷によってインナーリード４が形
成された例えばセラミ’７り基板１０に半導体素子３が
組み込まれる場合、同図（ｂ）はアイランドが下方へ折
り曲げられていないリードフレームを使用した場合の例
をそれぞれ示している。The figure (al) shows a lead frame in which the semiconductor element 3 is assembled into, for example, a ceramic substrate 10 on which the inner leads 4 are formed by thick film printing, and the figure (b) shows a lead frame in which the islands are not bent downward. Examples of their use are shown below.
同図（ｂ）よりわかるように、比較的大きいアイランド
１に小さい半導体素子３が載る場合であっても、絶縁リ
ング６によってワイヤの垂れが防止される。As can be seen from FIG. 3B, even when a small semiconductor element 3 is mounted on a relatively large island 1, the insulating ring 6 prevents the wire from sagging.
（へ）効果
この発明はグイボンデングされた半導体素子と、前記半
導体素子の周囲に配設されるインナーリード先端部との
間に、その半導体素子表面と略同じ高さの絶縁リングを
固着しているから、ワイヤボンディングの際のワイヤ垂
れを防止できる。(F) Effect This invention has an insulating ring fixed at approximately the same height as the surface of the semiconductor element between a semiconductor element that has been bonded and the tip of an inner lead disposed around the semiconductor element. This prevents the wire from sagging during wire bonding.
したがって、この発明によればワイヤ垂れによリワイヤ
と半導体素子のコーナ等との接触を防止できるから、半
導体装置の製造歩留り及びその信頼性を向上することが
できる。Therefore, according to the present invention, it is possible to prevent contact between the rewire and the corners of the semiconductor element due to wire sag, and therefore it is possible to improve the manufacturing yield and reliability of the semiconductor device.
第１図はこの発明に係る半導体装置の一実施例の説明図
、第２図はその他の実施例の説明図である。
■・・・アイランド、３・・・半導体素子、４・・・イ
ンナーリード、５・・・金線、６・・・絶縁リング。FIG. 1 is an explanatory diagram of one embodiment of a semiconductor device according to the present invention, and FIG. 2 is an explanatory diagram of another embodiment. ■... Island, 3... Semiconductor element, 4... Inner lead, 5... Gold wire, 6... Insulating ring.
Claims (1)
素子の周囲に配設されるインナーリード先端部との間に
、その半導体素子表面と略同じ高さの絶縁リングを固着
し、この半導体素子とインナーリードとの間をワイヤー
ボンディングしてなることを特徴とする半導体装置。(1) An insulating ring having approximately the same height as the surface of the semiconductor element is fixed between the die-bonded semiconductor element and the tip of the inner lead disposed around the semiconductor element, and the semiconductor element and the inner A semiconductor device characterized by wire bonding between leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59195349A JPS6173344A (en) | 1984-09-17 | 1984-09-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59195349A JPS6173344A (en) | 1984-09-17 | 1984-09-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6173344A true JPS6173344A (en) | 1986-04-15 |
Family
ID=16339686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59195349A Pending JPS6173344A (en) | 1984-09-17 | 1984-09-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6173344A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100481927B1 (en) * | 1997-11-19 | 2005-08-11 | 삼성전자주식회사 | Semiconductor Package and Manufacturing Method |
| JP2016143710A (en) * | 2015-01-30 | 2016-08-08 | シチズンファインデバイス株式会社 | Wire connection structure of electronic component |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5051260A (en) * | 1973-09-07 | 1975-05-08 | ||
| JPS5624958A (en) * | 1979-08-07 | 1981-03-10 | Nec Kyushu Ltd | Lead frame for semiconductor device |
-
1984
- 1984-09-17 JP JP59195349A patent/JPS6173344A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5051260A (en) * | 1973-09-07 | 1975-05-08 | ||
| JPS5624958A (en) * | 1979-08-07 | 1981-03-10 | Nec Kyushu Ltd | Lead frame for semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100481927B1 (en) * | 1997-11-19 | 2005-08-11 | 삼성전자주식회사 | Semiconductor Package and Manufacturing Method |
| JP2016143710A (en) * | 2015-01-30 | 2016-08-08 | シチズンファインデバイス株式会社 | Wire connection structure of electronic component |
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