JPH0287636A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0287636A
JPH0287636A JP63241413A JP24141388A JPH0287636A JP H0287636 A JPH0287636 A JP H0287636A JP 63241413 A JP63241413 A JP 63241413A JP 24141388 A JP24141388 A JP 24141388A JP H0287636 A JPH0287636 A JP H0287636A
Authority
JP
Japan
Prior art keywords
wire
bonding
semiconductor element
lead
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63241413A
Other languages
Japanese (ja)
Inventor
Chikayuki Kato
加藤　周幸
Seiichi Nishino
西野　誠一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63241413A priority Critical patent/JPH0287636A/en
Publication of JPH0287636A publication Critical patent/JPH0287636A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01—Chemical elements
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To prevent contact accident of a bonding wire from being caused by a method wherein, a semiconductor device provided with the bonding wire used to electrically connect a pad on a semiconductor element to a lead, an electrical insulator is formed on the lead under the wire. CONSTITUTION:Bonding leads 4 at the tip of lead frames 2 are plated with gold in order to bond gold wires 5. An island 9 is formed in the center surrounded by the bonding leads 4; a small semiconductor element 1 which is by about 0.1mm smaller than the island 9 is attached to its surface by using a silver paste 6. The wires 5 electrically connect pads on the semiconductor element 1 to the bonding leads 4. As a condition to install a frame body 3, a wire length exceeding 2.5mm is especially effective because a hanging of 70% or higher is produced. A polyimide resin containing a high-purity and low-cost adhesive is used as a material for the frame body 3.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に係シ、特にボンディング部のワイ
ヤー保持を目的としたパッケージの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a structure of a package for holding wires at a bonding portion.

〔従来の技術〕[Conventional technology]

従来のこの種の半導体装置は、ワイヤー長が長くなった
り、ボンディングリードの幅が狭くなったりすると、ワ
イヤータレやワイヤーカール等の事故が発生し、ボンデ
ィング不良が多発する。これを防止するためにはバ、ケ
ージ設計上制限を設け、チップサイズに合わせたパッケ
ージを作製しなければならない。In conventional semiconductor devices of this type, when the wire length becomes long or the width of the bonding lead becomes narrow, accidents such as wire sagging and wire curling occur, resulting in frequent bonding defects. In order to prevent this, restrictions must be placed on the package design and a package must be manufactured to match the chip size.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前述した従来の半導体装置は、ボンディングワイヤー長
が長くなるとワイヤータレやワイヤーカール等が発生し
、ボンディングワイヤーが半導体素子の接続点以外の部
分に接触して、ショートしたり、隣りのワイヤーに接触
してショートしたりするというボンディング不良が発生
し、歩留シが低下するという欠点がある−０ゆえに、ワ
イヤー長を短かくしなければならない為、パッケージ設
計が制限され、多ビン化対応ができなくなる。In the conventional semiconductor devices mentioned above, when the length of the bonding wire becomes long, wire sagging and wire curling occur, and the bonding wire may come into contact with a part other than the connection point of the semiconductor element, causing a short circuit or contacting an adjacent wire. There is a disadvantage that bonding defects such as short circuits occur and the yield decreases.Since the wire length must be shortened, package design is restricted and it is not possible to support a large number of bins.

これらを対処する為にはチップサイズに応じて種々のパ
ッケージが心安となり、パッケージの種類が多くなると
いう欠点を有する。In order to deal with these problems, various packages are available depending on the chip size, but this has the disadvantage of increasing the number of types of packages.

本発明の目的は、前記欠点が解決され、ボンディングワ
イヤーの接触事故が発生しないようにした半導体装置を
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which the above-mentioned drawbacks are solved and contact accidents of bonding wires do not occur.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の構成は、半導体素子上のパッドとリードとを電
気的に接続するボンディングワイヤを備えた半導体装置
において、前記ワイヤ下の前記リード上に電気的絶縁体
を設けたことを特徴とする。The structure of the present invention is characterized in that, in a semiconductor device including a bonding wire that electrically connects a pad on a semiconductor element and a lead, an electrical insulator is provided on the lead below the wire.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の第１の実施例の半導体装置の内部を示
す上面図、第２図は第１図のＡ　−Ａ’線の断面図であ
る。これら図において、本実施例ではリードフレーム２
が厚さ０．２５　ｒｒｔｍの４２アロイからなる。リー
ドフレーム２先端のボンディングリード４には、金ワイ
ヤ−５との接合の為、０．３μｍ以上の金めつきを行な
っている。ボンディングリード４に囲まれた中央には、
８　ｒｒａｎ’乃至１３ｍｍ０のアイランド９があり、
その上面にアイランド９より、０．１　ｒｒｒｍ程度小
さい半導体素子１が銀ペースト６により取り付けである
。ワイヤ５は、半導体素子１上のパッドと、ボンディン
グリード４とを電気的に接続するものである。枠体３は
、チップサイズとアイランドサイズに合ったものを作成
する必要があるが、なるべく半導体素子１側にした方が
エッヂタッチ防止効果があるので、チップより１咽程大
きい内径であυ、幅は０．５　ｍにした。FIG. 1 is a top view showing the inside of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA' in FIG. 1. In these figures, in this embodiment, the lead frame 2
is made of 42 alloy with a thickness of 0.25 rrtm. The bonding lead 4 at the tip of the lead frame 2 is plated with gold to a thickness of 0.3 μm or more for bonding with the gold wire 5. In the center surrounded by bonding leads 4,
There is an island 9 of 8 rran' to 13mm0,
A semiconductor element 1 smaller than the island 9 by about 0.1 rrrm is attached to its upper surface using silver paste 6. The wire 5 electrically connects the pad on the semiconductor element 1 and the bonding lead 4. The frame 3 needs to be made to match the chip size and island size, but it is better to place it on the semiconductor element 1 side as much as possible to prevent edge touching, so the inner diameter should be about 1 inch larger than the chip. The width was 0.5 m.

又、高さは、マウントされた半導体素子１の高さ約０．
５圓よりＯ乃至０．４ｓｎ高くなる様につくり、５０μ
ｍ程度のエポキシ系樹脂で接着させる。Further, the height is approximately 0.0 mm higher than the height of the mounted semiconductor element 1.
Made to be 0 to 0.4sn higher than 5mm, 50μ
Glue with epoxy resin of about m.

枠体３を入れる条件は、ワイヤー長が２．５叫を越える
ような長い場合が、タレの発生が７０％以上になる為、
特に有効である。枠体３の材料には、高純度で安価な接
着剤付きのボリイはド樹脂を使用する。The condition for installing frame 3 is that if the wire length is longer than 2.5 mm, the occurrence of sagging will be more than 70%.
Particularly effective. As the material of the frame 3, a high-purity and inexpensive resin with adhesive is used.

ここで、リードフレーム２の材料としては、リン青銅、
コバール、４２７０イ、銅合金の内から、選ばれること
が好ましい。尚、第１図、第２図では、トランスモール
ドする前の半導体装置が示されている。Here, the material of the lead frame 2 is phosphor bronze,
Preferably, the material is selected from Kovar, 4270, and copper alloy. Note that FIGS. 1 and 2 show the semiconductor device before being transmolded.

本実施例において、工程や使用環境から使用する枠体３
又は角棒体７の材料は、１７５℃以上の耐熱性を有する
ものでかつ耐湿性等の信頼性もそこなわない材料を選択
する。本条件を満足するものとしてはポリイばド系樹脂
やＰＢＴ　（ポリブチレンテレフタレート）やＰＥＴ１
又は耐熱ガラエボの高純度品等がコスト面からも適して
いる。In this example, the frame 3 used due to the process and usage environment
Alternatively, the material for the square bar 7 is selected to be one that has heat resistance of 175° C. or higher and does not impair reliability such as moisture resistance. Examples of materials that satisfy this condition include polyibide resin, PBT (polybutylene terephthalate), and PET1.
Alternatively, high-purity products such as heat-resistant Gala Evo are suitable from a cost standpoint.

第３図は本発明の第２の実施例の半導体装置の断面図で
ある。同図において、本実施例は、構造的には前記第１
の実施例と同様であるが、ここでは角棒体７を、セラｄ
２りにし、耐熱性が４５０℃以上のものを使用する。リ
ードフレーム２と角棒体７との接着には、鉛ホウ酸系の
低融点ガラス３００℃以上で溶かし、結晶化させ、接着
させる。FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention. In the same figure, this embodiment is structurally similar to the first
This is the same as the embodiment, but here the square rod body 7 is
Use one with a heat resistance of 450°C or higher. To bond the lead frame 2 and the rectangular rod 7, lead-boric acid-based low melting point glass is melted at 300° C. or higher, crystallized, and bonded.

本実施例では４５０℃以上のＡｕ−８ｉ共共晶台による
半導体素子１のマウントが可能となり、前記第１の実施
例に劣らぬ効果がめった。In this embodiment, it is possible to mount the semiconductor element 1 using an Au-8i eutectic table at a temperature of 450 DEG C. or higher, and the effect is comparable to that of the first embodiment.

ここで、角棒体７としては、セラミックの他に、ガラス
やアルミニウムのアルマイト処理されたものであっても
よい。Here, the square bar 7 may be made of glass or alumite-treated aluminum in addition to ceramic.

尚、枠体３又は角棒体７は、絶縁物であり、電気的に全
く無害であり、かつパッケージ内に存在しても耐湿性が
耐熱性その他伯頼性に全く影響しない。The frame body 3 or the square rod body 7 is an insulator and is electrically harmless, and even if it exists in the package, its moisture resistance, heat resistance, and other reliability are not affected at all.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に、本発明は、半導体素子とパッケージ
とを電気的に接続するボンディングワイヤの下面に来る
様に、素子面又はパッケージ接線面より高い枠体又は角
棒体を取ジ付け、ボンディングを行なうことにより、ワ
イヤー長やボンディングリード幅の影響で発生するワイ
ヤータレやワイヤーカールの発生を無くすことができ、
ショート不良もなくなる為、多ビンパッケージの設計が
半導体素子の大きさに制限されず容易になり、ボンディ
ング工程での歩留９も飛障的に上昇する効果がある。ま
た、本発明は、キャビティサイズを太き目につくってお
けば、いくつものパッケージを作製する必要が無く、基
板コストも低減できる効果がある。As explained above, the present invention provides bonding by attaching a frame or a square bar higher than the element surface or package tangential surface so as to be on the lower surface of the bonding wire that electrically connects the semiconductor element and the package. By doing this, it is possible to eliminate wire sag and wire curl that occur due to the influence of wire length and bonding lead width.
Since short-circuit defects are eliminated, the design of a multi-bin package is not limited by the size of the semiconductor element and becomes easy, and the yield rate in the bonding process is significantly increased. Further, in the present invention, if the cavity size is made large, there is no need to manufacture many packages, and the cost of the substrate can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の第１の実施例の半導体装置のモールド
の前の状態を示す上面図、第２図は第１図の八−Ａ′線
に沿って切断して見た断面図、第３図は本発明の第２の
実施例の半導体装置のモールド前状態の断面図である。 １・・・・・・半導体素子、２・・・・・・リードフレ
ーム（−部分）、３・・・・・・枠体、４・・・・・・
ボンディングリード、５・・・・・・ボンディングワイ
ヤ、６・・・・・・銀ペースト、７・・・・・・角棒体
、８・・・・・・Ａｕ−８ｉ結合部、９・・・・・・ア
イランド。 代理人　弁理士　　内　原　　　晋1 is a top view showing the state of a semiconductor device according to a first embodiment of the present invention before being molded; FIG. 2 is a sectional view taken along line 8-A' in FIG. 1; FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention in a pre-molding state. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2... Lead frame (- part), 3... Frame, 4...
Bonding lead, 5...Bonding wire, 6...Silver paste, 7...Square rod, 8...Au-8i bonding portion, 9... ...island. Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】[Claims] 半導体素子上のパッドとリードとを電気的に接続するボ
ンディングワイヤを備えた半導体装置において、前記ワ
イヤ下の前記リード上に電気的絶縁体を設けたことを特
徴とする半導体装置。1. A semiconductor device comprising a bonding wire that electrically connects a pad on a semiconductor element and a lead, characterized in that an electrical insulator is provided on the lead below the wire.
JP63241413A 1988-09-26 1988-09-26 Semiconductor device Pending JPH0287636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63241413A JPH0287636A (en) 1988-09-26 1988-09-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63241413A JPH0287636A (en) 1988-09-26 1988-09-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0287636A true JPH0287636A (en) 1990-03-28

Family

ID=17073921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63241413A Pending JPH0287636A (en) 1988-09-26 1988-09-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0287636A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5461471A (en) * 1977-10-25 1979-05-17 Nec Corp Semiconductor device
JPS6060743A (en) * 1983-09-14 1985-04-08 Matsushita Electronics Corp Lead frame
JPH01124227A (en) * 1987-11-09 1989-05-17 Mitsubishi Electric Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5461471A (en) * 1977-10-25 1979-05-17 Nec Corp Semiconductor device
JPS6060743A (en) * 1983-09-14 1985-04-08 Matsushita Electronics Corp Lead frame
JPH01124227A (en) * 1987-11-09 1989-05-17 Mitsubishi Electric Corp Semiconductor device

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