JPH01124227A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01124227A JPH01124227A JP28256187A JP28256187A JPH01124227A JP H01124227 A JPH01124227 A JP H01124227A JP 28256187 A JP28256187 A JP 28256187A JP 28256187 A JP28256187 A JP 28256187A JP H01124227 A JPH01124227 A JP H01124227A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- semiconductor chip
- inner leads
- insulator
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000012212 insulator Substances 0.000 claims abstract description 19
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 229920005989 resin Polymers 0.000 abstract description 3
- 239000011347 resin Substances 0.000 abstract description 3
- 239000004642 Polyimide Substances 0.000 abstract description 2
- 239000000853 adhesive Substances 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 abstract description 2
- 229920006332 epoxy adhesive Polymers 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、半導体装置に係り、詳しくは、半導体装置の
パッケージ構造に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor device, and more particularly to a package structure of a semiconductor device.
〈従来の技術〉
従来の半導体装置を第３図、第４図に基づいて説明する
。第３図は平面図、第４図はそのＩＶ−Ｉ＋／線断面図
である。<Prior Art> A conventional semiconductor device will be explained based on FIGS. 3 and 4. FIG. 3 is a plan view, and FIG. 4 is a sectional view taken along the line IV-I+/.
これらの図において、符号３０はダイスバット、３１は
インナーリード、３２は半導体チップ、３３はワイヤで
ある。In these figures, numeral 30 is a die bat, 31 is an inner lead, 32 is a semiconductor chip, and 33 is a wire.
ダイスパッド３０上には、半導体チップ３２が ゛ロウ
剤（図示せず）により固着されている。ダイスパッド３
０の周囲には、外部リード３４と一体となったインナー
リード３１・・・が配設されている。A semiconductor chip 32 is fixed onto the die pad 30 with a wax (not shown). Dice pad 3
Inner leads 31 . . . , which are integrated with the outer leads 34 , are arranged around the inner leads 31 .
半導体チップ３２の表面電極３２ａとインナーリード３
１・・・とは、ワイヤ３３によって接続されている。こ
れら半導体装置全体は、外部リード３４を残して樹脂の
ような封止剤３５によって封止されている。Surface electrode 32a of semiconductor chip 32 and inner lead 3
1... are connected by wires 33. These semiconductor devices as a whole are sealed with a sealant 35 such as resin, except for the external leads 34.
〈発明が解決しようとする問題点〉
ところで、従来の半導体装置では、半導体チップ３２と
インナーリード３１・・・との接続用ワイヤ３３に金や
アルミニウムなどの細線が用いられており、この細線は
、腰が弱いため、その中途部が垂れ下がって半導体チッ
プ３２の端部やダイスパッド３０等の不要部分に接触し
てしまい、電気的にショートしてしまうという問題があ
った。<Problems to be Solved by the Invention> Incidentally, in conventional semiconductor devices, thin wires made of gold, aluminum, etc. are used for the connecting wires 33 between the semiconductor chip 32 and the inner leads 31, and the thin wires are Because of its weak strength, there was a problem in that the midway portion of the semiconductor chip 32 sagged and came into contact with unnecessary parts such as the end of the semiconductor chip 32 and the die pad 30, resulting in an electrical short circuit.
また、製造工程中にダイスパッド３０やインナーリード
３１・・・が変形して位置ずれを起こし、インナーリー
ド３１・・・と半導体チップ３２の表面電極３２ａとの
接続が困難になるという問題らあった。Additionally, there is the problem that the die pads 30 and the inner leads 31 are deformed and misaligned during the manufacturing process, making it difficult to connect the inner leads 31 with the surface electrodes 32a of the semiconductor chip 32. Ta.
本発明は、上述の問題点に鑑みてなされたものであって
、ワイヤと不要部分との接触を防いで電気的にショート
するのを防止するとともに、確実に半導体チップとイン
ナーリードとを接続できる半導体装置を提供することを
目的とする。The present invention has been made in view of the above-mentioned problems, and it is possible to prevent electrical short-circuits by preventing contact between wires and unnecessary parts, and to reliably connect semiconductor chips and inner leads. The purpose is to provide semiconductor devices.
く問題点を解決するための手段〉
本発明は、上記の目的を達成するために、ワイヤの下側
で、ダイスパッドの周縁上面とその周囲のインナーリー
ドの内端上面とにわたって絶縁体を設けて半導体装置を
構成し、好ましくは、前記絶縁体をダイスパッドとイン
ナーリードとにそれぞれ固着して半導体装置を構成した
。Means for Solving the Problems> In order to achieve the above object, the present invention provides an insulator on the lower side of the wire across the upper surface of the peripheral edge of the die pad and the upper surface of the inner end of the inner lead around it. Preferably, the insulator is fixed to a die pad and an inner lead to form a semiconductor device.
〈作用〉
上記構成によれば、ワイヤが半導体チップの表面電極と
インナーリードとの間で垂れ下がっても、その垂れ下が
り部分は、絶縁体によって受は止められるので、半導体
チップの端部やダイスパッド等の不要部分に接触しない
。また、絶縁体をダイスパッドおよび各インナーリード
の内端側に固着すると、ダイスパッドと各インナーリー
ドとは、変形せず位置ずれが起こらない。<Function> According to the above configuration, even if the wire hangs down between the surface electrode of the semiconductor chip and the inner lead, the hanging part is stopped by the insulator, so that the wire does not hang down between the edge of the semiconductor chip, the die pad, etc. Do not touch unnecessary parts of the Furthermore, if the insulator is fixed to the inner ends of the die pad and each inner lead, the die pad and each inner lead will not be deformed and will not be misaligned.
〈実施例〉
以下、本発明を図面に示す実施例に基づいて詳細に説明
する。第１図は本発明の一実施例を示す平面図、第２図
はその■−■線断面図である。<Example> Hereinafter, the present invention will be described in detail based on an example shown in the drawings. FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line ■--■.
これらの図において、符号１はダイスバット、２はイン
ナーリード、３は半導体チップ、４はワイヤ、５は絶縁
体である。In these figures, numeral 1 is a die bat, 2 is an inner lead, 3 is a semiconductor chip, 4 is a wire, and 5 is an insulator.
ダイスパッドｌ上には、半導体チップ３がロウ剤（図示
せず）により固着されている。ダイスパッドｌの周囲に
は、外部リード６と一体となったインナーリード２・・
・が配設されている。そして、ポリイミドなどからなり
枠形状をした絶線体５がその中央にある孔から半導体チ
ップ３を突出させた形でダイスパッドｌとインナーリー
ド２・・・の内周端との上に載置され、エポキシ系接着
剤などの絶縁性接着剤（図示せず）によってインナーリ
ード２・・・とダイスパッド１とに固着されている。こ
のあと、半導体チップ３の表面電極３ａとインナーリー
ド２・・・とは、ワイヤ４によって接続される。そして
、これら半導体装置全体は、外部リード６を残して樹脂
７によって封止される。A semiconductor chip 3 is fixed onto the die pad 1 with a brazing agent (not shown). Around the die pad l, there are inner leads 2 integrated with the outer leads 6.
・is provided. Then, a frame-shaped disconnected wire body 5 made of polyimide or the like is placed on the die pad l and the inner peripheral ends of the inner leads 2, with the semiconductor chip 3 protruding from a hole in the center. and are fixed to the inner leads 2 and the die pad 1 using an insulating adhesive (not shown) such as an epoxy adhesive. Thereafter, the surface electrodes 3a of the semiconductor chip 3 and the inner leads 2 are connected by wires 4. The entire semiconductor device is then sealed with resin 7, leaving the external leads 6.
この半導体装置は、従来例と同様に、ワイヤ４の垂れ下
がりを起こすことがあるが、絶縁体製の絶縁体５がダイ
スパッドｌとインナーリード２・・・の内周端との上面
に載置されているので、その上をまたぐ形で位置するワ
イヤ４は、垂れ下がっても下方に設けられた絶縁体５に
よって受は止められ半導体チップ３の端部やダイスパッ
ドｌに接触することはない。In this semiconductor device, like the conventional example, the wire 4 may hang down, but the insulator 5 made of an insulator is placed on the upper surface of the die pad l and the inner peripheral end of the inner lead 2... Therefore, even if the wire 4 located over the wire 4 hangs down, it is stopped by the insulator 5 provided below and does not come into contact with the end of the semiconductor chip 3 or the die pad l.
また、インナーリード２・・・とダイスパッドｌとは、
絶縁体５によって相互に固定されているので、多少の外
力では変形しない。したがって、インナーリード２・・
・とダイスパッド１とは、製造途中に位置ずれを起こさ
ず、ワイヤ４による接続が困難になることはない。In addition, the inner lead 2... and the die pad l are
Since they are fixed to each other by the insulator 5, they will not be deformed by some external force. Therefore, inner lead 2...
· and the die pad 1 will not be misaligned during manufacturing, and connection with the wire 4 will not become difficult.
なお、上記実施例においては、絶縁体５を枠形状をした
一体物としたが、これに限るわけではなく、ダイスパッ
ドｌとインナーリード２・・・との上面に載置されて絶
縁体を形成する一つ以上の絶縁体であればよい。また、
上記実施例においては、絶縁体５は、ダイスパッドｌと
インナーリード２・・・との双方に固着されていたが、
単にダイスパッド１の周縁上面とインナーリード２の内
端上面とにわたって載置しただけのものであってもよい
。In the above embodiment, the insulator 5 is a frame-shaped integral body, but the insulator 5 is not limited to this. Any one or more insulators may be used. Also,
In the above embodiment, the insulator 5 was fixed to both the die pad l and the inner leads 2...
It may simply be placed over the upper surface of the periphery of the die pad 1 and the upper surface of the inner end of the inner lead 2.
〈発明の効果〉
以゛上のように、本発明によれば、ワイヤがダイスパッ
ド等の不要部分に接触するのを未然に防止して電気的に
ショートするのを防げる
また、絶縁体をインナーリードに固着すれば、インナー
リードの変形が防げワイヤ接続が確実になる。したがっ
て、高品質な半導体装置が簡単にしかも安価に得られる
。<Effects of the Invention> As described above, according to the present invention, it is possible to prevent wires from coming into contact with unnecessary parts such as die pads, thereby preventing electrical short-circuits. If it is fixed to the lead, deformation of the inner lead can be prevented and the wire connection can be ensured. Therefore, a high quality semiconductor device can be easily obtained at low cost.
第１図と第２図とは本発明の一実施例に係り、第１図は
平面図、第２図はその■−■線断面図である。第３図と
第４図とは従来例に係り、第３図は平面図、第４図はそ
の■−ＩＶ線断面図である。
ｌ・・・ダイスパッド
２・・・インナーリード
４・・・ワイヤ
５・・・絶縁体1 and 2 relate to one embodiment of the present invention, in which FIG. 1 is a plan view and FIG. 2 is a sectional view taken along the line ■-■. 3 and 4 relate to a conventional example, in which FIG. 3 is a plan view and FIG. 4 is a sectional view taken along the line -IV. l...Dice pad 2...Inner lead 4...Wire 5...Insulator
Claims (2)
周囲のインナーリードの内端上面とにわたって絶縁体を
設けたことを特徴とする半導体装置。(1) A semiconductor device characterized in that an insulator is provided below the wire, spanning the upper surface of the peripheral edge of the die pad and the upper surface of the inner end of the inner lead surrounding the die pad.
にそれぞれ固着されている特許請求の範囲第１項記載の
半導体装置(2) The semiconductor device according to claim 1, wherein the insulator is fixed to a die pad and an inner lead, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28256187A JPH01124227A (en) | 1987-11-09 | 1987-11-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28256187A JPH01124227A (en) | 1987-11-09 | 1987-11-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01124227A true JPH01124227A (en) | 1989-05-17 |
Family
ID=17654079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28256187A Pending JPH01124227A (en) | 1987-11-09 | 1987-11-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01124227A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0287636A (en) * | 1988-09-26 | 1990-03-28 | Nec Corp | Semiconductor device |
| JPH0342847A (en) * | 1989-07-11 | 1991-02-25 | Sony Corp | Semiconductor device |
-
1987
- 1987-11-09 JP JP28256187A patent/JPH01124227A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0287636A (en) * | 1988-09-26 | 1990-03-28 | Nec Corp | Semiconductor device |
| JPH0342847A (en) * | 1989-07-11 | 1991-02-25 | Sony Corp | Semiconductor device |
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