JPH0342847A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0342847A JPH0342847A JP1178587A JP17858789A JPH0342847A JP H0342847 A JPH0342847 A JP H0342847A JP 1178587 A JP1178587 A JP 1178587A JP 17858789 A JP17858789 A JP 17858789A JP H0342847 A JPH0342847 A JP H0342847A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- die pad
- wire
- lead
- inner leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 44
- 239000011347 resin Substances 0.000 claims abstract description 21
- 229920005989 resin Polymers 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 238000000465 moulding Methods 0.000 abstract description 4
- 238000007789 sealing Methods 0.000 abstract description 3
- 239000000725 suspension Substances 0.000 description 16
- 238000000034 method Methods 0.000 description 6
- 238000007665 sagging Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ダイパッドのチップ搭載面に存するチップと
外部から延びるインナーリードとが金属細線で接続され
た半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device in which a chip existing on a chip mounting surface of a die pad and an inner lead extending from the outside are connected by a thin metal wire.
本発明は、チップとインナーリードとが金属細線で接続
された半導体装置において、ダイパッドのチップ搭載面
におけるチップの周囲に絶縁部材を形成すると共に、チ
ップとインナーリード間を金属細線で接続し、更に全面
を樹脂封止して構成することにより、金属細線の垂れに
よる金属細線とグイパッド間の短絡を防止して半導体装
置の高信頼性を図れるようにすると共に、ダイパッドと
チップの実装上の制約を除去してリードフレーム等を設
計変更することなく多様化するチップの実装を実現でき
るようにしたものである。The present invention provides a semiconductor device in which a chip and an inner lead are connected by a thin metal wire, in which an insulating member is formed around the chip on the chip mounting surface of a die pad, and the chip and the inner lead are connected by a thin metal wire. By encapsulating the entire surface with resin, it is possible to prevent short circuits between the thin metal wires and the Gui pad due to sagging of the thin metal wires, thereby increasing the reliability of the semiconductor device, and also eliminating restrictions on mounting the die pad and chip. This makes it possible to implement mounting of diversified chips without removing the lead frame or changing the design of the lead frame or the like.
また、本発明は、上記半導体装置において、インナーリ
ードのチップ搭載面側先端部表面に絶縁部材を形成して
複数のインナーリード間を連結すると共に、上記絶縁部
材上部を跨って金属細線によりインナーリードとチップ
を接続し、更に全面を樹脂封止して構成することにより
、金属細線とインナーリード間の短絡及びインナーリー
ド同士の短絡を防止して半導体装置の高信頼性化を図れ
るようにすると共に、リードフレーム等を設計変更する
ことなくチップに対する多様の配線を実現できるように
したものである。Further, in the semiconductor device of the present invention, an insulating member is formed on the front end surface of the inner lead on the chip mounting surface side to connect the plurality of inner leads, and the inner lead is connected by a thin metal wire across the upper part of the insulating member. By connecting the chip to the chip and sealing the entire surface with resin, it is possible to prevent short circuits between the thin metal wire and the inner leads and between the inner leads, thereby increasing the reliability of the semiconductor device. , it is possible to realize various wirings for the chip without changing the design of the lead frame or the like.
また、本発明は、上記半導体装置において、ダイパッド
のチップ搭載面におけるチップの周囲に第１の絶縁部材
を形成すると共に、インナーリードのチップ搭載面側先
端部表面に第２の絶縁部材を形成し、上記第１及び第２
の絶縁部材の上部を跨って金属細線によりインナーリー
ドとチップを接続し、更に全面を樹脂封止して構成する
ことにより、金属細線の垂れによる金属細線とグイバン
ド間の短絡、金属細線とインナーリード間の短絡、イン
ナーリード同士の短絡を防止して半導体ｉｔの高信頼性
化をより一層図れるようにすると共に、リードフレーム
等を設計変更することなく多様（ヒするチップの実Ｍ並
びにチップに対する多様の配線を実現できるようにした
ものである。Further, in the semiconductor device of the present invention, a first insulating member is formed around the chip on the chip mounting surface of the die pad, and a second insulating member is formed on the tip end surface of the inner lead on the chip mounting surface side. , the first and second above
The inner lead and the chip are connected by a thin metal wire across the top of the insulating member, and the entire surface is sealed with resin. This prevents short circuits between the thin metal wire and the Gui band due to the thin metal wire hanging, and the thin metal wire and the inner lead. In addition to further increasing the reliability of semiconductor IT by preventing short-circuits between inner leads and short-circuits between inner leads, it is also possible to improve the reliability of semiconductor IT by preventing short-circuits between inner leads and short-circuiting between inner leads. This makes it possible to realize the following wiring.
従来の半導体装置は第１０図に示すように、ダイパッド
（２１）上にチップ（２２）を搭載し、ダイパッド（２
１）の周囲に配したインナーリード（２３）と上記チッ
プ（２２）上のボンディングパソド（２２ａ） とを
金１細線例えば金（Ａｕ）で形成されたワイヤ（２４）
で接続し、更にこれらダイパッド（２１）、チップ（２
２） 、インナーリード（２３）及びワイヤ（２４）を
モールドｌ”！を指層（２５）により封止して構成され
ている。As shown in FIG. 10, a conventional semiconductor device has a chip (22) mounted on a die pad (21).
1) and the bonding path (22a) on the chip (22) using a gold wire (24) made of gold (Au), for example.
and further connect these die pads (21) and chips (2
2) The inner lead (23) and wire (24) are sealed with a finger layer (25) in a mold l''!.
第１１図Ａ及びＢは、インナーリード（２３）の代表的
な配線パターンを示すもので、第１１図Ａは、ダイパッ
ド吊りリード（２６）がダイパッド（２１）の対向する
辺部（２１ａ） に配され、各グイバンド吊りリード
（２６〉の延長線を中心として互いに対称にインナＩＪ
−ド（２３）が配された例を示す。第ｉ１図Ｂは、ダイ
パッド吊りリード（２６）がダイパッド（２１）の四隅
に配され、夫々グイパッド吊りリード（２６）間にイン
ナーリード（２３）が配された例を示す。11A and 11B show typical wiring patterns of the inner lead (23). In FIG. 11A, the die pad suspension lead (26) is connected to the opposite side (21a) of the die pad (21). The inner IJ is arranged symmetrically with respect to the extension line of each guide
- An example in which a code (23) is arranged is shown. FIG. i1B shows an example in which die pad suspension leads (26) are arranged at the four corners of the die pad (21), and inner leads (23) are arranged between the die pad suspension leads (26).
尚、以後、ダイパッド（２１）、ダイパッド吊すリード
（２６〉及びインナーリード（２３）等を総称してリー
ドフレームと記す。Hereinafter, the die pad (21), the die pad suspending lead (26>), the inner lead (23), etc. will be collectively referred to as a lead frame.
〔発明が解決しようとする課題］
一般に、半導体装置においては、ワイヤタッチ（即ち、
ワイヤとグイパッド間の短絡）や構造上の問題から、搭
載するチップのサイズに対し適応するダイパッドの面積
及びワイヤ長等に関する制約が決まっており、この制約
条件に満足するように半導体装置の全体構造が決定され
ている。[Problems to be Solved by the Invention] Generally, in semiconductor devices, wire touch (i.e.
Due to problems such as short circuits between the wire and the die pad) and structural issues, restrictions on the area of the die pad and wire length, etc. that are applicable to the size of the chip to be mounted are determined, and the overall structure of the semiconductor device is designed to satisfy these restrictions. has been decided.
即ち、その制約条件とは、まず第１１図Ａ内の拡大図で
示すように、ワイヤ（２４）の長さａは２．５ｍｍ以内
にすること（制約１）。次に第１０図内の拡大図で示す
ように、ワイヤ（２４）の高さ、即ちダイパッド〈２１
）上面か与ワイヤ（２４〉の頂部までの距離りは１７０
μｍ以上にすること（制約２）。更に、例えば第１１図
へで示すように、ダイパッド（２１）のチップ搭載面と
チップ（２２）の外形との関係、即ちチップ（２２）端
面とグイバンド（２１）端面間の寸法は、グイバンド吊
りリード（２６）に平行な方向（Ｘ方向）においてはＱ
、 ４ｍｍ未満（ｘ ＜Ｑ、４ｍｍ）、ダイパッド吊り
リード（２６〉と直交する方向（Ｙ方向）においては０
．２ｍｍ未７Ｍ （３” Ｏｙ２＋ｎｍ） ｉこするこ
とである（制約３）。これは、Ｘ≧Ｑ、４ｍｍ、 ｙ≧
Ｑ、 ２ｍｍの場合、即ちチップ（２２）が小さい場合
、ワイヤ長ａが長くなることに伴ってワイヤ（２４）が
垂れ、結果的にワイヤ（２４〉とダイパッド（２１）間
において短絡が生じるおそれがあるためである。That is, the constraint condition is that, as shown in the enlarged view in FIG. 11A, the length a of the wire (24) must be within 2.5 mm (constraint 1). Next, as shown in the enlarged view in FIG. 10, the height of the wire (24), that is, the die pad
) The distance from the top surface to the top of the given wire (24〉) is 170
Must be at least μm (constraint 2). Furthermore, as shown in FIG. 11, for example, the relationship between the chip mounting surface of the die pad (21) and the external shape of the chip (22), that is, the dimension between the end face of the chip (22) and the end face of the guide band (21), In the direction parallel to the lead (26) (X direction), Q
, less than 4mm (x <Q, 4mm), 0 in the direction (Y direction) perpendicular to the die pad suspension lead (26>)
．． 2mm less than 7M (3” Oy2+nm) i (constraint 3). This means that X≧Q, 4mm, y≧
Q. In the case of 2 mm, that is, when the chip (22) is small, as the wire length a becomes longer, the wire (24) may sag, resulting in a short circuit between the wire (24> and the die pad (21)). This is because there is.
しかしながら、最近の実装技術要求（パッケージの小型
化等）により、上記制約条件が限界にきており、特に、
チップ（２２〉の多様化（小型化等）経済性（ユーザに
対する納期の短縮化等）や半導体装置の高信頼性等の要
求に対しては、上記制約条件では対応できない時点に来
ており、その対策が急務となっている。However, due to recent packaging technology requirements (package miniaturization, etc.), the above constraints have reached their limits, and in particular,
We have reached the point where the above constraints cannot meet the demands for diversification (miniaturization, etc.) of chips (22), economy (shortening of delivery time to users, etc.), and high reliability of semiconductor devices. Measures against this problem are urgently needed.
また、最近では同一のリードフレームを使用して多種の
ＩＣを搭載する傾向；こあり、それと同時にチップとリ
ード間の配線が規格化されていないことから、ユーザの
ニーズに合せて配線パターンを変える傾向にある。これ
らの傾向の流れに伴い第１１図Ｂ内の拡大図でも示すよ
うに無理な配線（例えばインナーリード（２３ａ）
とチップ（２２）間のワイヤ（２４ａ） ＃照）を行
なうことがあり、このような無理な配線の場合、ワイヤ
長ａが長くなり、それにつれてワイヤ（２４ａ） の
垂れが生じ、隣接するインナーリード（２３ｂ） と
短絡するという不都合がある。In addition, there is a recent trend of using the same lead frame to mount various types of ICs; at the same time, since the wiring between the chip and the leads is not standardized, the wiring pattern can be changed according to the needs of the user. There is a tendency. With the flow of these trends, as shown in the enlarged view in Figure 11B, unreasonable wiring (for example, inner lead (23a)
The wire (24a) may be connected between the chip (22) and the wire (24a), and in the case of such unreasonable wiring, the wire length a becomes long, and the wire (24a) sag, causing damage to the adjacent inner wire. There is an inconvenience that it short-circuits with the lead (23b).
また、パッケージの小型化やアクセス情報の増大化に伴
いインナーリード（２３）間の配線ピッチが狭くなる傾
向にあり、リードフレームの製造工程、特にリードフレ
ームの物流において第１２図に示すように隣接するイン
ナーリード（２３〉同士が寄り、結果的に短絡が発生す
るという不都合がある。Additionally, as packages become smaller and access information increases, the wiring pitch between inner leads (23) tends to become narrower. There is an inconvenience that the inner leads (23) close together, resulting in a short circuit.
本発明は、このような点に鑑み成されたもので、その目
的とするところは、ワイヤの垂れやワイヤとグイパッド
間の短絡を防止することができると共に、ダイパッドと
チップの実装上の制約を除去し、同一のリードフレーム
を使用して多様化するチップの実装を実現することがで
きる半導体装置を提供することにある。The present invention has been made in view of the above points, and its purpose is to prevent sagging of wires and short circuits between wires and guide pads, as well as to eliminate mounting constraints between die pads and chips. It is an object of the present invention to provide a semiconductor device which can be removed and which can realize mounting of various chips using the same lead frame.
また本発明は、ワイヤとインナーリード間の短絡及びイ
ンナーリード同士の短絡を防止することができると共に
、同一のリードフレームを使用して多種のチップに対す
る多様の配線を実現することができる半導体装置を提供
することにある。The present invention also provides a semiconductor device that can prevent short circuits between wires and inner leads and short circuits between inner leads, and can realize various wirings for various types of chips using the same lead frame. It is about providing.
また本発明は、ワイヤの垂れやワイヤとグイパッド間の
短絡、ワイヤとインナーリード間の短絡、インナーリー
ド同士の短絡を防止することができると共に、同一のリ
ードフレームを使用して多様化するチップの実装並びに
多種のチップに対する多様の配線を実現することができ
る半導体装置を提供することにある。Furthermore, the present invention can prevent wire sagging, short circuits between wires and guide pads, short circuits between wires and inner leads, and short circuits between inner leads, and can also be used to reduce the number of chips that are becoming more diverse using the same lead frame. It is an object of the present invention to provide a semiconductor device that can be mounted and realize various wirings for various types of chips.
本発明の半導体装置は、ダイパッド（１）のチップ搭載
面におけるチップ（２）の周囲に絶縁部材（絶縁性フィ
ルム）（７）を形成すると共に、チップ（２）とインナ
ーリード（４）間を金属細線〈ワイヤ）（５）で接続し
、更に全面をモールド樹脂層（６）で封止して構成する
。In the semiconductor device of the present invention, an insulating member (insulating film) (7) is formed around the chip (2) on the chip mounting surface of the die pad (1), and an insulating member (insulating film) (7) is formed between the chip (2) and the inner leads (4). They are connected by thin metal wires (5), and the entire surface is sealed with a molded resin layer (6).
また本発明の半導体装置は、インナーリード（４）のチ
ップ搭載面側先端部表面に絶縁部材（絶縁性テープ）（
９）を形成して複数のインナーリード（４）間を連結す
ると共に、絶縁部材（９）上部を跨ってワイヤ（５）に
よりインナーリード（４）とチップ（２）を接続し、更
に全面をモールド樹脂層（６）で封止して構成する。Further, in the semiconductor device of the present invention, an insulating member (insulating tape) (
9) to connect the plurality of inner leads (4), connect the inner leads (4) and the chip (2) by a wire (5) across the upper part of the insulating member (9), and further cover the entire surface. It is configured by sealing with a mold resin layer (6).
また本発明は、ダイパッド（１）のチップ搭載面におけ
るチップ（２）の周面に第１の絶縁部材（絶縁性フィル
ム）（７）を形成すると共に、インナーリード（４）の
チップ搭載面側先端部表面に第２の絶縁部材（絶縁性テ
ープ）（９）を形成し、これら第１及び第２の絶縁部材
（７）及び（９）の上部を跨ってワイヤ（５）によりイ
ンナーリード（４）とチップ（２）を接続し、更に全面
をモールド樹脂層（６）で封止して構成する。Moreover, the present invention forms a first insulating member (insulating film) (7) on the circumferential surface of the chip (2) on the chip mounting surface of the die pad (1), and also forms a first insulating member (insulating film) (7) on the chip mounting surface of the inner lead (4). A second insulating member (insulating tape) (9) is formed on the surface of the tip, and an inner lead ( 4) and the chip (2) are connected, and the entire surface is further sealed with a mold resin layer (6).
上述の第１の本発明のＭ４戊によれば、ダイパッド（１
）のチップ搭載面におけるチップ（２）の周囲に絶縁部
材（７）を形成するようにしたので、インナーリード（
４）とチップ（２）とを接続するワイヤ（５）が直接グ
イパッド（１）に接触することがない。従って、ワイヤ
（５）の長さａを例えば２．５ｍｍ以上にしたり、ワイ
ヤ（５）の高さｈを例えば１７０μｍ以下にしても、即
ち上述した制約ｌ及び制約２を破ってもワイヤ（５）と
ダイパッド（１）間の短絡は発生しない。また更に規定
のダイパッド（１）に所定サイズのチップより小型のチ
ップを搭載しても、即ち上述した制約３を破っても同様
にワイヤ（５）とグイパッド（１）間の短絡は発生しな
い。その結果、リードフレーム等を設計変更することな
く、即ち同一のリードフレームを使用して多様化するチ
ップ（２）の実装を実現することができると共に、半導
体装置の高信頼性化をも図ることができる。According to the above-mentioned M4 of the first invention, the die pad (1
Since the insulating member (7) is formed around the chip (2) on the chip mounting surface of the inner lead (
4) and the chip (2) do not directly contact the wire pad (1). Therefore, even if the length a of the wire (5) is, for example, 2.5 mm or more, or the height h of the wire (5) is, for example, 170 μm or less, that is, even if the above-mentioned constraints l and constraint 2 are violated, the wire (5) ) and die pad (1) will not occur. Furthermore, even if a chip smaller than a predetermined size chip is mounted on the specified die pad (1), that is, even if the above-mentioned constraint 3 is violated, a short circuit between the wire (5) and the guide pad (1) will not occur. As a result, it is possible to implement a variety of chips (2) without changing the design of the lead frame etc., that is, by using the same lead frame, and also to improve the reliability of the semiconductor device. I can do it.
また、上述の第２の本発明の構成によれば、インナーリ
ード（４）のチップ搭載面側先端部表面に絶縁部材（９
）を形成し、該絶縁部材（９）を跨ってワイヤ（５）に
よりインナーリード（４）とチップ（２）とを接続する
ようにしたので、一方のインナーリード（４ａ）からワ
イヤ（５）がその配線過程において隣接する他方のイン
ナーリード〈４ｂ）にかかったとしても、ワイヤ（５）
は直接他方のインナーリード（４ｂ〉に接触することが
ない。従って、ワイヤ（５）に関し無理な配線を行なっ
てもワイヤ（５）とインナーリード（４）間の短絡は発
生しない。また、インナーリード間は絶縁部材（９）に
より夫々が連結されているため、リードフレームの製造
工程におけるリードフレームの物流において、隣接する
インナーリード（４）同士が接触するということも防止
される。その結果、同一のリードフレームを使用してチ
ップ（２）に対する多様の配線を実現することができる
と共に、半導体装置の高信頼性化をも図ることができる
。Further, according to the configuration of the second aspect of the present invention described above, the insulating member (9) is provided on the tip end surface of the inner lead (4) on the chip mounting surface side.
), and the inner lead (4) and the chip (2) are connected by the wire (5) across the insulating member (9), so that the wire (5) can be connected from one inner lead (4a) to the chip (2). Even if the wire (5) touches the other adjacent inner lead (4b) during the wiring process,
does not directly contact the other inner lead (4b). Therefore, even if the wire (5) is wired in an unreasonable manner, a short circuit between the wire (5) and the inner lead (4) will not occur. Since the leads are connected to each other by the insulating member (9), it is also possible to prevent adjacent inner leads (4) from coming into contact with each other during the logistics of the lead frame in the lead frame manufacturing process.As a result, It is possible to realize various wirings for the chip (2) using the same lead frame, and it is also possible to improve the reliability of the semiconductor device.
また、上述の第３の本発明の構成によればダイパッド（
１）のチップ搭載面におけるチップ（２）の周囲に第１
の絶縁部材（７）を形成すると共に、インナーリード（
４）のチップ搭載面側先端表面に第２の絶縁部材（９）
を形成し、上記第１及び第２の絶縁部材（７）及び（９
）の上部を跨ってワイヤ（５）によりインナーリード（
４）とチップ（２）とを接続するようにしたので、ワイ
ヤ（５）のダイパッド（１）への接触及び隣接するイン
ナーリードへの接触が防止される。またインナーリード
（４）は第２の絶縁部材（９）により夫々が連結されて
いるため、隣接するインナーリード（４）同士の接触も
防止される。従って、同一のリードフレームを使用して
多様化するチップ（２）の実装並びにチップ（２）に対
する多様の配線を実現させることができると共に、半導
体装置の高信頼性化をも図ることができる。Furthermore, according to the configuration of the third aspect of the invention described above, the die pad (
A first layer is placed around the chip (2) on the chip mounting surface of (1).
In addition to forming the insulating member (7) of the inner lead (
4) A second insulating member (9) is placed on the tip surface on the chip mounting surface side.
and the first and second insulating members (7) and (9).
) and connect the inner lead (
4) and the chip (2), the wire (5) is prevented from contacting the die pad (1) and the adjacent inner lead. Further, since the inner leads (4) are connected to each other by the second insulating member (9), contact between adjacent inner leads (4) is also prevented. Therefore, it is possible to implement a variety of mounting of chips (2) and various wirings for the chips (2) using the same lead frame, and it is also possible to improve the reliability of the semiconductor device.
以下、第１図〜第９図を参照しながら本発明の詳細な説
明する。Hereinafter, the present invention will be explained in detail with reference to FIGS. 1 to 9.
第１図は、第１実施例に係る半導体装置の構成を示す断
面図、第２図は２つの代表的配線パターンに準じて示す
上記半導体装置の平面図である。FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to a first embodiment, and FIG. 2 is a plan view of the semiconductor device shown according to two typical wiring patterns.
これらの図において、（１）は上面のチップ搭載面にチ
ップ（２）が載置されるダイパッドである。そして第２
図Ａにおいては、ダイパッド吊りリード（３）がダイパ
ッド（１）の対向する辺部（１ａ）に配されると共に、
ダイパッド吊りリード（３）の延長線を中心として互い
に対称に夫々多数本のインナーリード（４）が設けられ
、これらが複数連結されてリードフレームが構成され、
一方、第２図Ｂにおいては、ダイパッド吊りリード（３
）がダイパッド（１）の四隅に配され、夫々のダイパッ
ド吊りリード（３）間において夫々多数本のインナーリ
ード（４）が設けられ、これらが複数連結されてリード
フレームが構成される。In these figures, (1) is a die pad on which a chip (2) is placed on the upper chip mounting surface. and the second
In Figure A, die pad suspension leads (3) are arranged on opposite sides (1a) of the die pad (1), and
A large number of inner leads (4) are provided symmetrically to each other around the extension line of the die pad suspension lead (3), and a plurality of these inner leads (4) are connected to form a lead frame,
On the other hand, in FIG. 2B, the die pad suspension leads (3
) are arranged at the four corners of the die pad (1), and a large number of inner leads (4) are provided between the respective die pad suspension leads (3), and a plurality of these inner leads (4) are connected to form a lead frame.
そして、チップ（２）上のボンディングパラ） （２ａ
＞とインナーリード（４）とを金（Ａｕ）で形成された
ワイヤ（５）で接続し、更に第１図に示すように、これ
らダイパッド（１）、チップ（２）、インナーリード（
４）及びワイヤ（５）をモールド樹脂層（６）により封
止して構成される。And the bonding para on the chip (2)) (2a
> and the inner lead (4) are connected with a wire (5) made of gold (Au), and as shown in FIG.
4) and the wire (5) are sealed with a molded resin layer (6).
しかしてこの第１実施例においては、ダイパッド（１１
のチップ搭載面にチップ（２）を囲むようにして枠状の
絶縁性フィルム（７）が貼着されて成る。この絶縁性フ
ィルム（７）はチップ（２）及びダイパッド（１）の各
サイズの指定により図示しないカッティング装置により
自動的にカッティングされ、ワイヤボンド処理前におい
てリードフレーム上に連設されたダイパッド（１）に対
し、連続的に貼着される。However, in this first embodiment, the die pad (11
A frame-shaped insulating film (7) is attached to the chip mounting surface of the chip (2) so as to surround the chip (2). This insulating film (7) is automatically cut by a cutting device (not shown) according to the specified sizes of the chip (2) and the die pad (1), and the die pad (1) is attached to the die pad (1) connected to the lead frame before the wire bonding process. ) are continuously pasted.
通常、ワイヤ（５）の高さｈは、規定のパッケージ〈モ
ールド樹脂層（６））のサイズとワイヤタッチ（ワイヤ
（５）とダイパッド（１）間の短絡〉を考慮して設定さ
れるが（現状では１７０μｍ）、パンケージ（６）を規
定サイズよりも小型、特に扁平化された場合、ワイヤ（
５）がパッケージ（６）から飛び出すおそれがある。そ
こで、上記第１実施例では、ダイパッド（１）のチップ
搭載面上に絶縁性フィルム（７）を形成することにより
、ワイヤ（５）の高さｈをある程度まで低くすることが
可能となる。ところが、ワイヤボンド装置が通常のパッ
ケージに対応して構成されているため、やはりワイヤ（
５）の高さｈは現状の１７０μｍを踏襲することになる
。そこで、第３図に示すように、ワイヤボンディング処
理後、新たに枠状の絶縁フィルム（８）を貼着してワイ
ヤ（５）を絶縁性フィルム（７）及び（８）で挟むよう
にすれば、ワイヤ（５）の高さｈを低くすることができ
、特にフィルム（８）の巾畠やワイヤ長ａを制ｉ卸する
ことによって、ワイヤ（５）の高さｈも制御することが
でき、いろいろなパターンのパッケージに対応すること
ができる。Usually, the height h of the wire (5) is set taking into account the size of the specified package (molded resin layer (6)) and wire touch (short circuit between the wire (5) and die pad (1)). (currently 170 μm), if the pan cage (6) is made smaller than the specified size, especially if it is made flat, the wire (
5) may fly out from the package (6). Therefore, in the first embodiment, by forming an insulating film (7) on the chip mounting surface of the die pad (1), it is possible to reduce the height h of the wire (5) to a certain extent. However, since the wire bonding equipment is configured to accommodate normal packages, the wire (
The height h of 5) will follow the current 170 μm. Therefore, as shown in Figure 3, after the wire bonding process, a new frame-shaped insulating film (8) is attached and the wire (5) is sandwiched between the insulating films (7) and (8). For example, the height h of the wire (5) can be reduced, and in particular, by controlling the width of the film (8) and the wire length a, the height h of the wire (5) can also be controlled. It can be used in various packaging patterns.
また、ワイヤ（５）は絶縁性フィルム（７）及び（８）
により挟持されたかたちとなるため、樹脂層（６）のモ
ールド時のワイヤ（５）の流れによる短絡を防止するこ
とができる。In addition, the wire (5) is connected to the insulating films (7) and (8).
Since the resin layer (6) is sandwiched between the two wires, it is possible to prevent short circuits caused by the flow of the wire (5) during molding of the resin layer (6).
上述の如く上記第１実施例によれば、ダイパッド（１）
のチップ搭載面にチップ（２）を囲むようにして絶縁フ
ィルム（７）を貼着するようにしたので、第１図に示す
ように、インナーリード（４）とチップ（２）を接続す
るワイヤ（５）は直接グイパッド（１）に接触すること
がない。従って、ワイヤ（５）の長さａを例えば２、５
ｍｍ以上にしたり、ワイヤ（５）の高さｈを例えば１７
０μｍ以下にしても、即ち上述した制約１及び制約２を
破ったとしてもワイヤ（５）とダイパッド（１）間にお
いて短絡は発生しなくなる。また更に、規定のダイパッ
ド（１）に小型のチップ（規定サイズよりも小さいチッ
プ〉を搭載しても、即ち上述した制約３を破ったとして
も上記と同様にワイヤ（５）とダイパッド（１１間での
短絡は発生しなくなる。その結果、リードフレーム等を
設計変更することなく同一のリードフレームを使用して
多様化するチップ（２）の実装を実現させることができ
、コスト的にも有利となる。また、ワイヤタッチ（ワイ
ヤとグイパッド間の短絡）等の不良を減少させ、品質の
向上並びに歩留りの向上が期待できる。また、ワイヤ（
５）の高さｈの制御をチップ単位で一括にでき、しかも
高さｈを低減化できるため、小型化、扁平化されたパッ
ケージが使用できる。また、通常の製造工程及び製造装
置が使用できることと上述の歩留り向上等の効果から納
期の短縮化に適しており、所謂ＡＳＩＣ等に適応可能で
ある。また、ワイヤボンディング上の制約を解除するこ
とが可能となり、それに伴い設計が楽になると共に、標
準化を促進させることができる。また、ワイヤの高さｈ
を制御することが可能であるため、パッケージの肉厚バ
ランスを適合化させることができ、パッケージへのクラ
ックの発生を防止することができる。As described above, according to the first embodiment, the die pad (1)
Since the insulating film (7) is attached to the chip mounting surface of the chip (2) so as to surround the chip (2), as shown in Figure 1, the wire (5) connecting the inner lead (4) and the chip (2) is ) does not come into direct contact with the Guipad (1). Therefore, the length a of the wire (5) is set to 2, 5, for example.
mm or more, or the height h of the wire (5) is, for example, 17 mm.
Even if the thickness is 0 μm or less, that is, even if the above-mentioned constraints 1 and 2 are violated, no short circuit will occur between the wire (5) and the die pad (1). Furthermore, even if a small chip (a chip smaller than the specified size) is mounted on the specified die pad (1), that is, even if the above-mentioned constraint 3 is violated, the same problem will occur between the wire (5) and the die pad (11). As a result, it is possible to implement a variety of chips (2) using the same lead frame without changing the design of the lead frame, which is also advantageous in terms of cost. It also reduces defects such as wire touch (short circuit between the wire and the guide pad), and can be expected to improve quality and yield.
Since the height h (5) can be controlled all at once on a chip-by-chip basis and the height h can be reduced, a smaller and flatter package can be used. In addition, because ordinary manufacturing processes and manufacturing equipment can be used, and the above-mentioned yield improvement is achieved, it is suitable for shortening delivery times, and can be applied to so-called ASICs. Further, it becomes possible to remove restrictions on wire bonding, thereby making design easier and promoting standardization. Also, the height of the wire h
Since it is possible to control the wall thickness balance of the package, it is possible to prevent the occurrence of cracks in the package.
上記第１実施例は、ダイパッド（１）側に絶縁性フィル
ム（７）を設けるようにしてワイヤタッチ等の不良を防
止するようにしたが、次にインナーリード（４）側に絶
縁部材を設けるようにした第２実施例を第４図及び第５
図に基いて説明する。In the first embodiment, an insulating film (7) is provided on the die pad (1) side to prevent defects such as wire touching, but next, an insulating member is provided on the inner lead (4) side. The second embodiment is shown in FIGS. 4 and 5.
This will be explained based on the diagram.
ここで、第４図は第２実施例に係る半導体装置の構成を
示す断面図、第５図は２つの代表的配線パターンに準じ
て示す上記半導体装置の平面図である。尚、この第２実
施例は、基本的には上記第１実施例と同様の構成を有す
るため、上記第１実施例と対応するものについて同符号
を記すことにし、その詳細説明は省略する。Here, FIG. 4 is a sectional view showing the structure of a semiconductor device according to a second embodiment, and FIG. 5 is a plan view of the semiconductor device shown according to two typical wiring patterns. Since this second embodiment basically has the same configuration as the first embodiment, the same reference numerals will be used to denote the same parts as in the first embodiment, and detailed explanation thereof will be omitted.
しかして、この第２実施例においては、インナＩＪ−ド
（４）の先端部表面、更に詳しくはダイパッド（１）の
チップ搭載面側の先端部表面に絶縁性テープ（９）を貼
着し、該テープ（９）の上部を跨がるようにしてワイヤ
（５）によりインナーリード（４）とチップ（２）とを
接続して成る。このテープ（９）の貼着方法としては、
まず第５図Ａの配線パターンについては、コの字状に裁
断した２本のテープ（９ａ）、 （９ｂ） を夫々そ
の両端部がダイパッド吊りリード（３）にかかるように
すると共に、ダイパッド（１）の周囲に配されたインナ
ーリード（４）を連結するようにして貼着する。また、
第５図Ｂの配線パターンについては、短冊状に裁断した
４本のテープ（９Ｃ〉〜（９ｆ）を夫々その両端部がダ
イパツド吊りリード（３）にかかるようにすると共に、
ダイパッド吊りリード（３）間に配されたインナーリー
ド（４）を連結するようにして貼着する。尚、第５図Ａ
及びＢとも、枠状に裁断したテープ〈図示せず〉でダイ
パツド吊りリード（３）及びインナーリード（４）を連
結するようにして貼着するようにしてもよいが、ダイパ
ツド吊りリード（３）とテープの熱膨張率の違いからダ
イパツド吊りリード（３）及びインナーリード（４）が
変形するおそれがあるため、本例の如くテープをダイパ
ツド吊りリード（３）の部分でカットするようにすれば
、熱膨張率の違いによる変形を防止することができる。Therefore, in this second embodiment, an insulating tape (9) is pasted on the tip surface of the inner IJ-pad (4), more specifically on the tip surface of the die pad (1) on the chip mounting surface side. The inner lead (4) and the chip (2) are connected by a wire (5) so as to straddle the upper part of the tape (9). The method for attaching this tape (9) is as follows:
First, regarding the wiring pattern shown in Figure 5A, two tapes (9a) and (9b) cut into a U-shape are cut so that both ends thereof hang over the die pad suspension leads (3), and the die pad ( The inner leads (4) arranged around 1) are connected and attached. Also,
For the wiring pattern shown in Figure 5B, cut four pieces of tape (9C> to (9f) into strips so that both ends thereof hang over the die pad hanging lead (3),
The inner leads (4) arranged between the die pad suspension leads (3) are attached so as to be connected. Furthermore, Figure 5A
For both of and B, the die pad suspension lead (3) and the inner lead (4) may be connected and attached using a tape (not shown) cut into a frame shape, but the die pad suspension lead (3) There is a risk that the die pad suspension lead (3) and inner lead (4) may be deformed due to the difference in thermal expansion coefficient between the die pad suspension lead (3) and the tape, so if you cut the tape at the die pad suspension lead (3) as in this example, , deformation due to differences in thermal expansion coefficients can be prevented.
上述の如く、上記第２実施例によれば、インナーリード
（４）のチップ搭載面側先端部表面に絶縁性テープ（９
）を貼着し、該テープ（９）の上部を跨がるようにして
ワイヤ（５）によりインナーリード（４）とチッブ（２
）を接続するようにしたので、一方のインナーリード（
４ａ）からワイヤ（５）がその配線過程において隣接す
る他方のインナーリード（４ｂ）にかかったとしてもワ
イヤ（５）は直接他方のインナーリード（４ｂ〉に接触
することがない。従って、ワイヤ（５）に関し無理な配
線を行ってもワイヤ（５）とインナーリード（４）間の
短絡は発生しない。また、インナーリード（４）間は、
絶縁性テープ（９）により夫々が連結されているため、
リードフレームの製造工程におけるリードフレームの物
流において、隣接するインナーリード（４）同士が接触
するということも防止され、インナーリード（４）間の
短絡は発生しない。その結果、リードフレーム等を設計
変更することなく同一のリードフレームを使用して多種
のチップに対する多様の配線をインナーリードの入射角
やワイヤ長等を気にせずに行なうことができると共に、
半導体装置の高信頼性化をも図ることができる。As described above, according to the second embodiment, the insulating tape (9) is attached to the tip end surface of the inner lead (4) on the chip mounting surface side.
) and connect the inner lead (4) and chip (2) with the wire (5) so as to straddle the top of the tape (9).
), so one inner lead (
Even if the wire (5) from 4a) touches the other adjacent inner lead (4b) during the wiring process, the wire (5) will not directly contact the other inner lead (4b). Regarding 5), a short circuit between the wire (5) and the inner lead (4) will not occur even if unreasonable wiring is performed.Also, between the inner leads (4),
Since each is connected by an insulating tape (9),
During the logistics of lead frames in the lead frame manufacturing process, adjacent inner leads (4) are prevented from coming into contact with each other, and short circuits between inner leads (4) do not occur. As a result, the same lead frame can be used to perform a variety of wiring for various types of chips without having to change the design of the lead frame, etc., without worrying about the incident angle of the inner leads or the wire length, etc.
It is also possible to improve the reliability of the semiconductor device.
また、チップの多端子化並びにパッケージの小型化に伴
ってインナーリード（４）の配列ピッチが挟間化されて
も、隣接するインナーリード（４）同士の寄りの心配は
ない。また、リードフレームの物流において、リードフ
レームを多段に重なっても上下に関するリードフレーム
同士にテープ貼着部分の厚さ分だけ隙間が形成されるた
め、リードフレームの分離を容易に行なうことができ、
上下に関するリードフレーム同士の係合によって生じる
該リードフレームの変形〈折曲がり等）を防止すること
ができる。尚、この第２実施例においてインナーリード
（４）に絶縁性テープ（９）を貼着してもワイヤボンデ
ィング時の空打ちに対して支障はない。Further, even if the arrangement pitch of the inner leads (4) is narrowed due to the increase in the number of terminals of chips and the miniaturization of packages, there is no need to worry about adjacent inner leads (4) shifting toward each other. Furthermore, in the distribution of lead frames, even if lead frames are stacked in multiple stages, a gap is formed between the upper and lower lead frames by the thickness of the taped area, making it easy to separate the lead frames.
Deformation (bending, etc.) of the lead frame caused by engagement between the upper and lower lead frames can be prevented. In this second embodiment, even if the insulating tape (9) is attached to the inner lead (4), there is no problem with dry bonding during wire bonding.
次に、第６図及び第７図に示す第３実施例は、上記第１
及び第２実施例を組合せたものである。Next, the third embodiment shown in FIGS. 6 and 7 is similar to the first embodiment described above.
and the second embodiment.
尚、この第３実施例において、上記第１及び第２実施例
と対応するものについて同符号を記すことにし、その詳
細説明は省略する。In this third embodiment, the same reference numerals are given to the parts corresponding to those in the first and second embodiments, and detailed explanation thereof will be omitted.
この第３実施例によれば、第１実施例による効果と第２
実施例による効果を兼ね備えることとなり、ワイヤ（５
）の垂れによるワイヤ（５）とダイパッド（１）間の短
絡、ワイヤ（５）とインナーリード（４）間の短絡、イ
ンナーリード（４）同士の短絡を一度に防止することが
でき、半導体装置の高信頼性化をより一層図ることがで
きると共に、リードフレーム等を設計変更することなく
同一のリードフレームを使用して多様化するチップの実
装並びに多種のチップに対する多様の配線を実現させる
ことができる。According to this third embodiment, the effects of the first embodiment and the second
It combines the effects of the embodiment, and the wire (5
) can prevent short circuits between the wire (5) and die pad (1), short circuits between the wire (5) and inner leads (4), and short circuits between inner leads (4) due to sagging of the semiconductor device. In addition to further increasing the reliability of the lead frame, it is also possible to implement a variety of chip mounting and various wiring for various types of chips using the same lead frame without changing the design of the lead frame etc. can.
上記第３実施例は、絶縁性フィルム（７）をダイパッド
（１）のチップ搭載面に貼着すると共に、絶縁性テープ
（９）をインナーリード（４）の先端部表面に貼着する
ようにしたが、その他第８図及び第９図に示すように、
枠状の絶縁性フィルム（１０〉を幅広に形威し、該フィ
ルム（１０）で−度にダイパッド（１）のチップ搭載面
及びインナーリード（４）の先端部表面を包含するよう
に貼着するようにしてもよい。また、樹脂層（６）のモ
ールディング、特に樹脂層（６）のチップ（２）上への
モールディングを容易にするために絶縁性フィルム（１
０）のダイパッド（１）とインナーリード（４）間の部
分に穴を設けるようにしてもよい。In the third embodiment, an insulating film (7) is attached to the chip mounting surface of the die pad (1), and an insulating tape (9) is attached to the tip surface of the inner lead (4). However, as shown in Figures 8 and 9,
Form a frame-shaped insulating film (10) into a wide shape, and attach the film (10) so as to cover the chip mounting surface of the die pad (1) and the tip surface of the inner lead (4) at once. In addition, an insulating film (1) may be used to facilitate molding of the resin layer (6), particularly molding of the resin layer (6) onto the chip (2).
A hole may be provided in the portion between the die pad (1) and the inner lead (4) of 0).
本発明に係る半導体装置は、ダイパッドのチップ搭載面
：こおけるチップの周囲に絶縁部材を形成すると共に、
チップとインナーリード間を金属細線（ワイヤ〉で接続
し、更に全面を樹脂封止して構成するようにしたので、
ワイヤの垂れによるワイヤとグイパッド間の短絡を防止
することができ、半導体装置の高信頼性化を図ることが
できると共に、ダイパッドとチップの実装上の制約を除
去してリードフレーム等を設計変更することなく同一の
リードフレームを使用して多様化するチップの実装を実
現させることができる。In the semiconductor device according to the present invention, an insulating member is formed around the chip on the chip mounting surface of the die pad, and
The chip and inner leads are connected by thin metal wires, and the entire surface is sealed with resin, so
It is possible to prevent short circuits between wires and guide pads due to sagging wires, making it possible to improve the reliability of semiconductor devices, and to change the design of lead frames, etc. by removing restrictions on mounting die pads and chips. It is possible to implement a variety of chips using the same lead frame without any problems.
また、本発明に係る半導体装置はインナーリードのチッ
プ搭載面側先端部表面に絶縁部材を形成して複数のイン
ナーリード間を連結すると共に、上記絶縁部材上部を跨
ってワイヤによりインナーリードとチップを接続し、更
に全面を樹脂封止して構成するようにしたので、ワイヤ
とインナーリード間の短絡及びインナーリード同士の短
絡を防止することができ、半導体装置の高信頼性化を図
ることができると共に、リードフレーム等を設計変更す
ることなく同一のリードフレームを使用して多種のチッ
プに対する多様の配線を実現させることができる。Further, in the semiconductor device according to the present invention, an insulating member is formed on the tip end surface of the inner lead on the chip mounting surface side to connect the plurality of inner leads, and a wire is used to connect the inner lead and the chip by straddling the upper part of the insulating member. Since the wires are connected and the entire surface is sealed with resin, it is possible to prevent short circuits between the wire and the inner leads and short circuits between the inner leads, thereby increasing the reliability of the semiconductor device. In addition, various wirings for various types of chips can be realized using the same lead frame without changing the design of the lead frame or the like.
また、本発明に係る半導体装置は、ダイパッドのチップ
搭載面におけるチップの周囲に第１の絶縁部材を形成す
ると共に、インナーリードのチップ搭載面側先端部表面
に第２の絶縁部材を形成し、上記第１及び第２の絶縁部
材の上部を跨ってワイヤによりインナーリードとチップ
を接続し、更に全面に樹脂封止して構成するようにした
ので、ワイヤの垂れによるワイヤとグイパッド間の短絡
、ワイヤとインナーリード間の短絡、インナーリード同
士の短絡を防止することができ、半導体装置の高信頼性
化をより一層図ることができると共に、リードフレーム
等を設計変更することなく同一のリードフレームを使用
して多様化するチップの実装並びにチ・・ブに対する多
様の配線を実現させることができる。Further, in the semiconductor device according to the present invention, a first insulating member is formed around the chip on the chip mounting surface of the die pad, and a second insulating member is formed on the tip end surface of the inner lead on the chip mounting surface side. The inner leads and the chip are connected by a wire across the upper parts of the first and second insulating members, and the entire surface is sealed with resin, so that short circuits between the wire and the Gui pad due to sagging of the wire can be avoided. It is possible to prevent short circuits between wires and inner leads, as well as short circuits between inner leads, making it possible to further improve the reliability of semiconductor devices, and to use the same lead frame without changing the design of the lead frame. By using this method, it is possible to realize diversified chip mounting and various wiring for chips.
第１図は第１実施例に係る半導体装置の構成を示す断面
図、第２図は第１実施例に係る半導体装置を代表的な配
線パターンに準じて示す平面図、第３図は第１実施例の
変形例を示す断面図、第４図は第２実施例に係る半導体
装置の構成を示す断面図、第５図は第２実施例に係る半
導体装置を代表的な配線パターンに準じて示す平面図、
第６図は第３実施例に係る半導体装置の構成を示す断面
図、第７図は第３実施例に係る半導体装置を代表的な配
線パターンに準じて示す平面図、第８図は第３実施例の
変形例を示す断面図、第９図は第３実施例の変形例を代
表的な配線パターンに準じて示す平面図、第１０図は従
来例に係る半導体装置の構成を示す断面図、第１１図は
従来例に係る半導体装置を代表的な配線パターンに準じ
て示す平面図、第１２図は従来例に係る半導体装置の作
用を示す説明図である。
（１）はダイパッド、（２）はチップ、（３）はダイパ
ッド吊りリード、（４）はインナーリード、（５）はワ
イヤ、（６）はモールド樹脂層、（７）、 （８）及
び（１０）は絶縁性フィルム、（９）は絶縁性テープで
ある。
第５図
＋４ｃｉ−派プ平面図
第７
７−ン＋二１ｅＺｉｊ’Ｆａｌ１
図
２５６−FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to the first embodiment, FIG. 2 is a plan view showing the semiconductor device according to the first example according to a typical wiring pattern, and FIG. FIG. 4 is a cross-sectional view showing the configuration of a semiconductor device according to the second example, and FIG. 5 is a cross-sectional view showing a modification of the second example. FIG. A plan view showing,
FIG. 6 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment, FIG. 7 is a plan view showing the semiconductor device according to a third example according to a typical wiring pattern, and FIG. 9 is a plan view showing a modification of the third embodiment according to a typical wiring pattern; FIG. 10 is a sectional view showing the configuration of a conventional semiconductor device. , FIG. 11 is a plan view showing a conventional semiconductor device according to a typical wiring pattern, and FIG. 12 is an explanatory diagram showing the operation of the conventional semiconductor device. (1) is the die pad, (2) is the chip, (3) is the die pad suspension lead, (4) is the inner lead, (5) is the wire, (6) is the mold resin layer, (7), (8) and ( 10) is an insulating film, and (9) is an insulating tape. Fig. 5+4ci- group plan view No. 7
Claims (1)
絶縁部材が形成され、チップとインナーリード間を金属
細線で接続され、更に全面が樹脂封止されて成る半導体
装置。 ２、チップ搭載面側のインナーリード先端部表面に絶縁
部材が形成されて複数のインナーリード間が連結され、
上記絶縁部材上部を跨って金属細線によりインナーリー
ドとチップが接続され、更に全面が樹脂封止されて成る
半導体装置。 ３、ダイパッドのチップ搭載面におけるチップの周囲に
第１の絶縁部材が形成され、チップ搭載面側のインナー
リード先端部表面に第２の絶縁部材が形成されて該第２
の絶縁部材により複数のインナーリード間が連結され、
上記第１及び第２の絶縁部材上部を跨って金属細線によ
りインナーリードとチップが接続され、更に全面が樹脂
封止されて成る半導体装置。[Claims] 1. A semiconductor device in which an insulating member is formed around the chip on the chip mounting surface of a die pad, the chip and inner leads are connected by thin metal wires, and the entire surface is sealed with resin. 2. An insulating member is formed on the tip surface of the inner lead on the chip mounting surface side to connect the plurality of inner leads,
A semiconductor device in which an inner lead and a chip are connected by a thin metal wire across the upper part of the insulating member, and the entire surface is sealed with resin. 3. A first insulating member is formed around the chip on the chip mounting surface of the die pad, and a second insulating member is formed on the surface of the tip of the inner lead on the chip mounting surface side.
A plurality of inner leads are connected by an insulating member,
A semiconductor device in which an inner lead and a chip are connected by a thin metal wire across the upper portions of the first and second insulating members, and the entire surface is sealed with resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1178587A JPH0342847A (en) | 1989-07-11 | 1989-07-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1178587A JPH0342847A (en) | 1989-07-11 | 1989-07-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0342847A true JPH0342847A (en) | 1991-02-25 |
Family
ID=16051080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1178587A Pending JPH0342847A (en) | 1989-07-11 | 1989-07-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0342847A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5409863A (en) * | 1993-02-19 | 1995-04-25 | Lsi Logic Corporation | Method and apparatus for controlling adhesive spreading when attaching an integrated circuit die |
| KR100247908B1 (en) * | 1992-12-30 | 2000-03-15 | 윤종용 | Semiconductor apparatus |
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|---|---|---|---|---|
| JPS57114263A (en) * | 1981-01-07 | 1982-07-16 | Toshiba Corp | Semiconductor device |
| JPS58182859A (en) * | 1982-04-21 | 1983-10-25 | Toshiba Corp | Lead frame for semiconductor device |
| JPS59166611A (en) * | 1983-03-12 | 1984-09-20 | Nippon Steel Corp | Reduction refining of molten steel containing chromium |
| JPS59181656A (en) * | 1983-03-31 | 1984-10-16 | Toshiba Corp | Semiconductor device |
| JPS62183078A (en) * | 1986-02-06 | 1987-08-11 | Fujitsu Ltd | Magnetic head supporting mechanism |
| JPS6427236A (en) * | 1987-07-22 | 1989-01-30 | Mitsubishi Electric Corp | Wire bonding method |
| JPH01124227A (en) * | 1987-11-09 | 1989-05-17 | Mitsubishi Electric Corp | Semiconductor device |
| JPH01128440A (en) * | 1987-11-11 | 1989-05-22 | Fukuoka Nippon Denki Kk | Resin-sealed semiconductor device |
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1989
- 1989-07-11 JP JP1178587A patent/JPH0342847A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57114263A (en) * | 1981-01-07 | 1982-07-16 | Toshiba Corp | Semiconductor device |
| JPS58182859A (en) * | 1982-04-21 | 1983-10-25 | Toshiba Corp | Lead frame for semiconductor device |
| JPS59166611A (en) * | 1983-03-12 | 1984-09-20 | Nippon Steel Corp | Reduction refining of molten steel containing chromium |
| JPS59181656A (en) * | 1983-03-31 | 1984-10-16 | Toshiba Corp | Semiconductor device |
| JPS62183078A (en) * | 1986-02-06 | 1987-08-11 | Fujitsu Ltd | Magnetic head supporting mechanism |
| JPS6427236A (en) * | 1987-07-22 | 1989-01-30 | Mitsubishi Electric Corp | Wire bonding method |
| JPH01124227A (en) * | 1987-11-09 | 1989-05-17 | Mitsubishi Electric Corp | Semiconductor device |
| JPH01128440A (en) * | 1987-11-11 | 1989-05-22 | Fukuoka Nippon Denki Kk | Resin-sealed semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100247908B1 (en) * | 1992-12-30 | 2000-03-15 | 윤종용 | Semiconductor apparatus |
| US5409863A (en) * | 1993-02-19 | 1995-04-25 | Lsi Logic Corporation | Method and apparatus for controlling adhesive spreading when attaching an integrated circuit die |
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