JPS62188149U - - Google Patents

Info

Publication number
JPS62188149U
JPS62188149U JP1986076334U JP7633486U JPS62188149U JP S62188149 U JPS62188149 U JP S62188149U JP 1986076334 U JP1986076334 U JP 1986076334U JP 7633486 U JP7633486 U JP 7633486U JP S62188149 U JPS62188149 U JP S62188149U
Authority
JP
Japan
Prior art keywords
thickened
exposed
semiconductor device
resin
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1986076334U
Other languages
Japanese (ja)
Other versions
JPH0419799Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986076334U priority Critical patent/JPH0419799Y2/ja
Publication of JPS62188149U publication Critical patent/JPS62188149U/ja
Application granted granted Critical
Publication of JPH0419799Y2 publication Critical patent/JPH0419799Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示す説明図、第２
図は第１図のＡ−Ａ′断面図である。 １……ダイアイランド、２……半導体素子、３
……インナーリード、４……保持用リード、５…
…モールド樹脂。 Fig. 1 is an explanatory diagram showing one embodiment of the present invention;
The figure is a sectional view taken along the line AA' in FIG. 1...Die island, 2...Semiconductor element, 3
...Inner lead, 4...Holding lead, 5...
...Mold resin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 小型樹脂封止の半導体装置において、リードフ
レームのダイアイランド部を厚くして、該肉厚部
の一面を封止樹脂の一面に露出させたことを特徴
とする半導体装置。 1. A small resin-sealed semiconductor device, characterized in that a die island portion of a lead frame is thickened, and one surface of the thick portion is exposed to one surface of the sealing resin.
JP1986076334U 1986-05-22 1986-05-22 Expired JPH0419799Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986076334U JPH0419799Y2 (en) 1986-05-22 1986-05-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986076334U JPH0419799Y2 (en) 1986-05-22 1986-05-22

Publications (2)

Publication Number Publication Date
JPS62188149U true JPS62188149U (en) 1987-11-30
JPH0419799Y2 JPH0419799Y2 (en) 1992-05-06

Family

ID=30923315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986076334U Expired JPH0419799Y2 (en) 1986-05-22 1986-05-22

Country Status (1)

Country Link
JP (1) JPH0419799Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009302387A (en) * 2008-06-16 2009-12-24 Sanken Electric Co Ltd Semiconductor device and method for manufacturing same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59115653U (en) * 1983-01-25 1984-08-04 サンケン電気株式会社 Insulator-encapsulated semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59115653U (en) * 1983-01-25 1984-08-04 サンケン電気株式会社 Insulator-encapsulated semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009302387A (en) * 2008-06-16 2009-12-24 Sanken Electric Co Ltd Semiconductor device and method for manufacturing same

Also Published As

Publication number Publication date
JPH0419799Y2 (en) 1992-05-06

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