JPH0476038U - - Google Patents
Info
- Publication number
- JPH0476038U JPH0476038U JP11910990U JP11910990U JPH0476038U JP H0476038 U JPH0476038 U JP H0476038U JP 11910990 U JP11910990 U JP 11910990U JP 11910990 U JP11910990 U JP 11910990U JP H0476038 U JPH0476038 U JP H0476038U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- die
- wire
- bonded
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Description
第１図は本考案によるリードフレームの一実施
例を示す外観図、第２図は同リードフレームの側
面図、第３図は同リードフレームの従来の外観図
である。
図中、１はリードフレーム、２はリード、３は
ワイヤ、４はハイブリツトＩＣのダイ、５はダイ
パツトである。
FIG. 1 is an external view showing an embodiment of the lead frame according to the present invention, FIG. 2 is a side view of the lead frame, and FIG. 3 is a conventional external view of the lead frame. In the figure, 1 is a lead frame, 2 is a lead, 3 is a wire, 4 is a hybrid IC die, and 5 is a die pad.
Claims (1)
レームのリードをワイヤーボンデイングし、ボン
デエイングしたワイヤーにてリードフレームにダ
イを保持しトランスフアーモールドしたことを特
徴とするリードフレーム。 A lead frame characterized in that the electrode of the die and the lead of the lead frame are wire bonded without using a die pad, and the die is held on the lead frame with the bonded wire and transfer molded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11910990U JPH0476038U (en) | 1990-11-14 | 1990-11-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11910990U JPH0476038U (en) | 1990-11-14 | 1990-11-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0476038U true JPH0476038U (en) | 1992-07-02 |
Family
ID=31867089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11910990U Pending JPH0476038U (en) | 1990-11-14 | 1990-11-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0476038U (en) |
-
1990
- 1990-11-14 JP JP11910990U patent/JPH0476038U/ja active Pending