JPH04759U - - Google Patents

Info

Publication number
JPH04759U
JPH04759U JP1990040790U JP4079090U JPH04759U JP H04759 U JPH04759 U JP H04759U JP 1990040790 U JP1990040790 U JP 1990040790U JP 4079090 U JP4079090 U JP 4079090U JP H04759 U JPH04759 U JP H04759U
Authority
JP
Japan
Prior art keywords
lead frame
tab tape
semiconductor device
interposed
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990040790U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990040790U priority Critical patent/JPH04759U/ja
Publication of JPH04759U publication Critical patent/JPH04759U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る半導体装置の実施例を示
す平面図、第2図は第1図のX−X線拡大断面図
、第3図は従来例を示す断面図である。 2……半導体素子、3……リードフレーム、6
……タブテープ、61……フイルム、62……リ
ード。
FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is an enlarged sectional view taken along the line X--X of FIG. 1, and FIG. 3 is a sectional view showing a conventional example. 2... Semiconductor element, 3... Lead frame, 6
...Tab tape, 61...Film, 62...Lead.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子とリードフレームとの間にタブテー
プを介装し、タブテープのリードとリードフレー
ムとを接続導通してなる半導体装置。
A semiconductor device in which a tab tape is interposed between a semiconductor element and a lead frame, and the leads of the tab tape are connected and electrically connected to the lead frame.
JP1990040790U 1990-04-16 1990-04-16 Pending JPH04759U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990040790U JPH04759U (en) 1990-04-16 1990-04-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990040790U JPH04759U (en) 1990-04-16 1990-04-16

Publications (1)

Publication Number Publication Date
JPH04759U true JPH04759U (en) 1992-01-07

Family

ID=31550885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990040790U Pending JPH04759U (en) 1990-04-16 1990-04-16

Country Status (1)

Country Link
JP (1) JPH04759U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58107659A (en) * 1981-12-21 1983-06-27 Seiko Keiyo Kogyo Kk Mounting device for integrated circuit
JPH01280687A (en) * 1988-05-06 1989-11-10 Natl Aerospace Lab Cups type ion engine
JPH0222850A (en) * 1988-07-11 1990-01-25 Hitachi Cable Ltd Lead frame for semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58107659A (en) * 1981-12-21 1983-06-27 Seiko Keiyo Kogyo Kk Mounting device for integrated circuit
JPH01280687A (en) * 1988-05-06 1989-11-10 Natl Aerospace Lab Cups type ion engine
JPH0222850A (en) * 1988-07-11 1990-01-25 Hitachi Cable Ltd Lead frame for semiconductor device

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