JPH03116043U - - Google Patents
Info
- Publication number
- JPH03116043U JPH03116043U JP2478090U JP2478090U JPH03116043U JP H03116043 U JPH03116043 U JP H03116043U JP 2478090 U JP2478090 U JP 2478090U JP 2478090 U JP2478090 U JP 2478090U JP H03116043 U JPH03116043 U JP H03116043U
- Authority
- JP
- Japan
- Prior art keywords
- leads
- circuit package
- window
- expose
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の第１の実施例、第２図は第１
図のＡ−Ａ断面図、第３図は窓部の拡大斜視図、
第４図は第２の実施例、第５図は第３の実施例、
第６図は従来例を示す図である。
図中、１……回路パツケージ、１ａ……窓、２
……チツプ、３……リードである。
Figure 1 shows the first embodiment of the present invention, Figure 2 shows the first embodiment of the invention.
AA sectional view in the figure, FIG. 3 is an enlarged perspective view of the window part,
FIG. 4 shows the second embodiment, FIG. 5 shows the third embodiment,
FIG. 6 is a diagram showing a conventional example. In the figure, 1...Circuit package, 1a...Window, 2
...Chip, 3...Lead.
Claims (1)
該リードを外部に露出させる窓１ａを形成したこ
とを特徴とする回路パツケージ。 In the circuit package 1 with leads 3,
A circuit package characterized in that a window 1a is formed to expose the leads to the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2478090U JPH03116043U (en) | 1990-03-12 | 1990-03-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2478090U JPH03116043U (en) | 1990-03-12 | 1990-03-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03116043U true JPH03116043U (en) | 1991-12-02 |
Family
ID=31527731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2478090U Pending JPH03116043U (en) | 1990-03-12 | 1990-03-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03116043U (en) |
-
1990
- 1990-03-12 JP JP2478090U patent/JPH03116043U/ja active Pending