JPS58143541A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58143541A JPS58143541A JP57026057A JP2605782A JPS58143541A JP S58143541 A JPS58143541 A JP S58143541A JP 57026057 A JP57026057 A JP 57026057A JP 2605782 A JP2605782 A JP 2605782A JP S58143541 A JPS58143541 A JP S58143541A
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- leads
- lead
- wire
- tab
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
本発明はリードフレームな用いて組立てる樹脂封止杉牛
導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resin-sealed Sugigyu conductor device assembled using a lead frame.
リード（ビン）数の多い樹脂封止形ｔＣ（半導体集積回
路装置）においては、第１図、第２図にボすようにタブ
（金属小板）１．タブ吊りリート。In a resin-sealed TC (semiconductor integrated circuit device) with a large number of leads (bins), tabs (small metal plates) 1. Tab hanging leat.
２、ＩＩ象のリード３かうなるリードフレームを用い、
タブ上にＩＣ素子の形成された半導体ペレット４を取り
付け、ペレット４ Ｉ：の電極とリードとの闇をワイヤ
（金属軸＃Ｉ）５により接続した七、ペレットとリード
の内側（インナーリード）３ａを包囲するように樹脂モ
ールド体７で封止し、リードの外側（アウターリード）
３ｂ間のダムＣ枝部）６を取り除いて各リード間な電気
的に離隔するようＫなっている。2. Using a lead frame with 3 elephant leads,
A semiconductor pellet 4 on which an IC element is formed is mounted on the tab, and the electrode and lead of the pellet 4 I are connected by a wire (metal shaft #I) 5. 7. The inside of the pellet and the lead (inner lead) 3a The outside of the lead (outer lead) is sealed with a resin mold body 7 so as to surround the lead.
The dam (C branch) 6 between 3b and 3b is removed to electrically isolate each lead.
ところでＩｃのリード本数が例えば４２杢と極めて多（
なると、タブ周辺の限られた範囲内に多くのインナーリ
ード３ｍを入れることが困罐であり、又、同時にパッケ
ージ寸法が大きくなるとインナーリードが長く不安定と
なるためにワイ・〒ボンディング時の空打ちを防止する
ようにリード端を固定する必要がでてくる。By the way, the number of leads of Ic is extremely large, for example 42 heathers (
Therefore, it is difficult to fit as many 3 m of inner leads within a limited area around the tab, and at the same time, as the package size increases, the inner leads become long and unstable, so the empty space during Y-bonding becomes difficult. It becomes necessary to fix the lead end to prevent it from being struck.
本発明は上記した開−な解決するためＫなされたもので
あり、その目的とするところは、リード数の多い樹脂封
止半導体装置において、インナーリードの不安定によっ
て生じるワイヤボンディング不良、ワイヤによるシ璽−
ト不良唖を防止することにある。The present invention has been made to solve the above-mentioned problem, and its purpose is to solve wire bonding defects caused by instability of inner leads and wire bonding problems in resin-sealed semiconductor devices with a large number of leads. Seal
The purpose is to prevent malfunctions.
以下実施例にそって本発明な畦述する。The present invention will be described below with reference to Examples.
第３図、１１４図は本発明による半導体Ｍｌｌの賛部を
示すものである。この半導体装置はタブやタブ吊りリー
ドな有しない複数のリード３とそれらを連結するダム（
６）及び周辺のフレーム８のみからなるリードフレーム
を使用し、半導体素子の形成されたペレット４と、この
ペレットを取り囲む複数のリード３の内側部すなわちイ
ンナーリード３１を一平面で同時に支持固定する絶縁シ
ート片９を１し、ベレット４の電極とインナーリード３
ｍとの間をワイヤ５で接続するとともにペレットとリー
ドの一部な樹脂モールド体（７）で封止したものである
。。FIGS. 3 and 114 show the main parts of the semiconductor Mll according to the present invention. This semiconductor device includes a plurality of leads 3 that do not have tabs or tab suspension leads, and a dam (
6) Insulation that simultaneously supports and fixes the pellet 4 on which the semiconductor element is formed and the inner parts of the plurality of leads 3 surrounding the pellet, that is, the inner leads 31, on one plane by using a lead frame consisting only of the peripheral frame 8. Place the sheet piece 9 into 1, and attach the electrode of the pellet 4 and the inner lead 3.
A wire 5 is used to connect the lead to the lead, and the pellet is sealed with a resin molded body (7) which is a part of the lead. .
上記絶縁シート片９は飼えばポリイミド系樹脂のごとく
高耐熱性を有するもので、ベレットと複数のリードとの
間は適当な接着剤等を介して固着する。このように絶縁
シート片上にベレットな直接に支持固着すればタブ及び
タブ付きリードは不要であり、またインナーリードはペ
レットと１ｒｉｆｌ −平向に支持固定されることにな
り、前記発明の目的が達成できる。The insulating sheet piece 9 is made of a material having high heat resistance, such as polyimide resin, and is fixed between the pellet and the plurality of leads using a suitable adhesive or the like. If the pellet is directly supported and fixed on the insulating sheet piece in this way, tabs and tabbed leads are unnecessary, and the inner lead is supported and fixed parallel to the pellet, thereby achieving the object of the invention. can.
上記のような半導体装置は例えばｓ ｒ ｗＪ（ｍ ｓ
）〜（ｆ）Ｋ示すような各工程を有するプロセスによ
って製造することができる。For example, the semiconductor device as described above is s r wJ (m s
) to (f)K.
（ａ、Ｘａｌ） 半導体ウェハからスクライビングサ
レタヘレット４ｔ−移動する長尺の樹脂テープｌ。(a, Xal) A long resin tape l moving from a semiconductor wafer to a scribing sample 4t.
に所定間隔で接着する。テープには予め絶縁シート片の
形状にそって切り込み１ｓ１１ｆ：設けておく。Glue at specified intervals. Cuts 1s11f are made in advance on the tape along the shape of the insulating sheet piece.
（ｂｓＸ ｂｓ）多連のリードフレーム１２に対して上
記樹脂テープ１０を下から重ね合せ、ベレット位置決め
する。(bsX bs) The resin tape 10 is superimposed on the multiple lead frames 12 from below, and the pellets are positioned.
（Ｃ） テープをリードフレームのインナーリード部
分（３ａ）Ｋ１１着し、不要部を切り込みＷ６１１で切
り離す。インナーリードＫ１１１着されたテープを絶縁
シート片９とする。(C) Attach the tape to the inner lead part (3a) K11 of the lead frame and cut off the unnecessary part with the cut W611. The tape attached to the inner lead K111 is used as an insulating sheet piece 9.
（ｄ） ベレ１１）４の電極とインナーリードとの間の
ワイヤでワイヤボンディングｔａなう。(d) Wire bonding is performed with a wire between the electrode of bevel 11)4 and the inner lead.
（ｅ） 樹脂モールドを行ない、ベレットインナーリ
ード部分を樹脂モールド体７で封止し、リードフレーム
のアウターリード部分３ｂのみを外部に出す。(e) Perform resin molding, seal the bullet inner lead portion with the resin mold body 7, and expose only the outer lead portion 3b of the lead frame to the outside.
（ｆ） リードフレームや境界部、ダム部を切断し１
個々のベレット４を含む半導体装置に分離する。(f) Cut the lead frame, boundary part, and dam part 1
Separate into semiconductor devices including individual pellets 4.
以上実施例で述べた装置＃ＪＫよれば下記の効果がもた
らされる。According to the apparatus #JK described in the above embodiments, the following effects are brought about.
（１）インナリードが樹脂テープ（シート片）ｋよって
固定されたため、長いリードであ−ても上下に動くこと
がなくボンディング時の空打ちを防止でき、ボンディン
グ不良をな（すことができる。(1) Since the inner lead is fixed with the resin tape (sheet piece) k, even a long lead does not move up and down, preventing blank firing during bonding, and making it possible to avoid bonding defects.
（２）テープ（シート片）が絶縁体であるため、従来タ
ブやタブ吊りリードに被−した分の金メツキ量が節減で
きる。(2) Since the tape (sheet piece) is an insulator, the amount of gold plating that would conventionally be applied to tabs and tab suspension leads can be reduced.
（３； ペレット付けした部分が絶縁体であるととに
より、長いワイヤとタブとの接触によるシ１−ト不良は
生じない。(3) Since the part to which the pellet is attached is an insulator, sheet defects due to contact between the long wire and the tab do not occur.
（４（ベレット上向とリード上向とな同じ程度の高さに
保持しタブ下げ効果によってワイヤが短かくてすみ、ワ
イヤによる電圧降下が小さくなり、多くの電流な流すこ
とができる。又、ワイヤ材を節減できる。(4) By holding the upper part of the bullet and the upper part of the lead at the same height, the wire can be shortened due to the effect of lowering the tab, the voltage drop due to the wire is reduced, and a large amount of current can flow. Wire material can be saved.
＋５１ タブがなくなったことにより、タブ吊りリー
ドの占めていた空間なインナーリードとして利用でき、
リードフレームの設計に蒙裕ができる。+51 With the tab removed, the space previously occupied by the tab hanging lead can be used as an inner lead.
Meng Yu is able to design lead frames.
＋６） ＃向するインナーリードの間隔−（第４図ｄ
ｔ）を任意とすることができベレット寸法に制限がなく
なる。+6) Distance between inner leads facing # - (Fig. 4 d
t) can be made arbitrary, and there are no restrictions on the pellet size.
（７）第５図に示すように絶縁シート片９の下面にイン
ナーリード３ａＮ−接着する構造と°すること力ｉでき
る。この場合、対向するインナー；リード間隔（ｄＩ）
よりもベレット寸法を大きくし、その範囲でベレット寸
法を任意に這ぶことができる。(7) As shown in FIG. 5, it is possible to form a structure in which the inner leads 3aN are bonded to the lower surface of the insulating sheet piece 9. In this case, opposing inner; lead spacing (dI)
It is possible to make the pellet size larger than that and adjust the pellet size arbitrarily within that range.
（８）第６ｖ！ＪＫ示ｔＪ： ５ｔＣＪ７’（ｌｉ付＋
７− ）’７１／−ムにも本発明を適用することができ
る。(8) 6th v! JK shown tJ: 5tCJ7' (with li +
The present invention can also be applied to 7-) '71/-.
本発明ｔｔｓｎｉｔ封止用ＩＣ，特にリード数の多い半
導体装置に適用して有効である。The present invention is effective when applied to ttsnit encapsulation ICs, especially semiconductor devices with a large number of leads.
嬉１図はこれまでの半導体装置におけるリードフレーム
への゛半導体ベレットの組立蒙様を示す平ｔＩｉ図、第
２図は同正面図、亀３図は本発明による半導体装置Ｋお
けるリードフレームと半導体ベレットの組立一様の一例
を示す一部平向図１１１４図は同正面図、ａＳ図及び第
６図は本発明による半導体装置の他のｆＩ４ｔそれぞれ
放す正面図、第７図（ｉｔ） 、−（ａｍ） 、（ｂ＋
） −（ｂｔ） 、（Ｃ）〜（ｆ）は本発明による半導
体装置の組立時の各工程における形膝を示し、このうち
（ａｔ） （ｂｔ）は平ｍｗＪ。
（５１ｍ） 、（ｂｌ） 、（Ｃ） 〜（＜りは正１１
ＷｌｒＥｌｉｔ図、（ｆ）は正面図である。
ｌ・・・タブ、２・・・タブ吊りリード、３・・・リー
ド、４・・・半導体ペレット、５・・・ワイヤ、６・・
・ダム％７・・・樹脂モールド体、８・・・フレーム、
９・・・絶縁シート片、ｌＯ・・・樹脂テープ、１１・
・・切り込み部。
１２・・・リードフレーム。
第 ３５１１
第 ５ 図Figure 1 is a flat view showing how a semiconductor pellet is assembled into a lead frame in a conventional semiconductor device, Figure 2 is a front view of the same, and Figure 3 is a diagram showing a lead frame and semiconductor in a semiconductor device K according to the present invention. 1114 is a partial plan view showing an example of the uniform assembly of the pellet; FIG. 1114 is a front view of the same, FIG. (am) , (b+
) -(bt) and (C) to (f) show the shape knees in each step of assembling the semiconductor device according to the present invention, among which (at) (bt) is the flat mwJ. (51m) , (bl) , (C) ~(< is positive 11
WlrElit diagram, (f) is a front view. l...Tab, 2...Tab suspension lead, 3...Lead, 4...Semiconductor pellet, 5...Wire, 6...
・Dam% 7...Resin mold body, 8...Frame,
9... Insulating sheet piece, lO... Resin tape, 11.
...Notch part. 12...Lead frame. 3511 Figure 5
Claims (1)
り囲む複数のリードと、ペレットと複数のリードの内ｗ
部を一平面上で同時に支持固定するように設けた絶縁シ
ート片と、ペレットの電極とリードとの間に接続された
金属細線及び、ペレットとり−・ドの内端を包囲するよ
うに封止する樹脂モールド体から成る半導体装置。1. A pellet on which a semiconductor element is formed, a plurality of leads surrounding the pellet, and a portion of the pellet and the plurality of leads.
An insulating sheet piece provided to simultaneously support and fix the parts on one plane, a thin metal wire connected between the electrodes and leads of the pellet, and a seal that surrounds the inner end of the pellet tray. A semiconductor device consisting of a resin molded body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57026057A JPS58143541A (en) | 1982-02-22 | 1982-02-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57026057A JPS58143541A (en) | 1982-02-22 | 1982-02-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58143541A true JPS58143541A (en) | 1983-08-26 |
Family
ID=12183048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57026057A Pending JPS58143541A (en) | 1982-02-22 | 1982-02-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58143541A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60106158A (en) * | 1983-11-14 | 1985-06-11 | Toshiba Corp | Semiconductor device |
| JPS61296749A (en) * | 1985-06-25 | 1986-12-27 | Toray Silicone Co Ltd | Lead frame for semiconductor device |
| JPS6282747U (en) * | 1985-11-14 | 1987-05-27 | ||
| JPS63165846U (en) * | 1987-04-17 | 1988-10-28 | ||
| JPH0195760U (en) * | 1987-12-17 | 1989-06-26 | ||
| JPH0195759U (en) * | 1987-12-17 | 1989-06-26 | ||
| US4943843A (en) * | 1985-03-25 | 1990-07-24 | Hitachi, Ltd. | Semiconductor device |
| US20110309483A1 (en) * | 2007-10-19 | 2011-12-22 | Rohm Co., Ltd. | Semiconductor Device |
-
1982
- 1982-02-22 JP JP57026057A patent/JPS58143541A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60106158A (en) * | 1983-11-14 | 1985-06-11 | Toshiba Corp | Semiconductor device |
| US4943843A (en) * | 1985-03-25 | 1990-07-24 | Hitachi, Ltd. | Semiconductor device |
| JPS61296749A (en) * | 1985-06-25 | 1986-12-27 | Toray Silicone Co Ltd | Lead frame for semiconductor device |
| JPH0513382B2 (en) * | 1985-06-25 | 1993-02-22 | Dow Corning Toray Silicone | |
| JPS6282747U (en) * | 1985-11-14 | 1987-05-27 | ||
| JPS63165846U (en) * | 1987-04-17 | 1988-10-28 | ||
| JPH0195760U (en) * | 1987-12-17 | 1989-06-26 | ||
| JPH0195759U (en) * | 1987-12-17 | 1989-06-26 | ||
| US20110309483A1 (en) * | 2007-10-19 | 2011-12-22 | Rohm Co., Ltd. | Semiconductor Device |
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