JPH0180937U - - Google Patents
Info
- Publication number
- JPH0180937U JPH0180937U JP1987177430U JP17743087U JPH0180937U JP H0180937 U JPH0180937 U JP H0180937U JP 1987177430 U JP1987177430 U JP 1987177430U JP 17743087 U JP17743087 U JP 17743087U JP H0180937 U JPH0180937 U JP H0180937U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- ground
- bonding pads
- ground terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 6
Description
第１図は本考案の一実施例のレイアウト図、第
２図は本考案の実施例２のレイアウト図、第３図
は本考案の実施例３のレイアウト図、第４図、第
５図は従来のレイアウト図、第６図、第７図は第
１図から第５図のレイアウト図を説明する為の実
装状態のプリント板上のレイアウト図である。
１１，２１，３１，４１，５１……ＩＣチツプ
、１２，１２′，１３，１３′，２２，２２′，
２３，２３′，２４，２４′，３２，３２′，３
３，３３′，４３，５３，５３′……ボンデイン
グパツド、１４，１５，２５，２６，２７，３４
，３５，４２，５２，５２′……接地配線、６２
，７３，７３′……プリント板上の接地配線、７
４……プリント板の配線、６１，７１……ＩＣ、
６２，７２……ＩＣの端子。
Figure 1 is a layout diagram of an embodiment of the present invention, Figure 2 is a layout diagram of a second embodiment of the invention, Figure 3 is a layout diagram of a third embodiment of the invention, and Figures 4 and 5 are Conventional layout diagrams, FIGS. 6 and 7, are layout diagrams on a printed circuit board in a mounted state for explaining the layout diagrams of FIGS. 1 to 5. 11, 21, 31, 41, 51...IC chip, 12, 12', 13, 13', 22, 22',
23, 23', 24, 24', 32, 32', 3
3, 33', 43, 53, 53'...Bonding pad, 14, 15, 25, 26, 27, 34
, 35, 42, 52, 52'...Ground wiring, 62
, 73, 73'...Ground wiring on printed board, 7
4... Printed board wiring, 61, 71... IC,
62, 72...IC terminals.
Claims (1)
て、半導体集積回路上の接地配線は、各接地端子
に複数のボンデイングパツドを設け、各接地端子
間に独立した対をなすボンデイングパツド間に接
地配線することを特徴とする半導体集積回路。 In a semiconductor integrated circuit consisting of a plurality of ground terminals, the ground wiring on the semiconductor integrated circuit is provided with a plurality of bonding pads for each ground terminal, and the ground wiring is carried out between the bonding pads that form an independent pair between each ground terminal. A semiconductor integrated circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17743087U JPH0726841Y2 (en) | 1987-11-19 | 1987-11-19 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17743087U JPH0726841Y2 (en) | 1987-11-19 | 1987-11-19 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0180937U true JPH0180937U (en) | 1989-05-30 |
| JPH0726841Y2 JPH0726841Y2 (en) | 1995-06-14 |
Family
ID=31469094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17743087U Expired - Lifetime JPH0726841Y2 (en) | 1987-11-19 | 1987-11-19 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0726841Y2 (en) |
-
1987
- 1987-11-19 JP JP17743087U patent/JPH0726841Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0726841Y2 (en) | 1995-06-14 |