JPS6117737U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6117737U
JPS6117737U JP1984102103U JP10210384U JPS6117737U JP S6117737 U JPS6117737 U JP S6117737U JP 1984102103 U JP1984102103 U JP 1984102103U JP 10210384 U JP10210384 U JP 10210384U JP S6117737 U JPS6117737 U JP S6117737U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
circuited
short
leads
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984102103U
Other languages
Japanese (ja)
Inventor
滋 鍵山
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1984102103U priority Critical patent/JPS6117737U/en
Publication of JPS6117737U publication Critical patent/JPS6117737U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の実施例の平面図である。 図において、１・・・・・・半導体チップ、２・・曲フ
ィルムキャリア、３・・・・・・接地母線、４・・・・
・・銅リード、である。FIG. 1 is a plan view of an embodiment of the present invention. In the figure, 1...semiconductor chip, 2...curved film carrier, 3...ground bus bar, 4...
...copper lead.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体チップのパッドに接続される全てのリードを短絡
しかつ隣接するフレームのリード同志をも短絡したリー
ドパターンを有してフィルムキャリア上に実装されたこ
とを特徴とする半導体装置。1. A semiconductor device, characterized in that it has a lead pattern in which all leads connected to pads of a semiconductor chip are short-circuited and leads in adjacent frames are also short-circuited, and is mounted on a film carrier.
JP1984102103U 1984-07-06 1984-07-06 semiconductor equipment Pending JPS6117737U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984102103U JPS6117737U (en) 1984-07-06 1984-07-06 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984102103U JPS6117737U (en) 1984-07-06 1984-07-06 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS6117737U true JPS6117737U (en) 1986-02-01

Family

ID=30661511

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984102103U Pending JPS6117737U (en) 1984-07-06 1984-07-06 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6117737U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413129U (en) * 1987-07-14 1989-01-24

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413129U (en) * 1987-07-14 1989-01-24

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