JPS6039245U - Wire bonding positioning mark - Google Patents

Wire bonding positioning mark

Info

Publication number
JPS6039245U
JPS6039245U JP13130883U JP13130883U JPS6039245U JP S6039245 U JPS6039245 U JP S6039245U JP 13130883 U JP13130883 U JP 13130883U JP 13130883 U JP13130883 U JP 13130883U JP S6039245 U JPS6039245 U JP S6039245U
Authority
JP
Japan
Prior art keywords
wire bonding
positioning mark
bonding positioning
chips
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13130883U
Other languages
Japanese (ja)
Inventor
浩 青木
Original Assignee
御代田精密株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 御代田精密株式会社 filed Critical 御代田精密株式会社
Priority to JP13130883U priority Critical patent/JPS6039245U/en
Publication of JPS6039245U publication Critical patent/JPS6039245U/en
Pending legal-status Critical Current

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  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のワイヤーボンディング前の回路基板の平
面図、第2図は本考案のワイヤーボンディング前の回路
基板の平面図。 1.11・・・回路基板、2〜4,12〜14・・・I
Cチップ、5〜10.15〜18・・・位置決めマーク
FIG. 1 is a plan view of a conventional circuit board before wire bonding, and FIG. 2 is a plan view of the circuit board of the present invention before wire bonding. 1.11...Circuit board, 2-4, 12-14...I
C chip, 5-10.15-18...positioning mark.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のICチップが、基板上の同一面側に実装される場
合に於て、基板上に設けられたワイヤーボンディングの
位置決めマークが複数のICチップに共通に使用される
ことを特徴とするワイヤーボンディングの位置決めマー
ク。
Wire bonding characterized in that when a plurality of IC chips are mounted on the same side of a substrate, a wire bonding positioning mark provided on the substrate is commonly used for the plurality of IC chips. positioning mark.
JP13130883U 1983-08-24 1983-08-24 Wire bonding positioning mark Pending JPS6039245U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13130883U JPS6039245U (en) 1983-08-24 1983-08-24 Wire bonding positioning mark

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13130883U JPS6039245U (en) 1983-08-24 1983-08-24 Wire bonding positioning mark

Publications (1)

Publication Number Publication Date
JPS6039245U true JPS6039245U (en) 1985-03-19

Family

ID=30296902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13130883U Pending JPS6039245U (en) 1983-08-24 1983-08-24 Wire bonding positioning mark

Country Status (1)

Country Link
JP (1) JPS6039245U (en)

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