JPS645450U

JPS645450U -

Info

Publication number: JPS645450U
Application number: JP9871387U
Authority: JP
Priority date: 1987-06-26
Filing date: 1987-06-26
Publication date: 1989-01-12

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例のＩＣチツプの断面
斜視図、第２図は従来の集積回路チツプの斜視図
である。１……半導体基板、２……ドレイン領域、３…
…ソース領域、５Ｇ……ゲート絶縁層、５ａ，５
ｂ……絶縁層、６……開孔部、７ａ，７ｂ，７ｄ
，７Ｓ……Ａｌ配線層、１０……ＩＣチツプ。 FIG. 1 is a cross-sectional perspective view of an IC chip according to an embodiment of the present invention, and FIG. 2 is a perspective view of a conventional integrated circuit chip. 1... Semiconductor substrate, 2... Drain region, 3...
...Source region, 5G...Gate insulating layer, 5a, 5
b...Insulating layer, 6...Opening portion, 7a, 7b, 7d
, 7S... Al wiring layer, 10... IC chip.

補正昭６３．４．２６図面の簡単な説明を次のように補正する。明細書の第５頁第７行目の各「ドレイン」を「
ソース」に補正する。明細書の第５頁第７〜８行目の各「ソース」を
「ドレイン」に補正する。明細書の第５頁第７行目の各「半導体基板」を
「ｎ型半導体基板」に補正する。Amendment April 26, 1981 The brief description of the drawing is amended as follows. Each “drain” on page 5, line 7 of the specification is replaced with “
Source”. Each "source" in lines 7 and 8 on page 5 of the specification is corrected to "drain". Each "semiconductor substrate" on page 5, line 7 of the specification is corrected to "n-type semiconductor substrate."

Claims

[Scope of utility model registration request]

In an integrated circuit in which an IC chip is resin-sealed, in which at least one conductive layer is formed on the surface of a semiconductor substrate having an element formation region on one principal surface with an insulating film interposed therebetween, the uppermost layer of the conductive layer is formed in the element formation region. an integrated circuit, characterized in that the top layer is connected to one of the power supply terminals of the integrated circuit.