JPH0183339U

JPH0183339U -

Info

Publication number: JPH0183339U
Application number: JP1987179181U
Authority: JP
Priority date: 1987-11-24
Filing date: 1987-11-24
Publication date: 1989-06-02

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例の主要部を示す模式
レイアウト図、第２図は従来例の模式レイアウト
図である。１…第１ＶＤＤ線、２…第１ＧＮＤ線、３…第
２ＶＤＤ線、４…第２ＧＮＤ線、５…第３ＶＤＤ
線、６…第３ＧＮＤ線、７…第４ＶＤＤ線、８…
第４ＧＮＤ線、９，１０，１１，１２，１７，１
７′，１８，１８′…ＶＤＤパツド、１３，１４
，１５，１６，１９，２０…ＧＮＤパツド。 FIG. 1 is a schematic layout diagram showing the main parts of an embodiment of the present invention, and FIG. 2 is a schematic layout diagram of a conventional example. 1...1st VDD line, 2...1st GND line, 3...2nd VDD line, 4...2nd GND line, 5...3rd VDD
line, 6...3rd GND line, 7...4th VDD line, 8...
4th GND line, 9, 10, 11, 12, 17, 1
7', 18, 18'...VDD pad, 13, 14
, 15, 16, 19, 20...GND pad.

Claims

[Scope of utility model registration request]

a first VDD line and a first GND line arranged around the periphery of the semiconductor chip;
A fourth VDD line and a fourth GND line are arranged to approximately equally divide the area surrounded by the line and the first GND line, respectively, and a fourth VDD line and a fourth GND line are arranged in parallel to the first VDD line and the first GND line, respectively, in the vertical direction. The connected second VDD line and second GND line are arranged horizontally in parallel with the first VDD line and the second GND line, respectively.
line and a third VDD connected to the first GND line.
A gate array type semiconductor device having a fourth VDD line and a third GND line, wherein the fourth VDD line and the fourth GND line are connected to independent VDD pads and GND pads, respectively. .