JPH02137044U - - Google Patents

Info

Publication number
JPH02137044U
JPH02137044U JP1989043726U JP4372689U JPH02137044U JP H02137044 U JPH02137044 U JP H02137044U JP 1989043726 U JP1989043726 U JP 1989043726U JP 4372689 U JP4372689 U JP 4372689U JP H02137044 U JPH02137044 U JP H02137044U
Authority
JP
Japan
Prior art keywords
semiconductor device
divided
electrode pads
electrode pad
columns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989043726U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989043726U priority Critical patent/JPH02137044U/ja
Publication of JPH02137044U publication Critical patent/JPH02137044U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/0554—External layer
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    • H01L2224/05554—Shape in top view being square
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    • H01L2224/061—Disposition
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    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
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    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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    • H01L2924/161—Cap
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    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の第１の実施例の部分平面図、
第２図は本考案の第２の実施例の部分平面図、第
３図はその縦断面図、第４図及び第５図はそれぞ
れ従来の電極パツドレイアウト構造を示す部分平
面図である。 １……半導体素子、２……電極パツド、２ａ…
…電源端子用電極パツド、２ｂ……信号端子用電
極パツド、３……半導体装置パツケージ、４……
金属ワイヤ、５……内部リード、５ａ……電源用
内部リード、５ｂ……信号用内部リード、６……
リツド、７……外部リード。 FIG. 1 is a partial plan view of the first embodiment of the present invention;
FIG. 2 is a partial plan view of a second embodiment of the present invention, FIG. 3 is a vertical sectional view thereof, and FIGS. 4 and 5 are partial plan views showing conventional electrode pad layout structures, respectively. 1... Semiconductor element, 2... Electrode pad, 2a...
...Electrode pad for power supply terminal, 2b...Electrode pad for signal terminal, 3...Semiconductor device package, 4...
Metal wire, 5... Internal lead, 5a... Internal lead for power supply, 5b... Internal lead for signal, 6...
Lead, 7...External lead.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子上面の外周に沿って配列された電極
パツドの全部又は一部を少なくとも２列以上に分
割し、分割した同一電極パツドはそれぞれ同一行
上に並列配置されていることを特徴とする半導体
素子の電極パツドレイアウト構造。 A semiconductor device characterized in that all or part of the electrode pads arranged along the outer periphery of the upper surface of the semiconductor device are divided into at least two or more columns, and the divided identical electrode pads are arranged in parallel on the same row. electrode pad layout structure.
JP1989043726U 1989-04-14 1989-04-14 Pending JPH02137044U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989043726U JPH02137044U (en) 1989-04-14 1989-04-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989043726U JPH02137044U (en) 1989-04-14 1989-04-14

Publications (1)

Publication Number Publication Date
JPH02137044U true JPH02137044U (en) 1990-11-15

Family

ID=31556382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989043726U Pending JPH02137044U (en) 1989-04-14 1989-04-14

Country Status (1)

Country Link
JP (1) JPH02137044U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007501537A (en) * 2003-06-09 2007-01-25 フリースケール セミコンダクター インコーポレイテッド Semiconductor package with optimized wire bond positioning

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007501537A (en) * 2003-06-09 2007-01-25 フリースケール セミコンダクター インコーポレイテッド Semiconductor package with optimized wire bond positioning

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