JPS62177038U - - Google Patents
Info
- Publication number
- JPS62177038U JPS62177038U JP6599186U JP6599186U JPS62177038U JP S62177038 U JPS62177038 U JP S62177038U JP 6599186 U JP6599186 U JP 6599186U JP 6599186 U JP6599186 U JP 6599186U JP S62177038 U JPS62177038 U JP S62177038U
- Authority
- JP
- Japan
- Prior art keywords
- bonding pads
- bonding
- chip
- square
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第1図は本考案の一実施例を示す平面図である
。
a…チツプの端から最初のボンデイングパツド
までの距離、b…ボンデイングパツドサイズ、c
…パツドの端から端までの間隔、1…チツプ、2
…ボンデイングパツド、3…内部セル。
FIG. 1 is a plan view showing an embodiment of the present invention. a...Distance from the tip end to the first bonding pad, b...Bonding pad size, c
...Distance from end to end of pad, 1...Tip, 2
...bonding pad, 3...internal cell.
Claims (1)
正方形になるように配列し、合計のボンデイング
パツド数を4の整数倍とし、ボンデイングパツド
間隔を製造上可能な最小間隔としたことを特徴と
する半導体集積回路。 A semiconductor characterized in that bonding pads are arranged at equal intervals so that the chip is square, the total number of bonding pads is an integral multiple of 4, and the bonding pad spacing is the minimum interval possible in manufacturing. integrated circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6599186U JPS62177038U (en) | 1986-04-28 | 1986-04-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6599186U JPS62177038U (en) | 1986-04-28 | 1986-04-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62177038U true JPS62177038U (en) | 1987-11-10 |
Family
ID=30903576
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6599186U Pending JPS62177038U (en) | 1986-04-28 | 1986-04-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62177038U (en) |
-
1986
- 1986-04-28 JP JP6599186U patent/JPS62177038U/ja active Pending