JPS6422047U - - Google Patents
Info
- Publication number
- JPS6422047U JPS6422047U JP11690287U JP11690287U JPS6422047U JP S6422047 U JPS6422047 U JP S6422047U JP 11690287 U JP11690287 U JP 11690287U JP 11690287 U JP11690287 U JP 11690287U JP S6422047 U JPS6422047 U JP S6422047U
- Authority
- JP
- Japan
- Prior art keywords
- lead
- affixed
- resistant
- tip
- once
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第1図は本考案の一実施例を示す平面図、第2
図は第1図の側面図である。
1……IC本体、2……リード、3……テープ
。
Fig. 1 is a plan view showing one embodiment of the present invention;
The figure is a side view of FIG. 1. 1...IC body, 2...lead, 3...tape.
Claims (1)
び絶縁性テープを貼つたことを有することを特徴
とするフラツトタイプ集積回路。 A flat type integrated circuit characterized in that a plurality of heat-resistant and insulating tapes are affixed to the tip of each lead at once.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11690287U JPS6422047U (en) | 1987-07-29 | 1987-07-29 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11690287U JPS6422047U (en) | 1987-07-29 | 1987-07-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6422047U true JPS6422047U (en) | 1989-02-03 |
Family
ID=31359864
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11690287U Pending JPS6422047U (en) | 1987-07-29 | 1987-07-29 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6422047U (en) |
-
1987
- 1987-07-29 JP JP11690287U patent/JPS6422047U/ja active Pending