JPH01160841U - - Google Patents
Info
- Publication number
- JPH01160841U JPH01160841U JP1988049666U JP4966688U JPH01160841U JP H01160841 U JPH01160841 U JP H01160841U JP 1988049666 U JP1988049666 U JP 1988049666U JP 4966688 U JP4966688 U JP 4966688U JP H01160841 U JPH01160841 U JP H01160841U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- stitch portion
- package
- semiconductor device
- stitch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15157—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例の平面図、第２図は
第１図のＡ―Ａ線に沿う断面図、第３図は本考案
の他の実施例の平面図である。
１…パツケージベース、２…アイランド部、３
…ステツチ部、４…外部リード端子、５…逃げ部
、６…半導体チツプ、７…電極パツド、８…金属
ワイヤ。
FIG. 1 is a plan view of one embodiment of the present invention, FIG. 2 is a sectional view taken along line AA in FIG. 1, and FIG. 3 is a plan view of another embodiment of the present invention. 1...Package base, 2...Island part, 3
... Stitch portion, 4... External lead terminal, 5... Relief portion, 6... Semiconductor chip, 7... Electrode pad, 8... Metal wire.
Claims (1)
半導体チツプと略同じ高さで前記アイランド部の
周囲に設けたステツチ部と、このステツチ部の上
に形成して金属ワイヤにより前記半導体チツプに
電気接続される外部リード端子とを備える半導体
装置用パツケージにおいて、前記ステツチ部は半
導体チツプとの間隔が可及的に小さくなるように
構成するとともに、ステツチ部の少なくとも２つ
の対角位置に外側に向けて凹設した逃げ部を形成
したことを特徴とする半導体装置用パツケージ。 an island portion on which a semiconductor chip is mounted; a stitch portion provided around the island portion at approximately the same height as the semiconductor chip; and a stitch portion formed on the stitch portion and electrically connected to the semiconductor chip by a metal wire. In a package for a semiconductor device including external lead terminals, the stitch portion is configured so that the distance from the semiconductor chip is as small as possible, and at least two diagonal positions of the stitch portion are recessed outward. A package for a semiconductor device, characterized in that a package for a semiconductor device is formed with a relief part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988049666U JPH01160841U (en) | 1988-04-13 | 1988-04-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988049666U JPH01160841U (en) | 1988-04-13 | 1988-04-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01160841U true JPH01160841U (en) | 1989-11-08 |
Family
ID=31275753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988049666U Pending JPH01160841U (en) | 1988-04-13 | 1988-04-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01160841U (en) |
-
1988
- 1988-04-13 JP JP1988049666U patent/JPH01160841U/ja active Pending