JPH0418439U - - Google Patents
Info
- Publication number
- JPH0418439U JPH0418439U JP5992290U JP5992290U JPH0418439U JP H0418439 U JPH0418439 U JP H0418439U JP 5992290 U JP5992290 U JP 5992290U JP 5992290 U JP5992290 U JP 5992290U JP H0418439 U JPH0418439 U JP H0418439U
- Authority
- JP
- Japan
- Prior art keywords
- lead electrodes
- package
- chip
- semiconductor package
- simplified
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例による半導体パツケ
ージの断面図、第２図は従来の半導体パツケージ
の断面図である。
図において、１は半導体チツプ、２はパツケー
ジ下部、４は金ワイヤ、５はリード電極、６はキ
ヤツプを示す。なお、図中、同一符号は同一、ま
たは相当部分を示す。
FIG. 1 is a sectional view of a semiconductor package according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor package. In the figure, 1 is a semiconductor chip, 2 is a lower part of a package, 4 is a gold wire, 5 is a lead electrode, and 6 is a cap. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
化し、かつ、チツプから直接リード電極にワイヤ
リングしたことを特徴とする半導体パツケージ。 A semiconductor package characterized in that the lead electrodes inside the package are simplified into a flat plate shape, and the lead electrodes are wired directly from the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5992290U JPH0418439U (en) | 1990-06-05 | 1990-06-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5992290U JPH0418439U (en) | 1990-06-05 | 1990-06-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0418439U true JPH0418439U (en) | 1992-02-17 |
Family
ID=31586850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5992290U Pending JPH0418439U (en) | 1990-06-05 | 1990-06-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0418439U (en) |
-
1990
- 1990-06-05 JP JP5992290U patent/JPH0418439U/ja active Pending