JPS6214725U - - Google Patents
Info
- Publication number
- JPS6214725U JPS6214725U JP10586085U JP10586085U JPS6214725U JP S6214725 U JPS6214725 U JP S6214725U JP 10586085 U JP10586085 U JP 10586085U JP 10586085 U JP10586085 U JP 10586085U JP S6214725 U JPS6214725 U JP S6214725U
- Authority
- JP
- Japan
- Prior art keywords
- land portion
- leads
- semiconductor pellet
- view
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 3
- 239000008188 pellet Substances 0.000 claims description 3
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案をモノリシツクＩＣに適用した
第１の実施例を示す半導体装置の平面図、第２図
は第１図に示す第１の実施例の変形例を示す平面
図、第３図は本考案のハイブリツドＩＣに適用し
た第２の実施例を示す半導体装置の平面図、第４
図は第３図の部分拡大図、第５図は第３の実施例
を示す半導体装置の平面図である。第６図はモノ
リシツクＩＣの一例を示す平面図、第７図は第６
図の正断面図、第８図はハイブリツドＩＣの一例
を示す平面図、第９図は第８図に示したものの正
断面図である。
１７，１７’，２３……リードフレーム、１８
，１８’，２８……リード、１９，１９’，２５
……ランド部、２１，２７……半導体ペレツト、
２２，２９……金属細線（ワイヤ）。
FIG. 1 is a plan view of a semiconductor device showing a first embodiment in which the present invention is applied to a monolithic IC, FIG. 2 is a plan view showing a modification of the first embodiment shown in FIG. 1, and FIG. 4 is a plan view of a semiconductor device showing a second embodiment applied to a hybrid IC of the present invention;
The figure is a partially enlarged view of FIG. 3, and FIG. 5 is a plan view of a semiconductor device showing a third embodiment. Fig. 6 is a plan view showing an example of a monolithic IC, and Fig. 7 is a plan view showing an example of a monolithic IC.
8 is a plan view showing an example of a hybrid IC, and FIG. 9 is a front sectional view of the one shown in FIG. 8. 17, 17', 23...Lead frame, 18
, 18', 28... lead, 19, 19', 25
... Land portion, 21, 27 ... Semiconductor pellet,
22, 29...Thin metal wire (wire).
Claims (1)
ペレツトを固着マウントし、上部ランド部の近傍
まで延びてくる複数のリードの先端と、上記半導
体ペレツトとを、金属細線で電気的に接続してな
る半導体装置において、 上記複数のリードをランド部に向かつて放射状
に配置したことを特徴とする半導体装置。[Claim for Utility Model Registration] A semiconductor pellet is fixedly mounted on the land portion of a metal lead frame, and the tips of a plurality of leads extending to the vicinity of the upper land portion and the semiconductor pellet are connected with a thin metal wire. A semiconductor device electrically connected, characterized in that the plurality of leads are arranged radially toward a land portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10586085U JPS6214725U (en) | 1985-07-11 | 1985-07-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10586085U JPS6214725U (en) | 1985-07-11 | 1985-07-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6214725U true JPS6214725U (en) | 1987-01-29 |
Family
ID=30980685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10586085U Pending JPS6214725U (en) | 1985-07-11 | 1985-07-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6214725U (en) |
-
1985
- 1985-07-11 JP JP10586085U patent/JPS6214725U/ja active Pending