JPH0195760U - - Google Patents

Info

Publication number
JPH0195760U
JPH0195760U JP1987192376U JP19237687U JPH0195760U JP H0195760 U JPH0195760 U JP H0195760U JP 1987192376 U JP1987192376 U JP 1987192376U JP 19237687 U JP19237687 U JP 19237687U JP H0195760 U JPH0195760 U JP H0195760U
Authority
JP
Japan
Prior art keywords
tab
protrusion
outer frame
semiconductor chip
lead patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987192376U
Other languages
Japanese (ja)
Other versions
JP2529366Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987192376U priority Critical patent/JP2529366Y2/en
Publication of JPH0195760U publication Critical patent/JPH0195760U/ja
Application granted granted Critical
Publication of JP2529366Y2 publication Critical patent/JP2529366Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の実施例を示す断面図、第２図
は第１図の―断面図、第３図乃至第５図は従
来例を示す断面図及び平面図である。 １……リードフレーム、２……半導体チツプ、
３……インナーリード、４……外部リード、５…
…外枠、６……タイバー、７……タブ、８……絶
縁フイルム、９……突出部、１０……ワイヤー。 FIG. 1 is a cross-sectional view showing an embodiment of the present invention, FIG. 2 is a cross-sectional view taken from FIG. 1, and FIGS. 3 to 5 are a cross-sectional view and a plan view showing a conventional example. 1...Lead frame, 2...Semiconductor chip,
3...Inner lead, 4...External lead, 5...
...Outer frame, 6...Tie bar, 7...Tab, 8...Insulating film, 9...Protrusion, 10...Wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リードパターンを支持固定する金属製の外枠と
、前記外枠に連結支持されてこの外枠で囲まれた
領域内に延在され、且つその先端が半導体チツプ
を固着する突出部を有したタブを取り囲む様に配
設された多数の金属製リードパターンと、前記タ
ブの突出部を囲むと共に前記半導体チツプの大き
さに対応してその大きさが任意に設定され前記リ
ードパターン上に接着された矩形状の絶縁フイル
ムと、前記タブの突出部と密接させ前記絶縁フイ
ルム上に固着された半導体チツプとを具備したこ
とを特徴とする半導体装置。 A metal outer frame for supporting and fixing a lead pattern, and a tab that is connected and supported by the outer frame and extends into an area surrounded by the outer frame, and has a protrusion whose tip fixes a semiconductor chip. A large number of metal lead patterns are arranged to surround the tab, and a plurality of metal lead patterns, which surround the protrusion of the tab and whose size is arbitrarily set according to the size of the semiconductor chip, are glued onto the lead patterns. 1. A semiconductor device comprising a rectangular insulating film and a semiconductor chip fixed on the insulating film in close contact with the protrusion of the tab.
JP1987192376U 1987-12-17 1987-12-17 Semiconductor device Expired - Lifetime JP2529366Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987192376U JP2529366Y2 (en) 1987-12-17 1987-12-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987192376U JP2529366Y2 (en) 1987-12-17 1987-12-17 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0195760U true JPH0195760U (en) 1989-06-26
JP2529366Y2 JP2529366Y2 (en) 1997-03-19

Family

ID=31483238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987192376U Expired - Lifetime JP2529366Y2 (en) 1987-12-17 1987-12-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2529366Y2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612360U (en) * 1979-07-04 1981-02-02
JPS5895657U (en) * 1981-12-23 1983-06-29 日本電気株式会社 Lead frame for integrated circuits
JPS58143541A (en) * 1982-02-22 1983-08-26 Hitachi Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612360U (en) * 1979-07-04 1981-02-02
JPS5895657U (en) * 1981-12-23 1983-06-29 日本電気株式会社 Lead frame for integrated circuits
JPS58143541A (en) * 1982-02-22 1983-08-26 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JP2529366Y2 (en) 1997-03-19

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