JPH01100457U - - Google Patents

Info

Publication number
JPH01100457U
JPH01100457U JP1987195253U JP19525387U JPH01100457U JP H01100457 U JPH01100457 U JP H01100457U JP 1987195253 U JP1987195253 U JP 1987195253U JP 19525387 U JP19525387 U JP 19525387U JP H01100457 U JPH01100457 U JP H01100457U
Authority
JP
Japan
Prior art keywords
outer frame
lead pattern
metal
insulating film
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987195253U
Other languages
Japanese (ja)
Other versions
JP2516390Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987195253U priority Critical patent/JP2516390Y2/en
Publication of JPH01100457U publication Critical patent/JPH01100457U/ja
Application granted granted Critical
Publication of JP2516390Y2 publication Critical patent/JP2516390Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の実施例を示す平面図、第２図
は第１図の―断面図、第３図乃至第５図は従
来例を示す断面図及び平面図である。 １……リードフレーム、２……半導体チツプ、
３……インナーリード、４……外部リード、５…
…外枠、６……タイバー、７……金属箔、８……
絶縁フイルム、９……接続領域、１０……ワイヤ
ー。 FIG. 1 is a plan view showing an embodiment of the present invention, FIG. 2 is a cross-sectional view of FIG. 1, and FIGS. 3 to 5 are a cross-sectional view and a plan view showing a conventional example. 1...Lead frame, 2...Semiconductor chip,
3...Inner lead, 4...External lead, 5...
...Outer frame, 6...Tie bar, 7...Metal foil, 8...
Insulating film, 9... connection area, 10... wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リードパターンを支持固定する金属製の外枠と
、前記外枠に連結支持され前記外枠で囲まれた領
域内の略中心部分を取り囲み、且つその先端部の
長さが少なくとも交互に異なる様に延在された金
属製リードパターンと、前記半導体チツプの大き
さに対応してその大きさが任意に設定され、前記
リードパターン上に接着された矩形状の絶縁フイ
ルムと、前記フイルム上に貼着されボンデイング
接続される接続領域を有する金属箔と、前記金属
箔上に固着された前記半導体チツプと前記リード
パターンの一端とを接続するボンデイングワイヤ
ーとを具備したことを特徴とする半導体装置。 A metal outer frame that supports and fixes the lead pattern; and a metal outer frame that is connected and supported by the outer frame, surrounds a substantially central portion within an area surrounded by the outer frame, and has tip portions whose lengths are at least alternately different. an extended metal lead pattern, a rectangular insulating film whose size is arbitrarily set according to the size of the semiconductor chip, and which is adhered onto the lead pattern; and a rectangular insulating film which is adhered onto the film. 1. A semiconductor device comprising: a metal foil having a connection region for bonding connection; and a bonding wire connecting the semiconductor chip fixed on the metal foil and one end of the lead pattern.
JP1987195253U 1987-12-23 1987-12-23 Semiconductor device Expired - Lifetime JP2516390Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987195253U JP2516390Y2 (en) 1987-12-23 1987-12-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987195253U JP2516390Y2 (en) 1987-12-23 1987-12-23 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH01100457U true JPH01100457U (en) 1989-07-05
JP2516390Y2 JP2516390Y2 (en) 1996-11-06

Family

ID=31485939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987195253U Expired - Lifetime JP2516390Y2 (en) 1987-12-23 1987-12-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2516390Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010097511A (en) * 2000-04-24 2001-11-08 이중구 Double-layer chip scale semiconductor package and method therefor

Also Published As

Publication number Publication date
JP2516390Y2 (en) 1996-11-06

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