JP2001203272A - Method for designing layout of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for designing the layout of a semiconductor integrated circuit wherein its peak power-supply current is suppressed and its radiant noise is reduced without increasing its chip area. SOLUTION: In the method for designing the layout of a semiconductor integrated circuit, there are included a step S110 for generating functional block and wiring layouts of its layout, a step S120 for laying fully such dummy patterns in an idle region other than the positioning regions of the functional block and wiring layouts which is also present in its layout as to adjust the area factor of its layout, and a step S130 for generating capacitor layouts provided in the dummy region wherein the dummy patterns are laid fully.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout design method for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, in layout design of a semiconductor integrated circuit, design automation is indispensable in order to improve design productivity, and a synchronous circuit design is employed for design automation. . In a semiconductor integrated circuit (for example, LSI) of a synchronous circuit design, all circuits operate in synchronization with a reference clock, so that the instantaneous current (peak power supply current) of the semiconductor integrated circuit increases. When the instantaneous current increases, a sharp power supply fluctuation caused by the instantaneous current causes L
Direct devices such as wires in the SI, lead frames or wiring on a printed circuit board affect other devices, and noise is generated when these connection paths serve as antennas. In particular, in a recent LSI in which high speed and miniaturization are advanced, an instantaneous current becomes extremely large, and as a result, noise is increased.

Hereinafter, with reference to FIGS. 9 and 10,
A conventional LSI layout design method will be described. FIG.
7 shows a mask pattern layout (chip layout) designed by a conventional LSI layout design method. FIG. 10 is a flowchart illustrating a conventional LSI layout designing method. In this specification, the “layout” refers to a layout that defines a geometric structure of a semiconductor integrated circuit. For example, a functional block layout that defines a geometric structure of a functional block, a wiring geometry, or the like. Wiring layout that defines the geometric structure.

[0004] A chip layout 101 shown in FIG. 9 includes a plurality of functional block layouts 102 and a power supply wiring layout 103 connected to the functional block layout 102.
And a signal wiring layout 104. Functional block layout 102, power supply wiring (or ground wiring) 103 layout, and signal wiring layout 10
Dummy patterns 105 for adjusting the area ratio of the chip layout 101 are laid out in the free area in the chip layout 101 other than the area where No. 4 is located. In this specification, the area where the dummy patterns 105 are spread is referred to as a dummy area 106. The dummy pattern 105 is used for adjusting the area ratio of the chip layout 101, and is not used for other purposes.

The chip layout 101 is designed as shown in FIG. First, in the arrangement and wiring step S510, the arrangement position of the functional block layout 102, the power supply wiring layout 103, and the signal wiring layout 1
04 is determined.

Next, in a dummy pattern generation step S520, a dummy pattern 105 is generated in the chip layout 101 created in the placement and wiring step S510. By generating the dummy pattern 105, the chip layout 10 is adjusted so that the area ratio becomes optimum in the manufacturing process.
Adjust the area ratio of 1.

Next, in a mask verification step S530,
After performing the design rule check and the comparison verification between the mask and the circuit, the mask processing step S540 performs an arithmetic process necessary for mask manufacturing. Thus, the conventional LSI layout design method has been executed.

[0008]

However, in the above-mentioned conventional LSI layout design method, no measures are taken to reduce the noise radiated from the LSI, so that it is not possible to prevent an increase in noise generation.

Japanese Patent No. 2724193 discloses a technique for forming a power supply line and a ground line around a specific line and arranging a capacitor region in order to reduce noise. However, in order to implement this technique, it is necessary to generate a capacitor region in a layout design process, which causes an inconvenience of increasing the chip area. Further, this technique does not assume that an empty area of the chip layout after the placement and routing process is used.

The present invention has been made in view of the above points, and a main object of the present invention is to provide a layout design method of a semiconductor integrated circuit in which a peak power supply current is suppressed without increasing a chip area and radiated noise is reduced. Is to provide.

[0011]

SUMMARY OF THE INVENTION The present inventor has proposed a dummy pattern for adjusting the area ratio of a chip layout to add a power supply capacity to a dummy region, thereby suppressing a peak power supply current without increasing the chip area. And found that the present invention can be performed.

According to the semiconductor integrated circuit layout designing method of the present invention, a functional block layout of the semiconductor integrated circuit layout, and a wiring including a signal wiring layout, a power wiring layout, and a ground wiring layout for connecting the functional block layouts are provided. Generating a layout, and laying a dummy pattern for adjusting an area ratio of the semiconductor integrated circuit layout in an empty area in the semiconductor integrated circuit layout other than the area where the functional block layout and the wiring layout are located; A step of generating a capacitor layout including a plurality of capacitor electrode layer layouts, each of which is arranged in a dummy region in which the dummy patterns are spread and each of which is connected to the power supply wiring layout or the ground wiring layout; It encompasses the door, thereby to achieve the object.

Preferably, each of the plurality of capacitor electrode layer layouts has the same shape as the dummy pattern.

It is preferable to generate a capacitor layout in which a capacitor electrode layer layout connected to the power supply wiring layout and a capacitor electrode layer layout connected to the ground wiring layout are alternately stacked.

In one embodiment, each of the plurality of capacitance electrode layer layouts is formed in a comb shape, and the capacitance electrode layer layout connected to the power supply wiring layout and the capacitance electrode layer layout connected to the ground wiring layout And generating a capacitor layout having a comb-shaped electrode structure.

In one embodiment, the method further includes a step of generating a capacitance cell layout disposed below the capacitance layout in the dummy region and connected to the capacitance layout.

According to the present invention, since a capacitance layout is generated in a dummy region in which dummy patterns for adjusting the area ratio of the semiconductor integrated circuit are spread, a layout design of the semiconductor integrated circuit in which the capacitance is formed in the dummy region is performed. be able to. When the capacitance is formed in the dummy area,
Since this capacitance (capacitor) can be used as a local power supply for the high-frequency power supply current accompanying the circuit operation, the peak power supply current can be suppressed. If the peak power supply current can be suppressed, the influence of the power supply current containing many high-frequency components can be prevented from being emitted to other circuits in the semiconductor integrated circuit (or to the outside of the semiconductor integrated circuit).
Noise radiated from the semiconductor integrated circuit can be reduced. Further, since the capacitance is formed in the dummy region, the layout area of the semiconductor integrated circuit does not increase.

Since each of the plurality of capacitor electrode layer layouts has the same shape as the dummy pattern, the dummy pattern spread over the empty area of the semiconductor integrated circuit layout can be used as the capacitor layout. Use efficiency can be improved. Also, an electrode wiring layer layout connected to the power supply wiring layout for the purpose of capacitance creation (capacitance electrode layer layout connected to the power supply wiring layout) and an electrode wiring layer connected to the ground wiring layout for the purpose of capacity creation By generating a capacitor layout in which a layout (a capacitor electrode layer layout connected to a ground wiring layout) is alternately stacked, a semiconductor integrated circuit layout in which a power supply capacitor is added to a dummy region can be easily designed. As the capacitor electrode layer layout, for example, an aluminum wiring layer layout is given. Further, the capacitor electrode layer layout may be a polysilicon layer layout, a copper wiring layer layout or a tungsten wiring layer layout.

Further, by forming each of the plurality of capacitor electrode layer layouts in a comb shape and forming a comb-shaped electrode structure, it is possible to generate a capacitance component not only in the vertical direction of the wiring layout but also between adjacent wiring layouts. Become. Also,
If a capacitance cell layout is generated below the capacitance layout in the dummy region, not only the wiring capacitance but also the capacitance due to the gate oxide film capacitance (the capacitance between the gate electrode and the substrate) can be generated.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, components having substantially the same function are denoted by the same reference numeral for simplicity. (Embodiment 1) Embodiment 1 according to the present invention will be described with reference to FIGS. FIG. 1 is a flowchart for explaining a layout design method for a semiconductor integrated circuit according to the present embodiment. FIG. 2 schematically shows a part of a cross-sectional structure of a semiconductor integrated circuit layout generated by the layout design method of the present embodiment.

As shown in FIG. 1, in the layout design method of this embodiment, after the placement and wiring step S110, a step S120 of generating a dummy pattern is executed, and then a capacitance is formed from the generated dummy pattern. Step S130 of generating a capacitor electrode layer layout is performed. After that, as in the conventional LSI layout design method, a mask verification step S140 is performed, and then a mask processing step S150 is performed.
Execute Hereinafter, steps S110 to S130 will be described in detail.

First, the placement and routing step S110 is performed.
A functional block layout and a wiring layout are generated by the placement and wiring step S110. The wiring layout includes a metal layer layout and a polysilicon layer layout. The placement and routing step S110 can be performed using a known automatic placement and routing technique. For example, based on the logic circuit information to be designed and the like, after the designer specifies the arrangement position of the functional blocks (for example, ROM, RAM, etc.) and the paths of the power supply wiring and the ground wiring, the wiring (for example, wiring signal ) Can be executed using a computer in which a program for automatically determining the path is built.

Next, in a dummy pattern generation step S120, dummy patterns for adjusting the area ratio of the chip layout are laid in empty areas in the chip layout other than the areas where the functional block layout and the wiring layout are located. Spreading of dummy patterns can be performed by logical operation. For example, when generating a first aluminum wiring layer layout as a dummy pattern, LS
After extracting the area of the first aluminum layer layout from the entire area of I, the area is extended in accordance with a fixed rule for separation between wirings (separation), then the inverted area is calculated, and a dummy pattern is spread over the inverted area. Such a logical operation may be performed. In order to improve the manufacturing yield, it is preferable that dummy patterns having the same number of layers as the wiring layout are laid in the empty areas. The shape of the dummy pattern may be appropriately set according to design conditions. When the dummy patterns of the respective layers spread over the empty area have the same shape and an overlapping structure, a capacitance component can be generated.

Next, by executing a capacitor layout generating step S130, a capacitor layout including a plurality of capacitor electrode layer layouts having the same shape as the dummy pattern of each layer is generated in a dummy region where dummy patterns are spread. The generation of the capacitance layout is performed by connecting the dummy pattern of each layer generated in step S120 to either the power supply wiring layout or the ground wiring layout. For example, by alternately connecting each of the plurality of dummy patterns to the power supply wiring layout and the ground wiring layout, the capacitance electrode layer layout connected to the power supply wiring layout and the capacitance electrode layer layout connected to the ground wiring layout are changed. An alternately stacked capacitor layout can be generated.

In the case where four layers of dummy patterns are laid all over the empty area of the chip layout in step S120, when the capacitance layout generating step S130 is executed, as shown in FIG. 2, a layer having a power supply potential and a layer having a ground potential are Are generated in the dummy region 106 including the capacitor electrode layer layouts 23 to 26 alternately stacked.

Layout of capacitor electrode layer 2 located in first layer
3 and capacitor electrode layer layout 24 located in the second layer
Are connected to a power supply wiring layout 21 located on the first layer and a ground wiring layout 22 located on the second layer of the wiring layout generated in the placement and wiring step S110. The third capacitor electrode layer layout 25 is
The fourth capacitor electrode layer layout 26 is connected to the power supply wiring layout 21 via the connection cell 29, and is connected to the connection cell 2
8 to the ground wiring layout 22. The connection cells 29 connect the odd-numbered capacitor electrode layouts to each other, and the connection cells 28 connect the even-numbered capacitor electrode layouts to each other.

In this embodiment, the dummy area 106 is used.
A polysilicon layer layout 27 is formed under the first-layer capacitor electrode layer layout 23 in FIG. The polysilicon layer layout 27 is formed in a region under which an active region generation pattern which is a pattern for forming a transistor region does not exist. Polysilicon layer layout 27
Is connected to the ground wiring layout 22 via the connection cell 28.
And a capacitor electrode layer layout 26. The polysilicon layer layout 27 is formed to generate an inter-wiring capacitance. When the polysilicon layer layout 27 is formed, the polysilicon layer layout 27 and the first-layer capacitor electrode layer layout (for example, a first aluminum wiring layout) 23, a structure in which an inter-wiring capacitance is generated can be obtained. As a result, a larger capacitance can be obtained. In the present embodiment, the polysilicon layer layout 27 is formed at the time of the capacitance layout generation step S130, and the dummy area 106 on which the dummy patterns are spread is provided.
Inside, a polysilicon layer layout 27 is formed.

The capacitance electrode layer layouts 23 to 26 are generated as follows. First, a potential is specified for each layer of the four-layer dummy pattern generated in step S120. For example, the first layer of the dummy pattern is designated as a power supply potential, the second layer is designated as a ground potential, the third layer is designated as a power supply potential, and the fourth layer is designated as a ground potential.

Next, a first layer dummy pattern adjacent to the power supply wiring layout 21 generated in the step S110 and designated as a power supply potential is connected to the power supply wiring layout 21.
Thereby, the capacitor electrode layer layout 23 is generated from the first layer dummy pattern. That is, the capacitor electrode layer layout 23 is generated from the first layer dummy pattern located adjacent to the same layer as the power supply wiring layout 21. Similarly, the second adjacent to the ground wiring layout 22
By connecting the layer dummy pattern to the ground wiring layout 22, a capacitor electrode layer layout 24 is generated from the second layer dummy pattern.

Next, the third-layer and fourth-layer dummy patterns that are not connected to the power supply wiring layout 21 and the ground wiring layout 22 are connected to the power supply wiring layout 21 and the ground wiring layout 22, respectively. And the fourth layer dummy pattern to the capacitor electrode layer layout 25 and the capacitor electrode layer layout 2
6 is generated. Such a connection can be made using the connection cells 29 and the connection cells 28. For example, the third-layer dummy pattern specified as the power supply potential is connected to the power supply wiring layout 21 via the connection cell 29, and the fourth-layer dummy pattern specified as the ground potential is connected via the connection cell 28. What is necessary is just to connect to the ground wiring layout 22. In this way, the capacitor electrode layer layouts 23 to 26 for forming the wiring capacitance by the upper layer and the lower layer are generated in the dummy region 106.

When the polysilicon layer layout 27 is formed below the capacitor electrode layer layout 23, the polysilicon layer layout 27 and the ground wiring layout 22 are connected via the connection cells 28, thereby forming the polysilicon layer layout. 27 can be at ground potential. Thus, the polysilicon layer layout 2
7 and the capacitor electrode layer layout 23 make it possible to form an interwiring capacitance.

In the present embodiment, by forming the capacitance layout 20 in the dummy region 106 on which the dummy patterns are spread, it is possible to design the layout of the semiconductor integrated circuit in which the capacitance is formed in the dummy region 106. Therefore, the layout design of the semiconductor integrated circuit in which the peak power supply current is suppressed and the radiated noise is reduced,
This can be performed without increasing the chip area.

In this embodiment, the layout of the electrode layer for the power supply potential and the layout of the electrode layer for the ground potential are the first.
Although the layers are alternately stacked from the layer, the order may be reversed. Further, the number of layers of the capacitor electrode layer layout is not limited to four, and may be, for example, two, three, or five or more. (Embodiment 2) Embodiment 2 according to the present invention will be described with reference to FIGS.

FIG. 3 is a flow chart for explaining a layout design method for a semiconductor integrated circuit according to the present embodiment. FIG. 4 schematically shows a part of a cross-sectional structure of a semiconductor integrated circuit layout generated by the layout design method of the present embodiment. The layout design method of the present embodiment is different from the layout design method of the first embodiment in that a step of generating a capacitance cell layout is further performed. In the following, in order to simplify the description of the present embodiment, points different from the first embodiment will be mainly described, and description of the same points as the first embodiment will be simplified or omitted.

As shown in FIG. 3, in the layout design method according to the present embodiment, first, as in the first embodiment, after performing the placement and wiring step S210, the dummy pattern generation step S220 is performed, and then the capacitance is determined. Layout generation step S
Execute 230. Next, a capacity cell layout generating step S240 is performed. Thereafter, in the same manner as in the first embodiment, the mask verification step S240 and then the mask processing step S240
Execute 250. Hereinafter, step S240 will be described.

When a four-layer dummy pattern is generated in step S220, when steps S230 and S240 are performed, as shown in FIG. 4, layers having a power supply potential and layers having a ground potential are alternately stacked. A capacitor layout 20 including the capacitor electrode layer layouts 23 to 26 and a capacitor cell layout 30 arranged below the capacitor layout 20 in the dummy region 106 are generated. The capacitance cell layout 30 has a structure in which a gate oxide film layout 38 is formed below a gate electrode layout 37. The capacity cell layout 30 is the same as the power supply wiring layout 2
Power is supplied to the gate electrode layout 37 from the capacitance electrode layer layout 23 connected to the gate electrode 1, and ground is supplied to the substrate layout 39 from the capacitance electrode layer layout 24 connected to the ground wiring layout 22. . Therefore, the capacitance cell layout 30
A gate oxide film capacitance can be formed between the gate electrode layout 37 and the substrate layout 30.

The generation of the capacity cell layout 30 is performed in step S
At 240, the capacity cell layout 30 separately created in advance is replaced with the capacity layout 20 in the dummy area 106.
By laying at the bottom of the

In this embodiment, since the capacitance cell layout 30 is further generated below the capacitance layout 20 in the dummy region 106, a gate oxide film capacitance can be formed in the dummy region 106 in addition to the inter-wiring capacitance. . For this reason, a larger capacitance component can be generated in the same area.

In the present embodiment, the layout of the electrode layer for the power supply potential and the layout of the electrode layer for the ground potential are the first.
Although the layers are alternately stacked from the layer, the order may be reversed. Further, the number of layers of the capacitor electrode layer layout is not limited to four, and may be, for example, two, three, or five or more.

(Embodiment 3) Embodiment 3 according to the present invention will be described with reference to FIGS.

FIG. 5 is a flowchart for explaining the layout design method of the semiconductor integrated circuit according to the present embodiment. FIG. 6A schematically shows a part of a planar structure of a semiconductor integrated circuit layout generated by the layout design method of the present embodiment, and FIG.
(A) shows a cross-sectional structure along the line 6B-6B '. The layout design method of the present embodiment differs from the layout design method of the first embodiment in that each of the plurality of capacitor electrode layer layouts is comb-shaped to form a comb-shaped electrode structure. In the following, in order to simplify the description of the present embodiment, points different from the first embodiment will be mainly described, and description of the same points as the first embodiment will be simplified or omitted.

As shown in FIG. 5, in the layout design method according to the present embodiment, first, after the placement and wiring step S310 is performed, the comb-shaped dummy pattern generation step S320 is performed to perform the comb-shaped electrode structure (interdigitated structure). )
Is generated. Next, a capacitance layout generation step S330 is executed to generate a capacitance layout having a comb-shaped electrode structure from the comb-shaped dummy pattern generated in step S320. After that, the mask verification step S340 and then the mask processing step S350 are executed in the same manner as in the first embodiment. Hereinafter, step S320 and step S
330 will be described in detail.

After performing step S310, in step S320, a comb-shaped dummy pattern is spread over the empty area of the chip.
A comb-shaped dummy pattern having a comb-shaped electrode structure is generated. Next, by performing step S330, FIG.
As shown in FIG. 7, a capacitor layout 3 including comb-shaped capacitor electrode layer layouts 33 and 34 from a comb-shaped dummy pattern.
5 is generated. The capacitance power supply layer layout 33 is connected to the power supply wiring layout 31 via the connection cell 41, and the capacitance power supply layer layout 34 is connected to the ground wiring layout 32 via the connection cell. That is, a capacitor layout 35 having a comb-shaped electrode structure in which the power supply potential capacitor electrode layer layout 33 is on one side and the ground potential capacitor electrode layer layout 34 is on the other side is generated.

In the present embodiment, as shown in FIG. 6B, a capacitance layout 35 including the first-layer capacitance electrode layer layouts 33 and 34 is generated from the uppermost fourth layer.
Further, a polysilicon layer layout 36 having a comb-shaped electrode structure is formed below the capacitor layout 35.

The capacity layout 35 is generated by connecting the power supply wiring layout generated in step S310 to one side of the pair of comb-shaped dummy patterns, and connecting the ground wiring layout generated in step S310 to the other side of the comb-shaped dummy pattern. This is done by connecting. Specifically, power supply wiring layout 3 generated in the first layer in step S310
1 and one side of a pair of comb-shaped dummy patterns are connected to the ground wiring layout 32, respectively. This connection
A connection cell 41 connecting all the layers of the fourth to first layers of the capacitor electrode layer layout and the polysilicon layer layout
And 42. In this way, a capacitor electrode layer layout having a structure in which layers having the same potential are vertically stacked from the uppermost fourth layer capacitor electrode layer layouts 33 and 34 to the polysilicon layer layout 36 is generated. Note that the polysilicon layer layout 36 is generated for the purpose of forming a larger capacitance component.

In this embodiment, since a plurality of capacitance electrode layer layouts 33 and 34 each having a comb-shaped electrode structure are generated, a capacitance component can be formed between adjacent wiring layouts, and noise radiated from the semiconductor integrated circuit can be generated. Can be reduced. In addition, when the capacitor electrode layer layouts 33 and 34 are configured such that layers having the same potential are stacked in the vertical direction, generation of the capacitor electrode layer layout can be facilitated.

In this embodiment, a four-layer capacitor electrode layout is generated, but the layout is not limited to this. For example, one to three or five or more capacitor electrode layer layouts may be generated.

(Embodiment 4) Embodiment 4 according to the present invention will be described with reference to FIGS.

FIG. 7 is a flowchart for explaining the layout design method of the semiconductor integrated circuit according to the present embodiment. FIG. 8A schematically shows a part of a planar structure of a semiconductor integrated circuit layout generated by the layout design method of the present embodiment, and FIG.
(A) shows a cross-sectional structure along the line 8B-8B '. The layout design method of the present embodiment is different from the layout design method of the third embodiment in that a capacitance layout of a comb-shaped electrode structure in which an upper layer and a lower layer form a wiring capacitance is used. Hereinafter, in order to simplify the description of the present embodiment, points different from the third embodiment will be mainly described, and description of the same points as the third embodiment will be simplified or omitted.

As shown in FIG. 7, in the layout design method according to the present embodiment, first, after a placement and wiring step S410 is performed, a comb-shaped dummy pattern generation step S420 is performed to perform a comb-shaped electrode structure (interdigitated structure). )
Is generated. Next, a capacitance layout generation step S430 is executed to generate a capacitance layout of a comb-shaped electrode structure in which an upper layer and a lower layer form a wiring capacitance from the comb-shaped dummy pattern generated in step S420. Thereafter, in the same manner as in the third embodiment, a mask verification step S440 and then a mask processing step S440
Execute 450. Hereinafter, step S430 will be described in detail.

After the comb dummy pattern is generated in step S420, step S430 is executed to obtain
As shown in (a) and (b), the electrode layer layout 4
Capacitance layout 45 of comb electrode structure including 3 and 44
Generate The capacitance layout 45 has a configuration in which a wiring capacitance is formed by an upper layer and a lower layer of the electrode layer layout.

To generate the capacitance layout 45, one side of the pair of comb-shaped dummy patterns is connected to the power supply wiring layout generated in step S310 by the connection cell 46, and the other side is connected to the ground wiring layout generated in step S310. The connection is performed by the cell 47. Connection cell 46
Interconnects the odd layers and interconnect cells 47 interconnect the even layers and the polysilicon layer layout. In this way, a configuration in which layers having a power supply potential and layers having a ground potential are alternately arranged in the upper, lower, left, and right directions from the uppermost fourth capacitance electrode layer layouts 33 and 34 to the polysilicon layer layout. can get.

In this embodiment, a capacitor layout 45 having a comb-shaped electrode structure in which a capacitor is formed by an upper layer and a lower layer is generated. Therefore, it is possible to generate a capacitance component not only between the adjacent wiring layouts but also between the wiring layouts in the vertical direction, and as a result, it is possible to increase the effect of noise suppression.

In this embodiment, a layout of four capacitor electrode layers is generated, but the present invention is not limited to this. For example, a layout of two, three, or five or more capacitor electrode layers may be generated.

[0055]

According to the present invention, a layout of a semiconductor integrated circuit having a capacitance formed in a dummy region can be designed by generating a capacitance layout disposed in a dummy region in which dummy patterns are spread. it can.
Therefore, the layout design of the semiconductor integrated circuit in which the peak power supply current is suppressed and the radiated noise is reduced can be performed without increasing the chip area.

[Brief description of the drawings]

FIG. 1 is a flowchart for explaining a layout design method for a semiconductor integrated circuit according to a first embodiment;

FIG. 2 is a cross-sectional view schematically illustrating a part of the semiconductor integrated circuit layout generated by the semiconductor integrated circuit layout designing method according to the first embodiment.

FIG. 3 is a flowchart illustrating a layout design method for a semiconductor integrated circuit according to a second embodiment;

FIG. 4 is a sectional view schematically showing a part of a semiconductor integrated circuit layout generated by a semiconductor integrated circuit layout designing method according to a second embodiment;

FIG. 5 is a flowchart for explaining a layout design method for a semiconductor integrated circuit according to a third embodiment;

FIG. 6A is a plan view schematically showing a part of a conductor integrated circuit layout generated by a semiconductor integrated circuit layout designing method according to a third embodiment; FIG.
FIG. 6A is a cross-sectional view along the line 6B-6B ′ in FIG.

FIG. 7 is a flowchart for explaining a layout design method for a semiconductor integrated circuit according to a fourth embodiment;

FIG. 8A is a plan view schematically showing a part of a conductor integrated circuit layout generated by the semiconductor integrated circuit layout designing method according to the fourth embodiment; FIG.
FIG. 7A is a cross-sectional view along the line 8B-8B ′ in FIG.

FIG. 9 is a plan view of a mask pattern layout (chip layout) designed by a conventional semiconductor integrated circuit layout design method.

FIG. 10 is a flowchart illustrating a conventional layout design method for a semiconductor integrated circuit.

[Explanation of symbols]

 Reference Signs List 21 power supply wiring layout 22 ground wiring layout 23 to 26 capacitance electrode layer layout 27 polysilicon layer layout 28 even layer connection cell 29 odd number layer connection cell 30 capacitance cell layout 31 power supply wiring layout 32 ground wiring layout 33, 34 capacitance electrode layer layout 37 Gate electrode layout 38 Gate oxide film layout 41, 42 Connection cell 43, 44 Capacitance electrode layer layout of comb-shaped electrode structure 45 Odd number layer connection cell 46 Even number layer connection cell 101 Chip layout 102 Function block layout 103 Power supply wiring layout 104 Signal wiring layout 105 Dummy pattern 106 Dummy area

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuhiko Kajimoto 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Yasuhiro Tanaka 1006 Okadoma Kadoma, Kadoma City Osaka Pref. Matsushita Electric Industrial Co., Ltd. 72) Inventor Shinichi Hashimoto 1006 Kadoma, Kazuma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Takeo Suzuki 1006 Odoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Hiroko Fukasawa Osaka No. 1006, Kazuma, Kadoma, Matsushita Electric Industrial Co., Ltd. EE36 EE45 EE52 HH06

Claims (5)

[Claims] A step of generating a functional block layout of a semiconductor integrated circuit layout, and a wiring layout including a signal wiring layout, a power supply wiring layout, and a ground wiring layout for connecting the functional block layouts; Laying a dummy pattern for adjusting the area ratio of the semiconductor integrated circuit layout in a vacant region in the semiconductor integrated circuit layout other than the region where the wiring layout is located; and arranging the dummy pattern in the dummy region laid out. Generating a capacitance layout including a plurality of capacitance electrode layer layouts each connected to either the power supply wiring layout or the ground wiring layout. 2. The semiconductor integrated circuit layout design method according to claim 1, wherein each of said plurality of capacitor electrode layer layouts has the same shape as said dummy pattern. 3. The capacitor layout according to claim 1, wherein a capacitor electrode layout connected to the power supply wiring layout and a capacitor electrode layer layout connected to the ground wiring layout are alternately stacked. A layout design method for a semiconductor integrated circuit. 4. Each of the plurality of capacitor electrode layer layouts is formed in a comb shape, and is formed by the capacitor electrode layer layout connected to the power supply wiring layout and the capacitor electrode layer layout connected to the ground wiring layout. 4. The layout design method for a semiconductor integrated circuit according to claim 1, wherein a capacitor layout having a comb-shaped electrode structure is generated. 5. The method according to claim 1, further comprising a step of generating a capacitor cell layout disposed below the capacitor layout in the dummy region and connected to the capacitor layout. A layout design method for a semiconductor integrated circuit.