JP2006344165A - Layout design device, layout design method, layout design program and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the working efficiency of layout design by improving a crosstalk error by a little wiring correction amount. <P>SOLUTION: This layout design device 200 determines whether a detecting part 202 detects a pair of networks (error network pair) in which an error occurs according to a result of a crosstalk analysis. When the pair of error networks is detected, an acquiring part 203 acquires correction information. The error network pair designates a wiring segment on the basis of the correction information, and a correcting part 204 executes wiring correction processing. A determining part 205 determines whether a correction result violates a design rule. When it is determined that the correction result violates the design rule, wiring correction processing is executed again. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a layout design apparatus, a layout design method, a layout design program, and a recording medium for designing a layout of a design target circuit of an LSI or a system LSI.

  LSI design has traditionally been required to improve work efficiency by shortening the design period. In particular, high quality is maintained for LSIs that are required to be large-scale, high-function, high-speed and low power consumption. It is important to improve the efficiency of this design work.

  For this reason, in LSI chip layout design, crosstalk is calculated by calculating and analyzing the amount of crosstalk between adjacent nets after placement and routing, and inserting a buffer for nets with crosstalk errors. An error was corrected (prior art 1).

  Further, in the prior art 1, instead of correcting the crosstalk error by inserting the buffer, the crosstalk error is corrected by specifying only the net to be corrected and rewiring as in Patent Document 1 below. (Prior art 2).

  In addition, in order to prevent the occurrence of a net with a long wiring length that would cause a crosstalk error, the placement and routing is appropriately devised in advance by hand, and an excessive number of relay buffers are inserted during the logic design, which is affected by the crosstalk. The wiring length was difficult (Prior Art 3).

JP-A-5-243383

  However, in the prior art 1 described above, a crosstalk error is detected after automatic placement and routing, and a buffer is inserted to improve the crosstalk error at the corresponding location. Therefore, when there is no space for placing the buffer at the place where the buffer is inserted, it is necessary to redo the placement and routing from the beginning, resulting in an increase in TAT (Turn Around Time).

  Further, in the above-described prior art 2, since only the net to be corrected is specified for correction, the relationship between the aggressor and victim is not considered, and an excessive detour is formed, resulting in reduced wiring efficiency. There was a problem.

  Furthermore, in the above-described prior art 3, there is a problem that it is required to devise a placement and wiring design beforehand in advance so as not to cause a crosstalk error, which requires a great number of work steps. In addition, it is necessary to be aware of the floor plan in advance from the logical design stage, and there is a problem that the design constraint increases and the design congestion increases and the required man-hours increase. As described above, there is a problem that the layout design period increases due to an increase in TAT and an increase in work man-hours, and the work efficiency decreases.

  The present invention eliminates the problems caused by the prior art described above, and improves the layout design work efficiency by improving the crosstalk error with a small amount of wiring correction, thereby improving the layout design work efficiency, An object is to provide a layout design program and a recording medium.

  In order to solve the above-described problems and achieve the object, a layout design apparatus according to the present invention detects and detects a pair of nets in which an error has occurred as a result of crosstalk analysis from layout data of a circuit to be designed. The pair of nets is corrected so that the pair of nets are separated from each other, and it is determined whether or not the corrected result violates a design rule of the design target circuit.

  According to the present invention, the correction target can be relatively corrected with respect to a pair of nets that cause a crosstalk error, that is, an interval between an aggressor net and a victim net, and an excessive detour can be prevented from being formed. .

  In the above invention, information on adjacent parallel wiring length allowed for the pair of nets (hereinafter referred to as “allowable adjacent parallel wiring length”) is acquired based on the result of the crosstalk analysis, and the acquired allowable adjacent parallel length is acquired. The pair of nets may be modified based on the information on the wiring length so that the adjacent parallel wiring length of the pair of nets is equal to or less than the allowable adjacent parallel wiring length.

  According to the present invention, only the minimum necessary portions can be corrected.

  In the above invention, the first timing window information related to the clock signal of at least one of the pair of nets, and the clocks of other nets other than the pair of nets adjacent to the one net Second timing window information related to the signal may be acquired, and it may be determined whether or not the design rule of the circuit to be designed is violated based on the overlap of the first and second timing window information. .

  According to the present invention, even if the corrected net is adjacent to another net, the recorrection processing can be reduced.

  According to the layout design apparatus, layout design method, layout design program, and recording medium according to the present invention, it is possible to improve the work efficiency of layout design by improving the crosstalk error with a small amount of wiring correction. There is an effect.

  Exemplary embodiments of a layout design apparatus, a layout design method, a layout design program, and a recording medium according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Hardware configuration of layout design device)
First, the hardware configuration of the layout design apparatus according to the embodiment of the present invention will be described. FIG. 1 is a block diagram showing a hardware configuration of a layout design apparatus according to an embodiment of the present invention.

  In FIG. 1, the layout design apparatus is an example of a CPU 101, ROM 102, RAM 103, HDD (hard disk drive) 104, HD (hard disk) 105, FDD (flexible disk drive) 106, and a removable recording medium. FD (flexible disk) 107, display 108, I / F (interface) 109, keyboard 110, mouse 111, scanner 112, and printer 113. Each component is connected by a bus 100.

  Here, the CPU 101 controls the entire layout design apparatus. The ROM 102 stores a program such as a boot program. The RAM 103 is used as a work area for the CPU 101. The HDD 104 controls reading / writing of data with respect to the HD 105 according to the control of the CPU 101. The HD 105 stores data written under the control of the HDD 104.

  The FDD 106 controls reading / writing of data with respect to the FD 107 according to the control of the CPU 101. The FD 107 stores data written under the control of the FDD 106, or causes the layout design apparatus to read data stored in the FD 107.

  In addition to the FD 107, the removable recording medium may be a CD-ROM (CD-R, CD-RW), MO, DVD (Digital Versatile Disk), memory card, or the like. The display 108 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. As this display 108, for example, a CRT, a TFT liquid crystal display, a plasma display, or the like can be adopted.

  The I / F 109 is connected to a network 114 such as the Internet through a communication line, and is connected to other devices via the network 114. The I / F 109 controls an internal interface with the network 114 and controls data input / output from an external device. For example, a modem or a LAN adapter may be employed as the I / F 109.

  The keyboard 110 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Moreover, a touch panel type input pad or a numeric keypad may be used. The mouse 111 performs cursor movement, range selection, window movement, size change, and the like. A trackball or a joystick may be used as long as they have the same function as a pointing device.

  The scanner 112 optically reads an image and takes in the image data into the layout design apparatus. The scanner 112 may have an OCR function. The printer 113 prints image data and document data. For example, a laser printer or an ink jet printer can be employed as the printer 113.

(Functional configuration of layout design device)
Next, a functional configuration of the layout design apparatus according to the embodiment of the present invention will be described. FIG. 2 is a block diagram showing a functional configuration of the layout design apparatus according to the embodiment of the present invention. In FIG. 2, the layout design device 200 is a computer device that corrects layout data 201, and includes a detection unit 202, an acquisition unit 203, a correction unit 204, and a determination unit 205.

  The layout data 201 is electronic data obtained by laying out a net of a design target circuit. FIG. 3 is an explanatory diagram showing a part of the layout data 201. In FIG. 3, nets 301 to 303 are laid out in a partial region 300 of the layout data 201.

  In FIG. 2, the detection unit 202 detects a pair of nets in which an error has occurred as a result of crosstalk analysis from the layout data 201 of the circuit to be designed. In FIG. 3, for example, if the net 301 and the net 302 are an error net pair, the net 301 and the net 302 are detected. In FIG. 3, for convenience, the net 301 is an aggressor net that causes crosstalk, and the net 302 is a victim net that is affected by the aggressor net (net 301).

  In FIG. 2, the acquisition unit 203 acquires correction information for a pair of nets. For example, information on the adjacent parallel wiring length allowed for a pair of nets (hereinafter referred to as “allowable adjacent parallel wiring length”) is acquired based on the result of the crosstalk analysis. Here, the adjacent parallel wiring length is the parallel wiring length that is the most adjacent in a pair of nets. For example, taking the aggressor net 301 and victim net 302 as a pair of nets shown in FIG. 3 as an example, the adjacent parallel wiring length is L.

  The information related to the allowable adjacent parallel wiring length is information defining the allowable adjacent parallel wiring length itself or a ratio (for example, 50% reduction) of reducing the adjacent parallel wiring length currently wired. Using the above-described example, the net 301 or the net 302 is corrected so that the adjacent parallel wiring length L is reduced by 50%.

  In addition, the acquisition unit 203 sets, as correction information, first timing window information related to the clock signal of at least one of the pair of nets, and other nets other than the pair of nets adjacent to the one net. And second timing window information relating to the clock signal. The timing window information is information describing changes in pulses (rise and fall) within the clock cycle of the clock signal of each net as a window having the maximum and minimum widths.

  The correcting unit 204 corrects the pair of nets so that the pair of nets are separated from each other. That is, the correction is made so that the interval between the pair of nets is widened. Specifically, for example, correction is performed by pulling away the victim net without moving the aggressor net. In addition, it is corrected by pulling away the aggressor net without moving the victim net. Also, move the aggressor net and victim net together to correct the gap between the two nets. Moreover, the distance to separate is set to 1 grid, for example.

  FIG. 4 is an explanatory diagram showing a modification example (1) by the modification unit 204. In FIG. 4, the victim net 302 is corrected without moving the aggressor net 301. Reference numeral 400 denotes a detour route generated by the modification of the victim net 302. A portion indicated by a dotted line in the detour route 400 is a portion routed to another layer. As described above, when the victim net 301 is corrected, the crosstalk error can be efficiently improved by providing an interval from the receiver side of the victim net 301.

  FIG. 5 is an explanatory diagram illustrating a modification example (2) by the modification unit 204. In FIG. 5, correction is performed by pulling away the aggressor net 301 without moving the victim net 302. Reference numeral 500 denotes a detour route generated by correcting the aggressor net 301.

  Further, when the acquisition unit 203 acquires information related to the adjacent parallel wiring length, the correction unit 204 corrects the pair of nets so that the adjacent parallel wiring length of the pair of nets is equal to or less than the allowable adjacent parallel wiring length. . Specifically, when the ratio for reducing the adjacent parallel wiring length is specified by the information, the adjacent parallel wiring length is corrected to be equal to or shorter than the allowable adjacent parallel wiring length according to the ratio.

  FIG. 6 is an explanatory diagram illustrating a modification example (3) by the modification unit 204. FIG. 6 shows an example of correcting a victim net. FIG. 6 shows a partial area 600 of the layout data 201. In FIG. 6A, a net 601 is a victim net, a net 602 is an aggressor net, and a net 603 is another net. When the adjacent parallel wiring length of the net 601 and the net 602 is L, when the rate of reducing the adjacent parallel wiring length is designated as 50%, for example, the wiring segment 610 corresponding to half L (1 / 2L) is designated as an aggressor. Correction is made by pulling away from the net 602.

  At this time, as shown in FIG. 6B, a prohibited area 611 is set in the vicinity of the wiring segment 610. The width W1 of the prohibited area 611 is set in a range that does not cause crosstalk with other nets 603. Then, as shown in FIG. 6C, the wiring segment 610 is drawn again so that the aggressor net 602 and the other net 603 do not overlap the prohibited area 611.

  FIG. 7 is an explanatory diagram illustrating a modification example (4) by the modification unit 204. FIG. 7 shows an example of correcting the aggressor net. In FIG. 7A, when the adjacent parallel wiring length of the net 601 and the net 602 is L, when the rate of reducing the adjacent parallel wiring length is designated as 50%, for example, it corresponds to half of L (1 / 2L). The wiring segment 620 is corrected by pulling it away from the victim net 601.

  At this time, as shown in FIG. 7B, a prohibited area 621 is set in the vicinity of the wiring segment 620. The width W2 of the prohibited area 621 is set within a range that does not cause crosstalk with other nets 603. Then, as shown in FIG. 7C, the wiring segment 610 of the victim net 601 is modified so that the victim net 601 and the other net 603 do not overlap the prohibited area 621.

  In FIG. 2, the determination unit 205 determines whether the correction result corrected by the correction unit 204 violates the design rule of the circuit to be designed. Specifically, it is determined whether or not the correction results shown in FIGS. 3 to 7 violate the design rule of the circuit to be designed. For example, the case where the nets intersect, the case where the nets are adjacent to each other at a predetermined interval, the wiring where the crosstalk error occurs, the case where the delay occurs or the like corresponds to the design rule violation.

  Further, as shown in FIG. 7C, even when the corrected wiring segment 610 and the other net 603 are close to each other and are wired within a predetermined interval permitted by the design rule, Even in the same clock domain, if the timing window information of victim net 601 and the timing window information of other net 603 do not overlap, it does not violate the design rule. In general, in the case of different clock domains, the timing of the clock signal change is handled in the worst state, so that the timing window information is handled as overlapping.

  FIG. 8 is a waveform diagram showing timing window information of victim net 601 and other net 603 shown in FIG. In FIG. 8, waveform (a) is timing window information of victim net 601 for one clock cycle, and waveform (b) is timing window information of other net 603 for one clock cycle.

  In the waveform (a), the pulse 811 has a width in which the rise time (rise) of the signal flowing to the victim net 601 changes upon receiving the clock signal (the shortest and longest time from the change of the clock signal to the change of the signal). The pulse 812 indicates the width in which the fall time (fall) of the signal flowing through the victim net 601 changes. Similarly, in the waveform (b), the pulse 821 indicates a width in which the rise time (rise) of the signal flowing in the other net 603 changes, and the pulse 822 indicates the fall time ( fall) indicates the width of change.

  Comparing the waveform (a) and the waveform (b), the pulse 811 and the pulse 821 indicating the width in which the rise time (rise) changes overlap, and the width in which the fall time (fall) changes is shown. The shown pulse 812 and pulse 822 overlap. Therefore, in this case, a crosstalk error may occur between the wiring segment 610 of the modified victim net 601 shown in FIG. 7C and the other net 603. Therefore, the design rule can be violated. On the other hand, when there is no overlapping of timing window information as shown in FIG. 8, no crosstalk error is induced, so that the design rule is not violated.

(Layout design process)
Next, a layout design processing procedure of the layout design apparatus 200 according to the embodiment of the present invention will be described. FIG. 9 is a flowchart showing a layout design processing procedure of the layout design apparatus 200 according to the embodiment of the present invention. In FIG. 9, the detection unit 202 determines whether or not a pair of nets (error net pair) in which an error has occurred is detected as a result of the crosstalk analysis (step S <b> 901). If an error net pair is not detected (step S901: No), a series of processing is terminated.

  On the other hand, when an error net pair is detected (step S901: Yes), the acquisition unit 203 acquires correction information (step S902). Then, a wiring segment is designated from the error net pair based on the correction information (step S903), and the correction unit 204 executes a wiring correction process (step S904). Then, the determination unit 205 determines whether the correction result violates the design rule (step S905).

  If it is determined that the design rule is violated (step S905: YES), the process returns to step S904, and the wiring correction process is executed again (step S904). On the other hand, if the design rule is not violated (step S905: No), the crosstalk error has been eliminated, and it is determined whether there is an unprocessed error net pair (step S906). When there is an unprocessed error net pair (step S906: Yes), the process returns to step S902. On the other hand, if there is no unprocessed error net pair (step S906: No), the series of processes is terminated.

  Thus, in the present embodiment, it is not necessary to insert a buffer even when a crosstalk error occurs. Further, by detecting an error net pair including an aggressor net and a victim net, it is possible to prevent excessive detouring of the correction target net. In addition, by setting the allowable adjacent parallel wiring length, it is possible to designate a wiring segment necessary for correction, and it is possible to correct with a small amount of wiring correction. Furthermore, by comparing the corrected timing window information with other nets, even corrections close to other nets can be permitted, and wiring efficiency can be improved.

  As described above, according to the layout design apparatus, layout design method, layout design program, and recording medium, it is possible to improve the work efficiency of layout design by improving the crosstalk error with a small amount of wiring correction. it can.

  The layout design method described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. Further, this program may be a transmission medium that can be distributed via a network such as the Internet.

(Supplementary Note 1) Detection means for detecting a pair of nets in which an error has occurred as a result of crosstalk analysis from layout data of a circuit to be designed;
Correcting means for correcting the pair of nets so that the pair of nets detected by the detecting means are separated from each other;
A determination unit that determines whether the correction result corrected by the correction unit violates a design rule of the circuit to be designed;
A layout design apparatus comprising:

(Additional remark 2) The acquisition means which acquires the information regarding the adjacent parallel wiring length (henceforth "allowable adjacent parallel wiring length") accept | permitted by the said one pair of net | network by the result of the said crosstalk analysis,
The correcting means is
Correcting the pair of nets so that the adjacent parallel wiring length of the pair of nets is equal to or less than the allowable adjacent parallel wiring length based on the information on the allowable adjacent parallel wiring length acquired by the acquisition unit; The layout design apparatus according to appendix 1, characterized by:

(Appendix 3) The acquisition means includes:
First timing window information regarding a clock signal of at least one of the pair of nets, and second timing regarding a clock signal of another net other than the pair of nets adjacent to the one net. Window information and
The determination means includes
The layout design apparatus according to appendix 1 or 2, wherein it is determined whether or not a design rule of the circuit to be designed is violated based on an overlap of the first and second timing window information.

(Supplementary Note 4) A detection step of detecting a pair of nets in which an error has occurred as a result of crosstalk analysis from layout data of a design target circuit;
A correction step of correcting the pair of nets so that the pair of nets detected by the detection step are separated;
A determination step for determining whether the correction result corrected by the correction step violates a design rule of the circuit to be designed;
A layout design method characterized by including:

(Additional remark 5) The acquisition process which acquires the information regarding the adjacent parallel wiring length (henceforth "allowable adjacent parallel wiring length") accept | permitted by the said pair of net | network by the result of the said crosstalk analysis,
The correction step includes
Correcting the pair of nets so that the adjacent parallel wiring length of the pair of nets is equal to or less than the allowable adjacent parallel wiring length based on information on the allowable adjacent parallel wiring length acquired by the acquiring step; The layout design method according to appendix 4, characterized by:

(Appendix 6)
First timing window information regarding a clock signal of at least one of the pair of nets, and second timing regarding a clock signal of another net other than the pair of nets adjacent to the one net. Window information and
The determination step includes
6. The layout design method according to appendix 4 or 5, wherein it is determined whether or not a design rule of the circuit to be designed is violated based on an overlap of the first and second timing window information.

(Supplementary Note 7) A detection step of detecting a pair of nets in which an error has occurred as a result of crosstalk analysis from layout data of a circuit to be designed;
A correction step of correcting the pair of nets so that the pair of nets detected by the detection step are separated;
A determination step for determining whether the correction result corrected by the correction step violates a design rule of the design target circuit; and
A layout design program for causing a computer to execute.

(Additional remark 8) The acquisition process which acquires the information regarding the adjacent parallel wiring length (henceforth "allowable adjacent parallel wiring length") accept | permitted by the said pair of net | network by the result of the said crosstalk analysis,
The correction step includes
Correcting the pair of nets so that the adjacent parallel wiring length of the pair of nets is equal to or less than the allowable adjacent parallel wiring length based on the information on the allowable adjacent parallel wiring length acquired by the acquiring step; The layout design program according to appendix 7, characterized by:

(Supplementary note 9)
First timing window information regarding a clock signal of at least one of the pair of nets, and second timing regarding a clock signal of another net other than the pair of nets adjacent to the one net. Window information and
The determination step includes
9. The layout design program according to appendix 7 or 8, wherein it is determined whether or not a design rule of the circuit to be designed is violated based on an overlap of the first and second timing window information.

(Supplementary note 10) A computer-readable recording medium in which the layout design program according to any one of supplementary notes 7 to 9 is recorded.

  As described above, the layout design apparatus, layout design method, layout design program, and recording medium according to the present invention are useful for design target circuits such as LSI and system LSI.

It is a block diagram which shows the hardware constitutions of the layout design apparatus concerning embodiment of this invention. It is a block diagram which shows the functional structure of the layout design apparatus concerning embodiment of this invention. It is explanatory drawing which shows a part of layout data. It is explanatory drawing which shows the example (1) of correction by a correction part. It is explanatory drawing which shows the example of correction (2) by a correction part. It is explanatory drawing which shows the example of correction (3) by a correction part. It is explanatory drawing which shows the example of correction (4) by a correction part. It is a wave form diagram which shows the timing window information of the victim net shown in FIG.7 (c), and another net. It is a flowchart which shows the layout design processing procedure of the layout design apparatus concerning embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 200 Layout design apparatus 201 Layout data 202 Detection part 203 Acquisition part 204 Correction part 205 Determination part

Claims (5)

Detecting means for detecting a pair of nets in which an error has occurred as a result of crosstalk analysis from layout data of a design target circuit;
Correcting means for correcting the pair of nets so that the pair of nets detected by the detecting means are separated from each other;
A determination unit that determines whether the correction result corrected by the correction unit violates a design rule of the circuit to be designed;
A layout design apparatus comprising: An acquisition means for acquiring information on adjacent parallel wiring length allowed for the pair of nets (hereinafter referred to as “allowable adjacent parallel wiring length”) according to the result of the crosstalk analysis;
The correcting means is
Correcting the pair of nets so that the adjacent parallel wiring length of the pair of nets is equal to or less than the allowable adjacent parallel wiring length based on the information on the allowable adjacent parallel wiring length acquired by the acquisition unit; The layout design apparatus according to claim 1. A detection step of detecting a pair of nets in which an error has occurred as a result of crosstalk analysis from the layout data of the design target circuit;
A correction step of correcting the pair of nets so that the pair of nets detected by the detection step are separated;
A determination step for determining whether the correction result corrected by the correction step violates a design rule of the circuit to be designed;
A layout design method characterized by including: A detection step for detecting a pair of nets in which an error has occurred as a result of crosstalk analysis from the layout data of the design target circuit;
A correction step of correcting the pair of nets so that the pair of nets detected by the detection step are separated;
A determination step for determining whether the correction result corrected by the correction step violates a design rule of the design target circuit; and
A layout design program for causing a computer to execute. A computer-readable recording medium on which the layout design program according to claim 4 is recorded.

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