JP5167740B2 - Design support program, design support apparatus, and design support method - Google Patents

Description

  The present invention relates to a design support program that supports LSI design in consideration of semiconductor process variations, a computer-readable recording medium that records the program, a design support apparatus, and a design support method.

  In recent years, with the miniaturization and high integration of LSI, the influence of process variation, power supply voltage drop, crosstalk, etc. has increased, and the fluctuation of circuit delay has increased. In particular, with the miniaturization of technology, the proportion of wiring delay occupying the delay of the entire circuit is increasing, and timing verification considering the variation in the wiring process has become important.

  Conventionally, methods for realizing timing verification in consideration of process variations have been disclosed (for example, see Patent Documents 1 to 4 below). Specifically, for example, by calculating the delay time by calculating the wiring capacity coefficient and the wiring resistance coefficient for each of the worst condition and the best condition as a coefficient depending on two elements of the wiring length and the wiring interval, the process variation is calculated. A method of performing timing verification in consideration of the variation amount of the factor is disclosed.

Japanese Patent Laid-Open No. 10-207937 JP 2006-338253 A JP 2004-362202 A JP 7-182380 A

  However, in the above-described conventional technique, timing verification considering an increase in wiring resistance due to miniaturization has not been performed. For this reason, the influence of the dispersion of the wiring resistance in the process after 65 nm becomes remarkable, and a hold error that conflicts with the setup error at the RC worst corner where the time constant is maximum occurs frequently. As a result, circuit design rework work such as layout optimization after layout and wiring route optimization frequently occurs, leading to a problem that the verification period is prolonged and the design period is prolonged.

  This program, a recording medium, an apparatus, and a method for recording the program are efficient by reducing a wiring resistance variation effect by increasing a wiring width that causes a hold error that conflicts with a setup error. The purpose is to realize accurate and highly accurate timing verification, reduce the burden on the designer, and shorten the design period.

  In order to solve the above-described problems and achieve the object, a program, a recording medium, an apparatus, and a method recording the program are analyzed using a corner condition that maximizes a time constant of a circuit to be designed. Based on the timing analysis result, a clock net in which a hold error has occurred is detected from the clock tree related to the circuit to be designed, and the wiring width of the wiring in the clock net is determined as the wiring. The requirement is to change the wiring width to be wider than the wiring width of other different wiring.

  According to this, the influence of variations in the wiring resistance can be reduced by reducing the absolute value of the wiring delay by increasing the wiring width of the wiring in the clock net that causes the hold error.

  In the program, the recording medium, the apparatus, and the method in which the program is recorded, a clock net in which a hold error that conflicts with a setup error occurs in the clock tree may be detected.

  According to this, it is possible to increase the wiring width of the wiring in the clock net that causes a hold error that conflicts with the setup error.

  Further, in the program, the recording medium, the apparatus, and the method in which the program is recorded, among the clock nets in which the hold error and the setup error compete, the number of leaves of the clock net, the clock frequency, and the number of gate stages It is also possible to detect a clock net in which at least one of them is maximized.

  According to this, among the clock nets that cause a hold error that conflicts with the setup error, the wiring width in the clock net in which at least one of the number of leaves, the clock frequency, and the number of gate stages is the maximum is wide. Can be.

  In the program, the recording medium, the apparatus, and the method recording the program, the wiring from the circuit element serving as a clock branch point to the terminal circuit element among the wirings in the clock net is connected to the other wiring. The wiring width may be determined to be thicker than the wiring width of the other wiring, and the wiring width of the wiring may be changed to a wiring width wider than the wiring width of the other wiring.

  According to this, only the remaining wirings of the wirings in the clock net excluding the part where the wiring delay variation is common in a plurality of clock paths can be made thick.

  Further, in the program, the recording medium, the apparatus, and the method in which the program is recorded, the wiring from the circuit element that is a clock branch point to the circuit element that is one stage before the end of the wiring in the clock net. The wiring may be determined to be thicker than the wiring width of the other wiring.

  According to this, it is possible to increase the wiring width of the wiring to the circuit element one stage before the terminal, assuming wiring congestion at the terminal circuit element.

  Further, in the program, the recording medium, the apparatus, and the method in which the program is recorded, according to the design rule, the minimum distance between the wiring to be changed and the wiring adjacent to the wiring is the track spacing of the wiring track. It is good also as changing to.

  According to this, crosstalk with adjacent wiring can be prevented by performing thick wiring in a double space.

  This design data also compensates for the timing of the clock that traces some wiring by making the wiring width of some wiring wider than the wiring width of other wiring that is different from that part of the wiring. It is necessary to relate to the designed circuit to be designed.

  In addition, this semiconductor integrated circuit has a wiring width of a part of the wiring that is wider than a wiring width of another wiring different from the part of the wiring, so that the timing of the clock that follows the part of the wiring can be reduced. It must be compensated.

  According to these, a high-quality semiconductor integrated circuit can be provided to the market at an early stage.

  According to this program, a recording medium, an apparatus, and a method on which the program is recorded, by reducing the influence of variations in wiring resistance by increasing the wiring width that causes a hold error that conflicts with a setup error. Thus, it is possible to achieve efficient and highly accurate timing verification, reduce the burden on the designer, and shorten the design period.

  Exemplary embodiments of a design support program, a computer-readable recording medium storing the program, a verification support apparatus, and a verification support method according to the present invention will be described below in detail with reference to the accompanying drawings.

(Hardware configuration of design support device)
First, the hardware configuration of the design support apparatus will be described. FIG. 1 is a block diagram showing a hardware configuration of the design support apparatus according to the present embodiment.

  In FIG. 1, a design support apparatus 100 is an example of a CPU 101, a ROM 102, a RAM 103, an HDD (hard disk drive) 104, an HD (hard disk) 105, an FDD (flexible disk drive) 106, and a removable recording medium. FD (flexible disk) 107, display 108, I / F (interface) 109, keyboard 110, mouse 111, scanner 112, and printer 113. Each component is connected by a bus 120.

  Here, the CPU 101 governs overall control of the design support apparatus 100. The ROM 102 records a program such as a boot program. The RAM 103 is used as a work area for the CPU 101. The HDD 104 controls reading / writing of data with respect to the HD 105 according to the control of the CPU 101. The HD 105 stores data written under the control of the HDD 104.

  The FDD 106 controls reading / writing of data with respect to the FD 107 according to the control of the CPU 101. The FD 107 stores data written under the control of the FDD 106 or causes the design support apparatus 100 to read data stored in the FD 107.

  In addition to the FD 107, the removable recording medium may be a CD-ROM (CD-R, CD-RW), MO, DVD (Digital Versatile Disk), memory card, or the like. The display 108 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. As the display 108, for example, a CRT, a TFT liquid crystal display, a plasma display, or the like can be adopted.

  The I / F 109 is connected to a network 114 such as the Internet through a communication line, and is connected to other devices via the network 114. The I / F 109 controls an internal interface with the network 114 and controls data input / output from an external device. For example, a modem or a LAN adapter may be employed as the I / F 109.

  The keyboard 110 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Moreover, a touch panel type input pad or a numeric keypad may be used. The mouse 111 performs cursor movement, range selection, window movement, size change, and the like. A trackball or a joystick may be used as long as they have the same function as a pointing device.

  The scanner 112 optically reads an image and reads image data into the apparatus. The scanner 112 may have an OCR function. The printer 113 prints image data and document data. As the printer 113, for example, a laser printer or an ink jet printer can be employed.

(Outline of this embodiment)
Next, an outline of the present embodiment will be described. FIG. 2 is an explanatory diagram showing an outline of the present embodiment. In FIG. 2, the design target circuit 200 includes a clock source CS and a plurality of circuit elements (for example, a clock buffer, flip-flops FF1, FF2, etc.). In the drawing, a part of the circuit to be designed is extracted and shown.

  Further, the clock signal line from the clock source CS to the flip-flop FF1 is a clock path P1 (thick line in FIG. 2), the clock signal line from the clock source CS to the flip-flop FF2 is a clock path P2 (thick line in FIG. 2), A data signal line from the flip-flop FF1 to the flip-flop FF2 is defined as a data path P3 (a dotted arrow in FIG. 2).

  Here, focusing on the C worst corner where the wiring capacitance (C) is maximized as the wiring corner condition, the skew is adjusted so that the clock from the clock source CS reaches the flip-flop FF1 and the flip-flop FF2 at the same time. ing. Here, the wiring corner will be described.

  FIG. 3 is an explanatory diagram showing a wiring corner. As shown in FIG. 3, in a process with a wiring width of 90 nm or less, paying attention to the C worst corner, the setup error is adjusted by logic optimization, layout optimization, and wiring path optimization. This is because the proportion of the delay time of the wiring occupying the delay time of the entire circuit is small, so that the timing can be adjusted sufficiently only by considering the C worst corner.

  On the other hand, in the process where the wiring width is 65 nm or more, the wiring resistance (R) increases and the wiring delay increases. Therefore, the influence of the wiring resistance (R) component on the wiring delay at the RC worst corner (time constant worst) is affected. If the timing verification is performed at the Rworst corner after adjusting the setup error focusing on the conventional Cworst corner, the circuit configuration is likely to generate a hold error that conflicts with the setup error. In FIG. 2, the wiring delay (R) is increased, and the wiring delay value at the RC worst corner is doubled as compared to the Cworst corner (210 and 220 in FIG. 2).

  Specifically, for example, when the OCV (On Chip Variation) is “Min = 0.95, Max = 1”, the Min wiring delay of the wiring stage number 5 from the branch point (clock buffer 230) of the clock paths P1, P2 is increased. In the case of 475 [ps] and Max wiring delay of 500 [ps], when the absolute value of the wiring resistance is doubled, the skew difference is 25 [ps] to 50 [ps]. As a result, a hold error that conflicts with the setup error has occurred in the data path P3.

  For this reason, in the present embodiment, RC extraction, delay calculation, and STA (static delay analysis) are performed in consideration of the RC worst corner, and the wiring at the location where the hold error and the setup error conflict with each other is thicker than the normal wiring width. By making the width, the influence of wiring delay is reduced. In consideration of the fact that the wiring resistance (R) increases as the temperature rises, the verification corner is set at RC worst and at a high temperature.

  The wiring structure under each corner condition is defined below. FIG. 4A is an explanatory diagram of the structure definition of the wiring. FIG. 4B is an explanatory diagram of a wiring cross-sectional structure image. In FIG. 4A, the wiring structure table 410 defines the wiring structure (width, thickness, height, via resistance) under each corner condition. However, “+” represents that it is larger than the standard wiring structure, and “−” represents that it is smaller than the standard wiring structure.

  FIG. 4B shows an image of a wiring cross-sectional structure, where 420 is an interlayer insulating film and 430 is a wiring metal. Here, taking RC worst as an example, the width, thickness, and height of the wiring structure under the RC worst corner condition are all smaller than the standard value, and the via resistance is larger than the standard value.

(Functional configuration of design support device)
Next, a functional configuration of the design support apparatus 100 according to the present embodiment will be described. FIG. 5 is a block diagram showing a functional configuration of the design support apparatus according to the present embodiment. In FIG. 5, the design support apparatus 100 includes an acquisition unit 501, a detection unit 502, a change unit 503, and a determination unit 504.

  Each of these functions 501 to 504 can realize the function by causing the CPU to execute a program related to the function stored in the memory. Output data from each function 501 to 504 is held in a memory. Further, the functional configuration of the connection destination indicated by the arrow in FIG. 5 reads output data from the connection source function from the memory, and causes the CPU to execute a program related to the function.

  First, the acquisition unit 501 has a function of acquiring a timing analysis result analyzed using a corner condition that maximizes the time constant of the circuit to be designed. The circuit to be designed handled here is, for example, an electronic circuit manufactured by a process with a wiring width of 65 nm or later. The time constant is an index indicating the response speed of the circuit to be designed, and is represented by a multiplication value “RC” of the wiring capacitance (C) and the wiring resistance (R) of the wiring.

  That is, the timing analysis result is a timing verification analysis result in consideration of the RC worst corner (see FIG. 3) in which the multiplication value of the wiring capacitance (C) and the wiring resistance (R) is maximized. The timing verification is a process of estimating the circuit delay of the circuit to be designed, performing optimization, and confirming that the delay is within a range necessary for normal operation of the circuit to be designed.

  Here, timing verification is performed by executing a simple STA (Static Timing Analysis) on a temporarily routed clock tree without considering DRC (Design Rule Check), and the timing analysis result is obtained. .

  Based on the timing analysis result acquired by the acquisition unit 501, the detection unit 502 detects a clock net in which a hold error has occurred in the clock tree related to the design target circuit. A clock tree is an electronic circuit that uses a clock source that generates a clock as a root and propagates the clock to a terminal circuit element group (for example, a flip-flop).

  This clock tree is derived from, for example, a timing constraint between FFs assuming that all flip-flops (FF) in the same clock net receive clocks at the same time, and after performing timing optimization arrangement, skew (FF It is constructed to minimize the clock arrival time difference between them. A clock net is a set of circuit elements that receive clocks from a clock source at the same time.

  Specifically, for example, a clock tree can be generated based on a net list relating to a circuit to be designed, a clock source, and circuit element arrangement / wiring information. A clock control circuit, a clock gate, or the like may be connected in the middle of the clock path from the clock source to the circuit element group. The clock control circuit controls the clock gate according to the clock from the clock source.

  The clock tree, netlist, and placement / wiring information described above may be acquired from an external device (not shown), or may be acquired by user operation input or extraction from a database or library (not shown).

  Here, two types of timing constraints that must be satisfied in order for the circuit to be designed to operate at the target frequency will be described. Normally, the timing at which the signal from the sending side (clock source, FF) reaches the receiving side FF must be after the current clock and before the next clock. The hold constraint ensures that the signal arrives after the current clock, and the setup constraint ensures that the signal arrives before the next clock.

  More specifically, the time during which data should not change before the clock edge is called the setup time, and the time when data should not change after the clock edge is called the hold time. If these timing constraints are not satisfied, it is not known whether the clock reads the value before the data changes or the value after the changes, and a hold error or a setup error occurs.

  That is, the detection unit 502 detects a clock net in which a hold error occurs because the arrival of a signal arrives before the current clock in violation of the hold constraint. In the example of FIG. 2 described above, a hold error has occurred in the data path P3, and the clock net from the clock source CS to the terminal FF1 and FF2 is detected.

  In addition, the detection unit 502 may detect a clock net in which a hold error that conflicts with a setup error occurs in the clock tree. Specifically, since there is no allowance in the setup time, when a correction for eliminating the hold error is performed, a clock net that causes a setup error due to the correction is detected.

  In other words, when a modification such as inserting a clock buffer on a data path in which a hold error has occurred (for example, the data path P3 shown in FIG. 2), the setup time is not sufficient, so the modification is accompanied. Detects clock nets where setup errors occur due to gate delay.

  In addition, the detection unit 502 may detect a clock net in which at least one of the number of leaves, the clock frequency, and the number of gate stages of the clock net is a maximum among clock nets in which a hold error and a setup error compete. . The leaf number is the total number of flip-flops of the clock net. The clock frequency is the operating frequency of the clock net. The number of gate stages is the total number of logic gates in the clock net.

  For example, when there are a plurality of clock nets in which a hold error and a setup error conflict, and the clock net having the largest number of leaves is detected, the detection unit 502 selects the clock net having the largest number of flip-flops from the plurality of clock nets. Will be detected.

  The changing unit 503 changes the wiring width of the wiring in the clock net detected by the detection unit 502 to a wiring width wider than the wiring width of another wiring different from the wiring. Specifically, the wiring width is changed to be thicker than the wiring width of the wiring normally used for the temporary wiring or the detailed wiring (hereinafter referred to as “normal width”). This is performed in order to reduce the wiring resistance by increasing the wiring width and to reduce the absolute value of the wiring delay.

  Note that specific numerical values of the thick wiring width are stored in advance in a storage area such as the ROM 102 or the RAM 103. This specific numerical value is a numerical value set in consideration of the balance between an increase in wiring capacitance and a reduction in wiring resistance due to the increased wiring width. Specifically, for example, an appropriate numerical value may be derived from the experimental result of measuring the wiring resistance variation using a simple model.

  Of the wirings in the clock net detected by the detection unit 502, the determination unit 504 changes the wiring from the circuit element that is the clock branch point to the terminal circuit element to be thicker than the wiring width of the other wirings. decide. A portion (wiring) that is common among a plurality of clock paths has a common variation in wiring delay. For this reason, of the wirings in the clock net, only the remaining wirings except the common part are made thick.

  In addition, the determination unit 504 determines, from among the wirings in the clock net detected by the detection unit 502, the wiring from the circuit element that is the clock branch point to the circuit element that is one stage before the terminal, The wiring may be determined to be thicker than the width. That is, assuming that the wiring of the terminal circuit element (such as flip-flop) is congested, the wiring to the previous circuit element is made wide.

  Specifically, for example, when the degree of wiring congestion at the terminal circuit element is high and a double space cannot be secured between adjacent wirings, the wiring up to the circuit element at the previous stage is made wide. It is good as well. Thereby, crosstalk between wirings in the terminal circuit element can be prevented.

  The changing unit 503 may change the wiring determined by the determining unit 504 to a wiring width wider than the wiring width of other wirings. At this time, the changing unit 503 may change the minimum distance between the wiring to be changed and the wiring adjacent to the wiring to be the track interval of the wiring track according to the design rule (DRC). That is, the wiring is performed in a double space in consideration of an increase in wiring capacity by making the width wide and crosstalk between adjacent wirings.

  Specifically, the changing unit 503 reads a specific numerical value of the wiring width from the storage area such as the ROM 102 or the RAM 103, and changes the wiring width of the wiring to be changed according to the specific numerical value. Note that the remaining wiring except the wiring to be changed is a wiring having a normal width in consideration of DRC. The changing process by the changing unit 503 may be automatically executed, or may be executed by receiving a user operation input.

  A series of processes by the detection unit 502, the change unit 503, and the determination unit 504 may be repeatedly executed until the hold error in the clock tree is resolved. Specifically, for example, a series of processes may be repeated until all the hold errors that conflict with the setup error are eliminated.

  In addition, preferentially set the threshold where the ratio of the correction location with respect to the location where the hold error occurs is preliminarily widened at a location where a more serious hold error has occurred (for example, a location where the setup time is more severe). When it exceeds, a series of processes by the detection unit 502, the change unit 503, and the determination unit 504 may be terminated.

  Specifically, for example, when the threshold is set to “10%”, correction is performed with priority given to a place where a more serious hold error has occurred, and the entire 10% hold error is resolved A series of processing is finished. As the threshold value, an arbitrary value can be set in advance by the user operating the keyboard 110 or the mouse 111 shown in FIG.

  Note that the acquisition unit 501, the detection unit 502, the change unit 504, and the determination unit 503 described above specifically include, for example, a program recorded in a recording medium such as the ROM 102, the RAM 103, and the HD 105 illustrated in FIG. The function is realized by the CPU 101 or by the I / F 109.

(Design support procedure of design support device)
Next, a design support processing procedure of the design support apparatus 100 according to the present embodiment will be described. FIG. 6 is a flowchart showing a design support processing procedure of the design support apparatus according to this embodiment. In the flowchart of FIG. 6, first, the acquisition unit 501 determines whether the timing analysis result analyzed using the corner condition that maximizes the time constant of the circuit to be designed is acquired (step S601).

  Here, it waits for the timing analysis result to be acquired (step S601: No), and if acquired (step S601: Yes), the detection unit 502 performs design based on the timing analysis result acquired by the acquisition unit 501. From the clock tree related to the target circuit, a clock net in which a hold error has occurred is detected (step S602).

  Thereafter, the changing unit 503 changes the wiring width of the wiring in the clock net detected by the detecting unit 502 to a wiring width that is thicker than the wiring width of another wiring different from the wiring (step S603). A series of processing by this flowchart is complete | finished.

  In step S602, a clock net in which a hold error that conflicts with a setup error has occurred in the clock tree may be detected. Furthermore, it is possible to detect a clock net in which at least one of the number of leaves, the clock frequency, and the number of gate stages is the maximum among clock nets in which a hold error and a setup error compete.

  Further, before the change processing in step S603, the determination unit 504 changes the wiring from the circuit element serving as the clock branch point to the terminal circuit element among the wirings in the clock net detected by the detection unit 502. The wiring may be determined to be thicker than the wiring width of the other wiring. In this case, the changing process by the changing unit 503 is executed based on the determination result determined by the determining unit 504.

  In step S603, according to the design rule, the minimum interval between the wiring to be changed and the wiring adjacent to the wiring may be changed to the track interval of the wiring track.

  According to the present embodiment described above, the influence of variation in wiring resistance is reduced by reducing the absolute value of the wiring delay by increasing the wiring width of the wiring in the clock net that causes the hold error. be able to. At this time, the wiring width of the wiring in the clock net that causes a hold error that conflicts with the setup error can be increased.

  Furthermore, among the clock nets that cause a hold error that conflicts with the setup error, increase the wiring width of the wiring in the clock net in which at least one of the number of leaves, the clock frequency, and the number of gate stages is maximum. Can do.

  In addition, among the wirings in the clock net, it is possible to make only the remaining wirings except for the part where the wiring delay variation is common in a plurality of clock paths thick. As a result, it is possible to prevent a reduction in the wiring rate due to an unnecessary wiring change, and it is possible to reduce useless processing related to the wiring change.

  In addition, assuming the wiring congestion at the terminal circuit element, the wiring width of the wiring to the circuit element one stage before the terminal can be increased. Thereby, the degree of wiring congestion in the terminal circuit element is increased, and crosstalk that occurs when a double space cannot be secured between adjacent wirings can be prevented.

  Furthermore, according to the design rule, the minimum distance between the wiring to be changed and the wiring adjacent to the wiring can be changed to the track interval of the wiring track. As a result, a minimum interval between wirings determined by the design rule can be ensured, and crosstalk between a wiring with a thick width and an adjacent wiring can be prevented.

  In addition, by setting the wiring width of some of the wirings described in this embodiment to be wider than the wiring width of other wirings that are different from the part of the wirings, the timing of clocks that follow the part of the wirings The design data relating to the design object circuit compensated for is recorded on a computer-readable recording medium and used by being read from the recording medium by the computer. As a result, a high-quality semiconductor integrated circuit can be provided to the market at an early stage.

  Next, examples of the above-described embodiment will be described. Here, a method for generating a clock tree of the circuit 200 to be designed will be described. FIGS. 7A and 7B are explanatory diagrams illustrating an outline of a clock tree generation method. The design target circuit 700 is divided into four clock groups A to D for each group in which clocks are synchronized. In the drawing, a part is extracted and shown.

  In (1), first, initial arrangement of circuit element groups (clock source CS, circuit elements 701 to 704) constituting the design target circuit 700 is performed. In (2), assuming that all FFs (circuit elements 701 to 703) receive clocks at the same time, timing constraints between FFs are derived, and timing optimized arrangement is performed. Then, a clock buffer is inserted, and a clock tree 710 is generated so as to minimize skew.

  In (3), temporary wiring of the clock tree 710 is performed without considering DRC. Further, temporary wiring is performed for wirings other than the clock wiring without considering DRC. Thereafter, using the temporarily wired clock tree 710, RC extraction at the RC worst corner and high temperature conditions, delay calculation, and STA are executed.

  Here, the timing analysis result acquired by the acquisition unit 501 will be described. FIG. 8 is an explanatory diagram illustrating an example of a timing analysis result. In FIG. 8, the timing analysis result 800 includes analysis results 800-1 to 800-4 regarding the number of leaves, the clock frequency, the number of gate stages, and whether or not a hold error has occurred for each clock group A to D.

  The number of leaves is the number of FFs present in each clock group A to D. The clock frequency is the operating frequency of each clock group A to D. The number of gate stages is the number of logic gates existing in each of the clock groups A to D.

  Here, taking analysis result 800-2 as an example, for clock group B, the number of leaves is 50000 [pieces], the clock frequency is 100 [Mhz], the number of gate stages is 30 [pieces], and a hold error occurs. It represents that. Next, by referring to the timing analysis result 800, the clock groups B to D in which a hold error has occurred are narrowed down.

  Furthermore, the evaluation function F is used to narrow down the clock groups that are subject to wiring change among the clock groups B to D in which the hold error has occurred. Here, the evaluation function F is “F: target (number of leaves | clock frequency | number of gate stages)”. This means that the clock group having the maximum items (number of leaves, clock frequency, number of gate stages) given as target is selected.

  For example, when the number of leaves is set as a target, an argument is set that gives a plurality of clock group names and returns the clock group name of the maximum number of leaves. Here, since the number of leaves of clock group B is the maximum, the clock group name of clock group B is returned. As a result, the detection unit 502 detects the clock net of the clock group B in the clock tree 710.

  In addition, when the clock frequency is set as a target, an argument is set that gives a plurality of clock group names and returns the clock group name of the maximum clock frequency. Here, since the clock frequency of the clock group C is the maximum, the clock group name of the clock group C is returned. As a result, the detection unit 502 detects the clock net of the clock group C in the clock tree 710.

  When the number of gate stages is set as a target, an argument is set that gives a plurality of clock group names and returns the clock group name of the maximum number of gate stages. Here, since the number of gate stages of clock group D is the maximum, the clock group name of clock group D is returned. As a result, the detection unit 502 detects the clock net of the clock group D in the clock tree 710. Here, the case where the number of gate stages is set as the target and the clock net of the clock group D is detected by the detection unit 502 will be described as an example.

  FIG. 9 is an explanatory diagram showing a clock net to be changed. In FIG. 9, the clock net 900 includes a clock source CS, clock buffers CB1 to CB11, and flip-flops FF1 and FF2. In the drawing, a part of the clock net is extracted and shown. Here, a hold error has occurred in the data signal line from the flip-flop FF1 to the flip-flop FF2.

  First, when the detection unit 502 detects the clock net 900, the wiring in the temporarily wired clock net 900 is erased. After that, the determination unit 504 causes the wirings (910 and 920 in FIG. 9) from the clock buffer CB3 to the terminal flip-flops FF1 and FF2 among the wirings in the clock net to have the normal width. Also decide to make the wiring thicker.

  Thereafter, the changing unit 503 performs detailed wiring with a wiring width larger than the normal width considering DRC for the wiring determined by the determination unit 504. Further, detailed wiring with a normal width in consideration of DRC is performed on the remaining wirings excluding the wiring determined by the determination unit 504. At this time, by ensuring the track interval of the wiring track and changing the wiring width, crosstalk between the wiring with the thick wiring and the adjacent wiring is prevented.

  Next, a design support processing procedure in the embodiment will be described. FIG. 10 is a flowchart illustrating a design support processing procedure in the embodiment. In the flowchart of FIG. 10, first, initial arrangement of circuit element groups constituting the design target circuit 700 is executed (step S1001). Thereafter, assuming that all the FFs receive the clock at the same time, the timing constraint between the FFs is derived, and the timing optimization arrangement is executed (step S1002).

  Then, a clock buffer is inserted, and a clock tree 710 is generated so as to minimize skew (step S1003). Thereafter, temporary wiring of the clock tree 710 and wirings other than the clock wiring is executed without considering DRC (step S1004). Next, the acquisition unit 501 acquires the timing analysis result 800 related to the clock tree 710 (step S1005).

  After that, the detection unit 502 detects the clock nets of the clock groups B to D where the hold error and the setup error compete (step S1006), and further, the number of gate stages of the clock nets of the clock groups B to D is the largest. The clock net 900 of the clock group D is detected (step S1007).

  Then, the wiring in the clock net 900 is deleted (step S1008), and the determination unit 504 uses the wiring from the clock buffer CB3 that is the clock branch point to the terminal flip-flops FF1 and FF2 among the wirings in the clock net 900. Are determined to be thicker than the normal width (step S1009).

  Finally, the change unit 503 performs detailed wiring with a wiring width wider than the normal width considering DRC for the wiring determined by the determination unit 504, and the remaining wiring except for the wiring determined by the determination unit 504 For the wiring, detailed wiring with a normal width in consideration of DRC is executed (step S1010).

  According to the embodiment described above, the wiring resistance variation is reduced by reducing the absolute value of the wiring delay by increasing the wiring width of the wiring in the clock net 900 that causes the generation of the hold error that conflicts with the setup error. The influence can be reduced. As a result, a setup error that conflicts with a hold error that occurs in the design target circuit 700 can be eliminated.

  Also, of the wirings in the clock net 900, only the remaining wirings can be made thick except for a portion (wiring from the clock source CS to the clock buffer CB3) where wiring delay variation is common in a plurality of clock paths. . As a result, it is possible to prevent a reduction in the wiring rate due to an unnecessary wiring change, and it is possible to reduce useless processing related to the wiring change.

  As described above, according to the program, the recording medium on which the program is recorded, the apparatus, and the method, the wiring width of the wiring that causes the hold error that conflicts with the setup error is increased and the wiring resistance variation effect Therefore, efficient and highly accurate timing verification can be realized, and the burden on the designer can be reduced and the design period can be shortened.

  The design support method described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The program may be a transmission medium that can be distributed via a network such as the Internet.

  In addition, the design support apparatus 100 described in the present embodiment includes an application-specific IC (hereinafter simply referred to as “ASIC”) such as a standard cell or a structured ASIC (Application Specific Integrated Circuit), or a PLD (Programmable) such as an FPGA. It can also be realized by Logic Device). Specifically, for example, the functional configuration 501 to 504 of the design support apparatus 100 described above is defined by HDL description, and the HDL description is logically synthesized and given to the ASIC or PLD to manufacture the design support apparatus 100. can do.

  The following supplementary notes are further disclosed with respect to the embodiments including the above examples.

(Appendix 1) An acquisition step of acquiring a timing analysis result analyzed using a corner condition that maximizes a time constant of a circuit to be designed;
Based on the timing analysis result acquired by the acquisition step, a detection step of detecting a clock net in which a hold error has occurred in the clock tree related to the design target circuit;
A change step of changing the wiring width of the wiring in the clock net detected by the detection step to a wiring width wider than the wiring width of another wiring different from the wiring,
A design support program characterized by causing a computer to execute.

(Supplementary Note 2) The detection step includes
The design support program according to appendix 1, wherein a clock net in which a hold error that conflicts with a setup error occurs in the clock tree is detected.

(Supplementary Note 3) The detection step includes
Further, among clock nets in which the hold error and the setup error compete, a clock net in which at least one of the number of leaves, the clock frequency, and the number of gate stages of the clock net is maximum is detected. 2. The design support program according to 2.

(Supplementary Note 4) Of the wirings in the clock net detected by the detection step, the wiring from the circuit element serving as the clock branch point to the terminal circuit element is made thicker than the wiring width of the other wiring. Causing the computer to execute a determination step for determining,
The changing step includes
The design support program according to any one of appendices 1 to 3, wherein the wiring determined in the determining step is changed to a wiring width wider than a wiring width of the other wiring.

(Supplementary note 5)
Of the wirings in the clock net detected by the detection step, the wiring from the circuit element serving as the clock branch point to the circuit element one stage before the terminal is thicker than the wiring width of the other wiring. The design support program according to appendix 4, wherein the design support program is determined by

(Appendix 6)
According to any one of appendices 1 to 5, wherein the minimum interval between the wiring to be changed and the wiring adjacent to the wiring is changed to the track interval of the wiring track according to the design rule. Design support program.

(Supplementary note 7) A computer-readable recording medium in which the design support program according to any one of supplementary notes 1 to 6 is recorded.

(Appendix 8) By making the wiring width of a part of the wiring wider than the wiring width of another wiring different from the part of the wiring, the timing of the clock that traces the part of the wiring is compensated. A computer-readable recording medium in which design data related to a design target circuit is recorded.

(Supplementary Note 9) By making the wiring width of some wirings wider than the wiring width of other wirings different from the part of the wirings, the timing of the clock that traces the part of the wiring is compensated. A semiconductor integrated circuit.

(Supplementary Note 10) Acquisition means for acquiring a timing analysis result analyzed using a corner condition that maximizes a time constant of a circuit to be designed;
Based on the timing analysis result acquired by the acquisition unit, a detection unit that detects a clock net in which a hold error has occurred among clock trees related to the design target circuit;
Changing means for changing the wiring width of the wiring in the clock net detected by the detecting means to a wiring width that is thicker than the wiring width of other wiring different from the wiring;
A design support apparatus characterized by comprising:

(Additional remark 11) The acquisition process which acquires the timing analysis result analyzed using the corner conditions in which the time constant of a design object circuit becomes the maximum,
Based on the timing analysis result acquired by the acquisition step, a detection step of detecting a clock net in which a hold error has occurred among clock trees related to the design target circuit;
Changing the wiring width of the wiring in the clock net detected by the detection step to a wiring width wider than the wiring width of other wiring different from the wiring;
The design support method characterized by including.

It is a block diagram which shows the hardware constitutions of the design support apparatus concerning this Embodiment. It is explanatory drawing which shows the outline | summary of this Embodiment. It is explanatory drawing which shows a wiring corner. It is explanatory drawing which shows the structure definition of wiring. It is explanatory drawing which shows a wiring cross-section structure image. It is a block diagram which shows the functional structure of the design assistance apparatus concerning this Embodiment. It is a flowchart which shows the design assistance processing procedure of the design assistance apparatus concerning this Embodiment. It is explanatory drawing (the 1) which shows the outline | summary of the production | generation method of a clock tree. It is explanatory drawing (the 2) which shows the outline | summary of the production | generation method of a clock tree. It is explanatory drawing which shows an example of a timing analysis result. It is explanatory drawing which shows the clock net of wiring change object. It is a flowchart which shows the design assistance process procedure in an Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Design support apparatus 200,700 Design object circuit 410 Wiring structure table 420 Interlayer insulation film 430 Wiring metal 501 Acquisition part 502 Detection part 503 Change part 504 Determination part 701-704 Circuit element 710 Clock tree 800 Timing analysis result 900 Clock net

Claims (6)

An acquisition process for acquiring a timing analysis result analyzed using a corner condition that maximizes the time constant of the circuit to be designed;
Based on the timing analysis result acquired by the acquisition step, a detection step of detecting a clock net in which a hold error has occurred among clock trees related to the design target circuit;
Among the wirings in the clock net detected by the detection step, the wiring from the circuit element serving as the clock branch point to the terminal circuit element is made thicker than the wiring width of the other wiring different from the wiring. A decision process to decide;
A change step of changing the wiring determined by the determination step to a wiring width wider than the wiring width of the other wiring,
A design support program characterized by causing a computer to execute. The detection step includes
The design support program according to claim 1, wherein a clock net in which a hold error that conflicts with a setup error has occurred is detected in the clock tree. The detection step includes
Furthermore, among the clock nets and the hold error and the set-up error conflict, wherein the leaf number of the clock net, is at least one of the clock frequency and the number of gate stages and detecting a clock nets which maximizes Item 3. The design support program according to Item 2.   The determination step includes
  Of the wirings in the clock net detected by the detection step, the wiring from the circuit element serving as the clock branch point to the circuit element one stage before the terminal is thicker than the wiring width of the other wiring. The design support program according to claim 1, wherein the design support program is determined as follows.   An acquisition means for acquiring a timing analysis result analyzed using a corner condition that maximizes a time constant of a circuit to be designed;
  Based on the timing analysis result acquired by the acquisition unit, a detection unit that detects a clock net in which a hold error has occurred among clock trees related to the design target circuit;
  Among the wirings in the clock net detected by the detecting means, the wiring from the circuit element that is the clock branch point to the terminal circuit element is made thicker than the wiring width of the other wiring different from the wiring. A decision means to decide;
  Changing means for changing the wiring determined by the determining means to a wiring width wider than the wiring width of the other wiring;
  A design support apparatus characterized by comprising:   Computer
  An acquisition process for acquiring a timing analysis result analyzed using a corner condition that maximizes the time constant of the circuit to be designed;
  Based on the timing analysis result acquired by the acquisition step, a detection step of detecting a clock net in which a hold error has occurred among clock trees related to the design target circuit;
  Among the wirings in the clock net detected by the detection step, the wiring from the circuit element serving as the clock branch point to the terminal circuit element is made thicker than the wiring width of the other wiring different from the wiring. A decision process to decide;
  A change step of changing the wiring determined by the determination step to a wiring width wider than the wiring width of the other wiring,
  A design support method characterized by executing

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