JP2007264993A - Verification support apparatus, verification support method, verification support program and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten a design period by efficiently preparing a logic library in a simple way. <P>SOLUTION: The verification support apparatus 200 is provided with a logic library preparation part 202. In the logic library preparation part 202, the layout information of a preparation object cell is acquired by a layout information acquisition part 701. By a circuit information extraction part 702, the circuit information is extracted from the layout information of the preparation object cell. The characteristic information of a transistor, a resistor and a capacitor is extracted by a characteristic information extraction part 703, and connection information is extracted by a connection information extraction part 704. Then, the library information of the preparation object cell is generated. Thus, the logic library 220 is prepared. By the logic library preparation part 202, the logic library 220 flexibly adaptable to the manufacture process change of an LSI and the addition of cells, etc., is automatically generated. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a verification support apparatus, a verification support method, a verification support program, and a recording medium that support LSI logic verification.

  In LSI design, it is indispensable to check the operation by logic verification work such as logic simulation to verify whether the LSI operates normally. Especially, large scale, high functionality, high speed and low consumption For LSIs that are required to be powered, this logic verification work is important in order to maintain high quality. On the other hand, work efficiency has been demanded by shortening the design period.

  In the actual machine level logic simulation, a net list described by cells, delay information obtained from a physical layout (SDF (Standard Delay File) file), and a logic library are used.

  The logic library includes characteristic information obtained from layout information such as parasitic resistance, parasitic capacitance, and transistor in each cell, and its operation description. When performing logic simulation, LSI delay information is obtained for each operation condition from inter-cell wiring resistance / capacitance obtained from the physical layout and cell characteristic information.

  For this reason, since it is necessary for the logic library to include the characteristic information of the assumed operating conditions, the transistor model that is the source of the logic library must be the same. When creating a transistor model, a transistor evaluation chip (Tr TEG) is created for each assumed operating condition, and characteristic information is obtained using the transistor evaluation chip, thereby enabling creation of a logic library. . As for the creation of a logical library, for example, the technique disclosed in Patent Document 1 below can be cited.

JP 2000-181946 A

  However, in the above-described conventional logic library creation, there is a problem that it takes time to create a logic library because two steps of a transistor model creation process and a cell library creation process must be performed. Further, as the number of types of cells is increased in order to facilitate LSI development, there is a problem that the creation time of the logic library becomes longer. Therefore, there is a problem that it is difficult to re-create a logical library in a short time even if characteristics are improved or manufacturing equipment is changed.

  The present invention eliminates the problems caused by the prior art described above, and can easily reduce the design period by creating a logical library simply and efficiently, a verification support apparatus, a verification support method, and a verification support program And a recording medium.

  In order to solve the above-described problems and achieve the object, the verification support apparatus, the verification support method, the verification support program, and the recording medium according to the present invention acquire and acquire circuit information about the cell for each cell. The transistor constituting the cell is detected from the circuit information, characteristic information about the transistor is calculated, and the calculated characteristic information is stored in a database for each transistor type.

  According to the present invention, transistor characteristic information can be collected for each transistor type.

  In the above invention, the layout information of the creation target cell is acquired, the circuit information about the creation target cell is extracted from the acquired layout information, and the characteristic information about the transistor specified by the extracted circuit information is extracted from the database. Based on the extracted characteristic information relating to the transistor, library information relating to the creation target cell may be generated.

  According to the present invention, automatic generation of a logical library can be efficiently performed. Further, even if the transistors constituting the cell are changed due to the change of the LSI manufacturing process, new library information can be generated only by changing the transistor characteristic information extracted from the transistor characteristic information DB.

  Further, in the above invention, characteristic information relating to other circuit elements other than the transistor specified by the extraction circuit information is extracted from the extraction circuit information, and based on the extracted characteristic information relating to the transistors and other circuit elements, Library information relating to the creation target cell may be generated.

  According to the present invention, it is also possible to automatically create a library of characteristic information of other circuit elements (resistance, capacitance) constituting a cell from which the cell delay value is calculated.

  In the above invention, the connection information of the transistor specified by the extraction circuit information and other circuit elements is extracted from the extraction circuit information, and library information related to the creation target cell is generated based on the extracted connection information. It is good to do.

  According to the present invention, it is possible to automatically create a library of connection information, which is a calculation source of the cell delay value.

  In the above invention, circuit information related to a circuit to be verified is acquired, and circuit information including an arbitrary cell that is a delay value calculation target and an additional circuit element connected to the cell from the acquired circuit information ( (Hereinafter referred to as “calculation target circuit information”), library information relating to the cell specified by the calculated calculation target circuit information is extracted from the generated library information group, and based on the extracted library information Then, the delay value of the cell specified by the calculation target circuit information may be calculated, and the calculated calculation result may be output.

  According to the present invention, it is possible to efficiently calculate the delay value of the cell in the circuit to be verified.

  Further, in the above invention, based on the library information, the calculation target circuit information is divided for each transistor constituting a cell specified by the calculation target circuit information, and the characteristic information related to the transistor included in the library information is obtained. On the basis of this, a delay value may be calculated for each divided calculation target circuit information, and the calculation result may be output as a delay value of a cell specified by the calculation target circuit information.

  According to the present invention, it is possible to increase the accuracy of the calculated delay value of the cell in the circuit to be verified.

  According to the verification support apparatus, the verification support method, the verification support program, and the recording medium according to the present invention, it is possible to shorten the design period by creating a logical library simply and efficiently. .

  Exemplary embodiments of a verification support apparatus, a verification support method, a verification support program, and a recording medium according to the present invention will be described below in detail with reference to the accompanying drawings.

(Hardware configuration of verification support device)
First, the hardware configuration of the verification support apparatus according to the embodiment of the present invention will be described. FIG. 1 is a block diagram showing a hardware configuration of a verification support apparatus according to an embodiment of the present invention.

  In FIG. 1, the verification support apparatus is an example of a CPU 101, ROM 102, RAM 103, HDD (hard disk drive) 104, HD (hard disk) 105, FDD (flexible disk drive) 106, and a removable recording medium. FD (flexible disk) 107, display 108, I / F (interface) 109, keyboard 110, mouse 111, scanner 112, and printer 113. Each component is connected by a bus 100.

  Here, the CPU 101 controls the entire verification support apparatus. The ROM 102 stores a program such as a boot program. The RAM 103 is used as a work area for the CPU 101. The HDD 104 controls reading / writing of data with respect to the HD 105 according to the control of the CPU 101. The HD 105 stores data written under the control of the HDD 104.

  The FDD 106 controls reading / writing of data with respect to the FD 107 according to the control of the CPU 101. The FD 107 stores data written under the control of the FDD 106, or causes the verification support apparatus to read data stored in the FD 107.

  In addition to the FD 107, the removable recording medium may be a CD-ROM (CD-R, CD-RW), MO, DVD (Digital Versatile Disk), memory card, or the like. The display 108 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. As this display 108, for example, a CRT, a TFT liquid crystal display, a plasma display, or the like can be adopted.

  The I / F 109 is connected to a network 114 such as the Internet through a communication line, and is connected to other devices via the network 114. The I / F 109 controls an internal interface with the network 114 and controls data input / output from an external device. For example, a modem or a LAN adapter may be employed as the I / F 109.

  The keyboard 110 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Moreover, a touch panel type input pad or a numeric keypad may be used. The mouse 111 performs cursor movement, range selection, window movement, size change, and the like. A trackball or a joystick may be used as long as they have the same function as a pointing device.

  The scanner 112 optically reads an image and takes in the image data into the verification support apparatus. The scanner 112 may have an OCR function. The printer 113 prints image data and document data. For example, a laser printer or an ink jet printer can be employed as the printer 113.

(Functional configuration of verification support device)
Next, a functional configuration of the verification support apparatus according to the embodiment of the present invention will be described. FIG. 2 is a block diagram showing a functional configuration of the verification support apparatus according to the embodiment of the present invention. In FIG. 2, the verification support apparatus 200 includes a transistor characteristic information creation unit 201, a logic library creation unit 202, and a delay value calculation unit 203.

  The transistor characteristic information creation unit 201 creates transistor characteristic information for each transistor type. A set of the transistor characteristic information is a transistor characteristic information DB 210. Further, the logic library creating unit 202 creates a cell logic library 220 using the transistor characteristic information stored in the transistor characteristic information DB 210. In addition, the delay value calculation unit 203 calculates the delay value of the cell in the verification target circuit using the library information of the cell stored in the logic library 220. The calculated cell delay value is used for logic simulation.

  Detailed functional configurations of the transistor characteristic information creation unit 201, the logic library creation unit 202, and the delay value calculation unit 203 will be described later. The transistor characteristic information creation unit 201, the logic library creation unit 202, and the delay value calculation unit 203 are specifically programs recorded in a recording medium such as the ROM 102, the RAM 103, and the HD 105 shown in FIG. Is realized by the CPU 101 or by the I / F 109.

(Contents stored in transistor characteristic information DB 210)
Next, the contents stored in the transistor characteristic information DB 210 shown in FIG. 2 will be described. FIG. 3 is an explanatory diagram showing the stored contents of the transistor characteristic information DB 210 shown in FIG. In FIG. 3, the transistor characteristic information DB 210 stores transistor characteristic information Fi for each transistor type Tri (i = 1 to n).

  Here, the transistor type Tri represents the classification of the transistor, and includes various operating conditions such as size information (Poly width, Poly length, etc.) Si, P type / N type, standard driving voltage, operating temperature, and the like. Appears. The size information Si is used in the logical library creation unit 202.

  The transistor characteristic information Fi is information representing the characteristics of the transistor corresponding to the transistor type Tri. Specifically, for example, the classification according to the transistor type Tri, that is, the resistance and capacitance when the operating condition is given. Indicates. In the transistor characteristic information Fi and Fj shown in FIG. 3, the transistor characteristics are indicated by the resistance between the source and the drain, the resistance between the gate and the drain, the input capacitance, and the output capacitance.

  In this way, by classifying by transistor type Tri, not by an unspecified number (X) of transistors, the transistor characteristic information DB 210 is obtained from a smaller number (n) of transistor characteristic information Fi than the number of transistors (X). Can be built. Therefore, the creation time can be shortened compared to the conventional transistor model creation process. Note that, specifically, the transistor characteristic information DB 210 realizes its function by a recording medium such as the ROM 102, the RAM 103, and the HD 105 shown in FIG.

(Storage contents of the logical library 220)
Next, the contents stored in the logical library 220 shown in FIG. 2 will be described. FIG. 4 is an explanatory diagram showing the storage contents of the logical library 220 shown in FIG. In FIG. 4, the logic library 220 stores a cell operation description Ak and cell internal information Ik for each cell CEk (k = 1 to m). The cell internal information Ik stores connection information in the cell CEk and characteristic information thereof for each circuit element type in the cell CEk.

  For example, if the circuit element in the cell CEk includes a transistor of the transistor type Tri, connection information (PCH (VCC, NET1, NET2)) of the transistor type Tri and transistor characteristic information Fi are stored.

  Similarly, if the circuit element in the cell CEk includes a resistor of resistance type R1, connection information (A, NET1) and resistance characteristic information r1 of resistance type R1 are stored. The resistance characteristic information r1 is information representing the characteristic of the resistance, for example, a resistance value.

  Similarly, assuming that the circuit element in the cell CEk includes a resistance of the capacity type C1, connection information (NET1, VCC) and capacity characteristic information c1 of the capacity type C1 are stored. The resistance characteristic information c1 is information representing the characteristics of the capacitance, and is, for example, a capacitance value. Note that, specifically, the transistor characteristic information DB 210 realizes its function by a recording medium such as the ROM 102, the RAM 103, and the HD 105 shown in FIG.

(Functional configuration of transistor characteristic information creation unit 201)
Next, a functional configuration of the transistor characteristic information creation unit 201 illustrated in FIG. 2 will be described. FIG. 5 is a block diagram showing a functional configuration of the transistor characteristic information creation unit 201 shown in FIG. In FIG. 5, the transistor characteristic information creation unit 201 includes a cell circuit information acquisition unit 501, a transistor detection unit 502, a characteristic information calculation unit 503, and a storage unit 504.

  First, the cell circuit information acquisition unit 501 acquires circuit information related to the cell for each cell. Here, the cell is a circuit that includes a circuit element including a transistor and has a specific function.

  For example, logic gate circuits such as buffers, inverters, AND circuits, OR circuits, NAND circuits, NOR circuits, XOR circuits, matching circuits, comparison circuits, combinational logic circuits such as decoders, encoders, multiplexers, demultiplexers, various flip-flops, etc. And a digital arithmetic circuit combining sequential logic circuits such as a counter and a shift register.

  Further, the circuit information regarding the cell is equivalent circuit data in which the cell is represented by a circuit element such as a transistor. Hereinafter, the circuit information regarding the cell is referred to as cell circuit information. Further, the transistor detection unit 502 detects a transistor constituting the cell from the cell circuit information acquired by the cell circuit information acquisition unit 501. For example, when the cell is an inverter, one P-type transistor and one N-type transistor are detected from the equivalent circuit data.

  In addition, the characteristic information calculation unit 503 calculates transistor characteristic information Fi of the transistor detected by the transistor detection unit 502. Specifically, transistor characteristic information is narrowed down according to various operating conditions such as the above-described size information (Poly width, Poly length, etc.) Si, P-type / N-type, standard drive voltage, operating temperature, etc., and transistor characteristic information Fi is calculated. If the same kind of transistor characteristic information Fi has already been calculated, there is no need to calculate it.

  The storage unit 504 stores the transistor characteristic information Fi calculated by the characteristic information calculation unit 503 in the transistor characteristic information DB 210 for each transistor type Tri. Thereby, the transistor characteristic information DB 210 shown in FIG. 3 can be constructed.

(Creation processing procedure of transistor characteristic information creation unit 201)
Next, a creation processing procedure of the above-described transistor characteristic information creation unit 201 will be described. FIG. 6 is a flowchart showing a creation processing procedure of the transistor characteristic information creation unit 201. In FIG. 6, first, it is determined whether or not there is an unprocessed cell (step S601). If there is an unprocessed cell (step S601: Yes), the cell circuit information acquisition unit 501 determines the cell of the unprocessed cell. Circuit information is acquired (step S602).

  Then, the transistor is detected from the cell circuit information by the transistor detection unit 502 (step S603). Then, the transistor characteristic information is calculated by the characteristic information calculation unit 503 (step S604). Thereafter, the process returns to step S601.

  On the other hand, if it is determined in step S601 that there is no unprocessed cell (step S601: No), the storage unit 504 stores it in the transistor characteristic information DB 210 for each transistor type Tri (step S605). As a result, the series of processes is completed.

  According to the transistor characteristic information creation unit 201, since the transistors can be narrowed down to the transistor type Tri, the transistor characteristic information Fi of the transistors in many cells can be collected. Therefore, only the necessary transistor type Tri needs to be made into a library, and man-hours can be reduced. In addition, when the same kind of transistor characteristic information Fi has already been calculated, it is not necessary to calculate, so that the calculation efficiency can be improved.

(Functional configuration of the logical library creation unit 202)
Next, a functional configuration of the logic library creation unit 202 shown in FIG. 2 will be described. FIG. 7 is a block diagram showing a functional configuration of the logical library creation unit 202 shown in FIG. In FIG. 7, the logical library creation unit 202 includes a layout information acquisition unit 701, a circuit information extraction unit 702, a characteristic information extraction unit 703, a connection information extraction unit 704, and a generation unit 705.

  The layout information acquisition unit 701 acquires layout information of a cell (creation target cell) that is a creation target of the logical library 220. Specifically, the layout information of the creation target cell created by the layout tool is acquired. FIG. 8 is an explanatory diagram showing an example of development of the inverter. When the creation target cell is the inverter 801, the layout information 802 is read.

  The circuit information extraction unit 702 extracts circuit information related to the creation target cell from the layout information acquired by the layout information acquisition unit 701. This extracted circuit information is referred to as extracted circuit information. The extraction rules include, for example, pattern recognition rules and RC extraction rules. The pattern recognition rule is a rule for recognizing patterns such as transistors, metals, and vias.

  The RC extraction rule extracts the resistance and capacitance of the pattern recognized according to the pattern recognition rule. Then, extraction circuit information is obtained from the recognized pattern, resistance, and capacitance. In the inverter 801 shown in FIG. 8, circuit data 803 indicating the equivalent circuit can be extracted from the layout information 802.

  Further, the characteristic information extraction unit 703 extracts the transistor characteristic information Fi specified by the extraction circuit information from the transistor characteristic information DB 210. For example, in the case of the circuit data 803 shown in FIG. 8, the transistor types Tri and Trj that are equivalent to the size of the transistors Tra and Trb in the circuit data 803 (match or within a predetermined error) are specified. Then, transistor characteristic information Fi and Fj of the specified transistor types Tri and Trj are extracted.

  In addition, the characteristic information extraction unit 703 extracts characteristic information related to other circuit elements other than the transistor specified by the extraction circuit information from the extraction circuit information. That is, characteristic information relating to circuit elements (resistance, capacitance) other than the transistors included in the extraction circuit information is extracted. For example, the characteristic information regarding the resistance is the resistance value of the resistance, and the characteristic information regarding the capacity is the capacitance value of the capacity.

  In addition, the connection information extraction unit 704 extracts the connection information of the transistor specified by the extraction circuit information and other circuit elements from the extraction circuit information. Specifically, connection information representing connection relationships among the gate, source, drain, power supply VCC, VSS, resistance, and capacitance of the transistor is extracted from the extraction circuit information. For example, the connection information shown in FIG. 4 can be obtained for the circuit data 803 shown in FIG.

  That is, since the type of the transistor Tra is the transistor type Tri, connection information (VCC, NET1, NET2) can be obtained. In addition, connection information as shown in FIG. 4 can be obtained for the transistor Trb, resistors R1 and R2, and capacitors C1 and C2. This connection information and characteristic information Fi, Fj, r1, r2, c1, c2 of various circuit elements (transistors, resistors, capacitors) are obtained.

  Also, the generation unit 705 generates library information related to the creation target cell based on the extraction circuit information and the characteristic information extracted by the characteristic information extraction unit 703. Specifically, connection information and characteristic information are associated with each in-cell circuit element constituting the extraction circuit information and stored in the logic library 220.

  For example, in the circuit data 803 shown in FIG. 8, since the type of the transistor Tra is the transistor type Tri, the connection information (VCC, NET1, NET2) is associated with the transistor characteristic information Fi. Other circuit elements (transistor Trb, resistors R1 and R2, capacitors C1 and C2) are similarly associated, and cell internal information Ik as shown in FIG. 4 is generated. Library information of the creation target cell CEk (in this case, the inverter 801 shown in FIG. 8) including the cell internal information Ik and the cell operation description Ak is obtained.

(Creation processing procedure of the logical library creation unit 202)
Next, the creation processing procedure of the logical library creation unit 202 will be described. FIG. 9 is a flowchart showing a creation processing procedure of the logical library creation unit 202. First, it is determined whether or not there is a creation target cell CEk (step S901). If there is a creation target cell CEk (step S901: Yes), the layout information acquisition unit 701 acquires layout information (step S902).

  Next, the circuit information extraction unit 702 extracts the circuit information from the layout information of the creation target cell CEk (step S903). Thereafter, the characteristic information extraction unit 703 extracts transistor, resistance, and capacitance characteristic information, and the connection information extraction unit 704 extracts connection information (step S904). Then, library information of the creation target cell CEk is generated (step S905). Thereafter, the process returns to step S901.

  In step S901, when there is no creation target cell CEk (step S901: No), a series of processing ends. As a result, the logical library 220 shown in FIG. 4 can be created. According to the logic library creation unit 202, a logic library 220 that can flexibly cope with a change in an LSI manufacturing process or addition of a cell can be automatically generated.

(Functional configuration of delay value calculation unit 203)
Next, a functional configuration of the delay value calculation unit 203 illustrated in FIG. 2 will be described. FIG. 10 is a block diagram showing a functional configuration of the delay value calculation unit 203 shown in FIG. In FIG. 10, the delay value calculation unit 203 includes a verification target circuit information acquisition unit 1001, a calculation target circuit information extraction unit 1002, a library information extraction unit 1003, a division unit 1004, a delay value calculation unit 1005, and an output unit. 1006.

  The verification target circuit information acquisition unit 1001 acquires circuit information related to the verification target circuit. Here, the verification target circuit is a circuit that is a target of logic simulation. The circuit information (hereinafter referred to as “verification target circuit information”) 1000 regarding the verification target circuit is circuit information including a net list 1010 and layout information 1020 of the verification target circuit.

  The calculation target circuit information extraction unit 1002 includes, from the verification target circuit information 1000, circuit information (hereinafter referred to as “calculation target circuit information”) including an arbitrary cell that is a delay value calculation target and an additional circuit element connected to the cell. "). Here, the additional circuit element is a circuit element such as a resistor or a capacitor connected to an input terminal or an output terminal of a cell that is a delay value calculation target.

  The library information extraction unit 1003 extracts library information about the cell specified by the calculation target circuit information extracted by the calculation target circuit information extraction unit 1002 from the logic library 220. For example, if the cell specified by the calculation target circuit information is an inverter, the library information of the inverter is extracted from the logic library 220.

  Further, the dividing unit 1004 divides the calculation target circuit information for each transistor constituting the cell specified by the calculation target circuit information based on the library information extracted by the library information extraction unit 1003. Specifically, when there are a plurality of transistors constituting a cell in the calculation target circuit information, the equivalent circuit of the cell is divided for each transistor.

  The delay value calculation unit 1005 calculates the delay value of the cell specified by the calculation target circuit information based on the library information extracted by the library information extraction unit 1003. Specifically, the delay value is calculated for each calculation target circuit information divided by the dividing unit 1004 based on the transistor characteristic information Fi of the transistors included in the library information extracted by the library information extracting unit 1003. For example, the delay value of the divided calculation target circuit information is calculated using transistor characteristic information that matches the transistor of the divided calculation target circuit information.

  The output unit 1006 outputs the calculation result calculated by the delay value calculation unit 1005. Specifically, the calculation result calculated by the delay value calculation unit 1005 is output as the delay value of the cell specified by the calculation target circuit information. The delay value calculation unit 1005 calculates a delay value for each divided calculation target circuit information, that is, for each transistor. Therefore, the delay value of the cell is information including the delay value for each transistor.

  Next, a specific calculation processing example of the delay value calculation unit 203 will be described. FIG. 11 is a process diagram illustrating a specific calculation processing example of the delay value calculation unit 203. In FIG. 11, an inverter will be specifically described as an example. First, in step (A), a net list 1010 and layout information 1020 that are verification target circuit information 1000 are prepared.

  Next, in step (B), the calculation target circuit information extraction unit 1002 extracts the inverter which is an arbitrary cell CEk and the resistors Ra, Rx, Ca and Cx which are the additional circuit elements. Next, in step (C), the library information extraction unit 1003 extracts the library information of the cell CEk from the logic library 220. Thereby, an equivalent circuit 1100 of the cell CEk is obtained.

  Next, in step (D), the dividing unit 1004 divides the equivalent circuit 1100 of the cell CEk for each of the transistors Tra and Trb. As a result, an equivalent circuit 1101 having a transistor Tra and an equivalent circuit 1102 having a transistor Trb are obtained. The equivalent circuit 1101 represents the state transition of the inverter from 0 → 1 → 0, and the equivalent circuit 1102 represents the state transition of the inverter from 1 → 0 → 1.

  In equivalent circuits 1101 and 1102, resistors Ra and R1 are merged to form resistor Ra1, resistors R2 and Rx are merged to form resistor R2x, capacitors Ca and C1 are merged to form capacitor Ca1, and capacitors C2 and Cx are merged. The capacity is C2x.

  Next, in step (E), the delay value calculation unit 1005 calculates a delay value for each of the equivalent circuits 1101 and 1102. Thereby, the delay values Da and Db can be obtained for each operation of the transistors Tra and Trb constituting the cell CEk. Finally, in step (F), the output unit 1006 outputs the delay values Da and Db for each of the equivalent circuits 1101 and 1102 as the delay value of the cell CEk.

  Here, the delay value calculation processing by the delay value calculation unit 1005 will be specifically described. FIG. 12 is an explanatory diagram showing the equivalent circuit 1102 and its signal waveform. In FIG. 12, Slew (in) is a round of the input signal waveform 1201, and Slew (out) is a round of the output signal waveform 1202. The time distance between the input signal waveform 1201 and the output signal waveform 1202 is the delay value Db.

  FIG. 13 is a chart showing a reference table of the SPICE simulator. In FIG. 13, a table 1301 is an input side table, and a table 1302 is an output side table. Tables 1301 and 1302 are prepared for each temperature range.

  The delay value Db is obtained from the table 1302 by a combination of the delay value obtained from the table 1301 by the combination of Slew (in) and the input addition RC (in) and the combination of Slew (in) and the output addition RC (out). (Out) and the sum.

  In FIG. 13, an input addition RC (in) is an addition of an input side circuit composed of a resistor Ra1 and a capacitor Ca1. Similarly, the output addition RC (out) is an addition of an input side circuit composed of a resistor R2x and a capacitor C2x.

  For example, when Slew (in) = Slew (in2), input addition RC (in) = RC (in3), and output addition RC (out) = RC (out2) at a certain temperature T, the delay value Delay23 from the table 1301 is obtained. Is read, and Slew (out23) is read from the table 1302. The delay value Db is the sum of the delay value Delay23 and Slew (out22).

(Calculation procedure of delay value calculation unit 203)
Next, a calculation processing procedure of the delay value calculation unit 203 will be described. FIG. 14 is a flowchart showing a calculation processing procedure of the delay value calculation unit 203. In FIG. 14, first, the verification target circuit information acquisition unit 1001 acquires the verification target circuit information 1000 (step S1401), and determines whether there is an unprocessed cell (step S1402). When there is an unprocessed cell (step S1402: Yes), the calculation target circuit information extraction unit 1002 extracts the calculation target circuit information from the verification target circuit information 1000 (step S1403).

  Next, library information of the cell specified by the calculation target circuit information is extracted from the logic library 220 (step S1404). By extracting the library information, an equivalent circuit of the cell can be obtained.

  Then, the dividing unit 1004 divides the equivalent circuit for each transistor (step S1405), and the delay value calculating unit 1005 calculates the delay value for each transistor (step S1406). Then, the calculation result is output (step S1407), and the process returns to step S1402. Thereafter, in step S1402, if there is no unprocessed cell (step S1402: No), the series of processes is terminated.

  According to this delay value calculation process, since the delay value of the cell can be calculated for each transistor, the reliability of the delay value can be improved and the accuracy of the logic simulation can be improved.

  As described above, according to the embodiment of the present invention, it is possible to reduce the man-hours required for creating a logic library used for logic simulation of an LSI. Further, when there is a change in the manufacturing process, it is only necessary to re-create necessary types of transistor characteristic information. When the cell physical information is changed, it is not necessary to calculate the cell characteristic information by correcting the transistor type Tri or the like.

  Further, when adding a logic cell, only the operation description, transistor type Tri, resistance, and capacitance need be obtained. In other words, it is possible to share the man-hours for calculating the cell characteristics that have been performed in a lump for the LSI chip delay calculation.

  Therefore, a logic library 220 that can flexibly cope with process changes and cell additions can be developed, and only the necessary transistor type Tri needs to be made into a library, thereby reducing the number of steps for creating the logic library.

  As described above, according to the verification support device, the verification support method, the verification support program, and the recording medium, the design period can be shortened by creating the logic library 220 easily and efficiently.

  The verification support method described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The program may be a transmission medium that can be distributed via a network such as the Internet.

(Appendix 1) Cell circuit information acquisition means for acquiring circuit information related to the cell for each cell;
Detecting means for detecting a transistor constituting the cell from circuit information acquired by the cell circuit information acquiring means;
Characteristic information calculating means for calculating characteristic information about the transistor detected by the detecting means;
Storage means for storing the characteristic information calculated by the characteristic information calculation means in a database for each transistor type;
A verification support apparatus comprising:

(Supplementary Note 2) Layout information acquisition means for acquiring layout information of a creation target cell;
Circuit information extraction means for extracting circuit information relating to the creation target cell from layout information acquired by the layout information acquisition means;
Characteristic information extraction means for extracting characteristic information about the transistor specified by the circuit information extracted by the circuit information extraction means from the database;
Generating means for generating library information relating to the creation target cell based on the circuit information and the characteristic information relating to the transistor extracted by the characteristic information extracting means;
The verification support apparatus according to Supplementary Note 1, further comprising:

(Supplementary Note 3) Layout information acquisition means for acquiring layout information of a creation target cell;
Circuit information extraction means for extracting circuit information relating to the creation target cell from layout information acquired by the layout information acquisition means;
A characteristic for extracting characteristic information relating to a transistor specified by circuit information extracted by the circuit information extracting means (hereinafter referred to as “extracted circuit information”) from a set of characteristic information relating to the transistor obtained for each transistor type. Information extraction means;
Based on the extraction circuit information and the characteristic information extracted by the characteristic information extraction means, generation means for generating library information related to the creation target cell;
A verification support apparatus comprising:

(Supplementary Note 4) The characteristic information extracting means includes:
Extracting characteristic information about circuit elements other than the transistor specified by the extraction circuit information from the extraction circuit information,
The generating means includes
4. The verification support apparatus according to appendix 2 or 3, wherein library information relating to the creation target cell is generated based on characteristic information relating to the transistor and other circuit elements extracted by the characteristic information extracting means.

(Supplementary note 5) comprising connection information extracting means for extracting connection information of the transistor specified by the extraction circuit information and other circuit elements from the extraction circuit information;
The generating means includes
The verification support apparatus according to any one of appendices 2 to 4, wherein library information related to the creation target cell is generated based on the connection information extracted by the connection information extraction unit.

(Appendix 6) Verification target circuit information acquisition means for acquiring circuit information related to the verification target circuit;
Among the circuit information acquired by the verification target circuit information acquisition means, circuit information (hereinafter referred to as “calculation target circuit information”) consisting of an arbitrary cell as a delay value calculation target and an additional circuit element connected to the cell. Calculation target circuit information extracting means for extracting
Library information extraction means for extracting library information related to the cell specified by the calculation target circuit information detected by the calculation target circuit information extraction means from the library information group generated by the generation means;
A delay value calculating means for calculating a delay value of a cell specified by the calculation target circuit information based on the library information extracted by the library information extracting means;
Output means for outputting a calculation result calculated by the delay value calculating means;
A verification support apparatus comprising:

(Additional remark 7) It is provided with the division means which divides | segments the said calculation object circuit information for every transistor which comprises the cell specified by the said calculation object circuit information based on the library information extracted by the said library information extraction means,
The delay value calculating means includes
Based on the characteristic information about the transistors included in the library information extracted by the library information extraction unit, a delay value is calculated for each calculation target circuit information divided by the division unit,
The output means includes
The verification support apparatus according to appendix 6, wherein the calculation result calculated by the delay value calculation means is output as a delay value of a cell specified by the calculation target circuit information.

(Supplementary note 8) A cell circuit information acquisition step for acquiring circuit information about the cell for each cell;
A detection step of detecting a transistor constituting the cell from the circuit information acquired by the cell circuit information acquisition step;
A characteristic information calculation step of calculating characteristic information about the transistor detected by the detection step;
A storage step of storing the characteristic information calculated by the characteristic information calculation step in a database for each transistor type;
A verification support method characterized by including

(Supplementary note 9) Layout information acquisition step of acquiring layout information of a creation target cell;
A circuit information extraction step for extracting circuit information relating to the creation target cell from the layout information acquired by the layout information acquisition step;
A characteristic for extracting characteristic information about a transistor specified by circuit information extracted by the circuit information extraction step (hereinafter referred to as “extracted circuit information”) from a set of characteristic information about the transistor obtained for each transistor type. An information extraction process;
Based on the extraction circuit information and the characteristic information extracted by the characteristic information extraction step, a generation step of generating library information related to the creation target cell;
A verification support method characterized by including

(Additional remark 10) The cell circuit information acquisition process which acquires the circuit information regarding the said cell for every cell,
A detection step of detecting a transistor constituting the cell from the circuit information acquired by the cell circuit information acquisition step;
A characteristic information calculation step for calculating characteristic information about the transistor detected by the detection step;
A storing step of storing the characteristic information calculated by the characteristic information calculating step in a database for each transistor type;
A verification support program characterized by causing a computer to execute.

(Additional remark 11) The layout information acquisition process of acquiring the layout information of a production target cell;
A circuit information extraction step for extracting circuit information relating to the creation target cell from the layout information acquired by the layout information acquisition step;
A characteristic for extracting characteristic information related to a transistor specified by circuit information extracted by the circuit information extraction step (hereinafter referred to as “extracted circuit information”) from a set of characteristic information related to the transistor obtained for each transistor type. An information extraction process;
Based on the extraction circuit information and the characteristic information extracted by the characteristic information extraction step, a generation step for generating library information related to the creation target cell;
A verification support program characterized by causing a computer to execute.

(Supplementary note 12) A computer-readable recording medium on which the verification support program according to Supplementary note 10 or 11 is recorded.

  As described above, the verification support apparatus, the verification support method, the verification support program, and the recording medium according to the present invention are useful for creation of an LSI logic library and logic simulation.

It is a block diagram which shows the hardware constitutions of the verification assistance apparatus concerning embodiment of this invention. It is a block diagram which shows the functional structure of the verification assistance apparatus concerning embodiment of this invention. FIG. 3 is an explanatory diagram showing stored contents of a transistor characteristic information DB shown in FIG. 2. FIG. 3 is an explanatory diagram showing storage contents of a logical library shown in FIG. 2. FIG. 3 is a block diagram illustrating a functional configuration of a transistor characteristic information creation unit illustrated in FIG. 2. It is a flowchart which shows the creation processing procedure of a transistor characteristic information creation part. FIG. 3 is a block diagram illustrating a functional configuration of a logical library creation unit illustrated in FIG. 2. It is explanatory drawing which shows the example of expansion | deployment of an inverter. It is a flowchart which shows the creation processing procedure of a logic library creation part. FIG. 3 is a block diagram illustrating a functional configuration of a delay value calculation unit illustrated in FIG. 2. It is process drawing which shows the specific example of a calculation process of a delay value calculating part. It is explanatory drawing which shows an equivalent circuit and its signal waveform. It is a chart which shows the reference table of a SPICE simulator. It is a flowchart which shows the calculation processing procedure of a delay value calculating part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 200 Verification assistance apparatus 201 Transistor characteristic information preparation part 202 Logic library preparation part 203 Delay value calculating part 210 Transistor characteristic information DB
220 logic library 501 cell circuit information acquisition unit 502 transistor detection unit 503 characteristic information calculation unit 504 storage unit 701 layout information acquisition unit 702 circuit information extraction unit 703 characteristic information extraction unit 704 connection information extraction unit 705 generation unit 1001 verification target circuit information acquisition Unit 1002 calculation target circuit information extraction unit 1003 library information extraction unit 1004 division unit 1005 delay value calculation unit 1006 output unit

Claims (5)

Cell circuit information acquisition means for acquiring circuit information about the cell for each cell;
Detecting means for detecting a transistor constituting the cell from circuit information acquired by the cell circuit information acquiring means;
Characteristic information calculating means for calculating characteristic information about the transistor detected by the detecting means;
Storage means for storing the characteristic information calculated by the characteristic information calculation means in a database for each transistor type;
A verification support apparatus comprising: Layout information acquisition means for acquiring layout information of a creation target cell;
Circuit information extraction means for extracting circuit information relating to the creation target cell from layout information acquired by the layout information acquisition means;
A characteristic for extracting characteristic information relating to a transistor specified by circuit information extracted by the circuit information extracting means (hereinafter referred to as “extracted circuit information”) from a set of characteristic information relating to the transistor obtained for each transistor type. Information extraction means;
Based on the extraction circuit information and the characteristic information extracted by the characteristic information extraction means, generation means for generating library information related to the creation target cell;
A verification support apparatus comprising: For each cell, a cell circuit information acquisition step for acquiring circuit information about the cell;
A detection step of detecting a transistor constituting the cell from the circuit information acquired by the cell circuit information acquisition step;
A characteristic information calculation step of calculating characteristic information about the transistor detected by the detection step;
A storage step of storing the characteristic information calculated by the characteristic information calculation step in a database for each transistor type;
A verification support method characterized by including For each cell, a cell circuit information acquisition step for acquiring circuit information about the cell,
A detection step of detecting a transistor constituting the cell from the circuit information acquired by the cell circuit information acquisition step;
A characteristic information calculation step for calculating characteristic information about the transistor detected by the detection step;
A storing step of storing the characteristic information calculated by the characteristic information calculating step in a database for each transistor type;
A verification support program characterized by causing a computer to execute.   A computer-readable recording medium on which the verification support program according to claim 4 is recorded.

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