JP4783712B2 - Layout design method, layout design program, and layout design apparatus - Google Patents

Description

  The present invention relates to a layout design method, a layout design program, and a layout design apparatus.

  In general, a large scale integration (LSI) is developed using a technique called hierarchical layout design in order to shorten the development period. In this method, the entire logic circuit is hierarchized for each logic module of the netlist, and processing of each hierarchical layout block (HLB) is performed in parallel, thereby shortening TAT (Turn Around Time). ing.

  Conventionally, the following logic circuit block division method is known. This method is a block division method for a logic circuit that has already been divided into blocks, and extracts cells that belong to different blocks and that have a maximum allowable delay time shorter than a predetermined value due to timing constraints between these cells. By calculating the length of each block to which these extracted cells belong, and by calculating the wiring length for connecting cells across these blocks, and by the determined wiring length When the delay time exceeds the maximum allowable delay time due to the timing constraint between these cells, a new block is generated and these cells are moved to the newly generated block (for example, the following patents) Reference 1).

JP-A-6-204337 (Claim 1)

  However, in the conventional method, since it is divided into HLB before layout, it is difficult to divide into blocks in consideration of the arrangement position and wiring property, and timing errors are likely to occur. In addition, since the top and each HLB are arranged and wired after being cut out to the HLB, it is difficult to generate the HLB terminal at an optimal position. Therefore, when a static timing analysis (STA) is performed, a timing error frequently occurs or the convergence of wiring is severe and it is necessary to review the size of the HLB. Therefore, there is a problem that TAT cannot be shortened sufficiently.

  In order to eliminate the above-described problems caused by the conventional technology, the present invention prevents timing errors caused by the position of the HLB terminal, timing errors caused by the size and arrangement position of the HLB, and deterioration of wiring properties, thereby. An object of the present invention is to provide a layout design method, a layout design program, and a layout design apparatus capable of sufficiently shortening TAT.

  In order to solve the above-described problems and achieve the object, the present inventor has made a detailed study on each process of the conventional hierarchical layout design. As a result, in the conventional hierarchical layout design method, when the period from the start of layout to the execution of the first STA is compared with the period from the execution of the first STA to the completion of the layout, the latter occupies a large proportion. It has been found. The factor is that hierarchies are performed before layout is performed, so that timing errors frequently occur when the first STA is performed. In addition, until the first STA was implemented, it was found that there was no difference between development with flat physical design data and development with hierarchical data.

  The present invention has been made based on such findings and has the following characteristics. First, a placement / wiring process and a timing analysis process are performed based on flat physical design data, and a path where a timing error has occurred (hereinafter referred to as a timing error path) is extracted. Next, the region including the extracted timing error path is divided into HLBs, and the timing constraints are divided for each HLB. Next, layout is performed for each HLB based on the divided timing constraints, and flat physical design data is generated by combining the HLB data that has already been laid out.

  According to the present invention, since the layout is started based on the flat physical design data and divided into the HLB after the placement / wiring process, the HLB terminals along the actual wiring can be generated. Therefore, a timing error due to the HLB terminal position can be prevented. In addition, it is possible to prevent timing errors due to the size and position of the HLB and deterioration of wiring properties. Furthermore, since the layout of each HLB can be processed in parallel until the layout design is completed after the HLB division, the time until timing convergence is shortened and the development period can be shortened.

  According to the layout design method, the layout design program, and the layout design apparatus according to the present invention, it is possible to prevent a timing error caused by the position of the HLB terminal, a timing error caused by the size and arrangement position of the HLB, and deterioration of the wiring property. . Therefore, the TAT can be sufficiently shortened.

  Exemplary embodiments of a layout design method, a layout design program, and a layout design apparatus according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Hardware configuration of layout design device)
First, the hardware configuration of the layout design apparatus according to the embodiment of the present invention will be described. FIG. 1 is a block diagram showing a hardware configuration of a layout design apparatus according to an embodiment of the present invention.

  In FIG. 1, the layout design apparatus is an example of a CPU 101, ROM 102, RAM 103, HDD (hard disk drive) 104, HD (hard disk) 105, FDD (flexible disk drive) 106, and a removable recording medium. FD (flexible disk) 107, display 108, I / F (interface) 109, keyboard 110, mouse 111, scanner 112, and printer 113. Each component is connected by a bus 100.

  Here, the CPU 101 controls the entire layout design apparatus. The ROM 102 stores a program such as a boot program. The RAM 103 is used as a work area for the CPU 101. The HDD 104 controls reading / writing of data with respect to the HD 105 according to the control of the CPU 101. The HD 105 stores data written under the control of the HDD 104.

  The FDD 106 controls reading / writing of data with respect to the FD 107 according to the control of the CPU 101. The FD 107 stores data written under the control of the FDD 106, or causes the layout design apparatus to read data stored in the FD 107.

  In addition to the FD 107, the removable recording medium may be a CD-ROM (CD-R, CD-RW), MO, DVD (Digital Versatile Disk), memory card, or the like. The display 108 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. As this display 108, for example, a CRT, a TFT liquid crystal display, a plasma display, or the like can be adopted.

  The I / F 109 is connected to a network 114 such as the Internet through a communication line, and is connected to other devices via the network 114. The I / F 109 controls an internal interface with the network 114 and controls data input / output from an external device. For example, a modem or a LAN adapter can be employed as the I / F 109.

  The keyboard 110 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Moreover, a touch panel type input pad or a numeric keypad may be used. The mouse 111 performs cursor movement, range selection, window movement, size change, and the like. A trackball or a joystick may be used as long as they have the same function as a pointing device.

  The scanner 112 optically reads an image and takes in the image data into the layout design apparatus. The scanner 112 may have an OCR function. The printer 113 prints image data and document data. As the printer 113, for example, a laser printer or an ink jet printer can be employed.

(Functional configuration of layout design device)
Next, a functional configuration of the layout design apparatus according to the embodiment of the present invention will be described. FIG. 2 is a block diagram showing a functional configuration of the layout design apparatus according to the embodiment of the present invention. As shown in FIG. 2, the layout design apparatus includes a flat layout unit 1, a timing error path extraction unit 2, a block division unit 3, a timing constraint division unit 4, a block layout unit 5, and a combination unit 6.

  The flat layout unit 1 performs placement / wiring processing and timing analysis processing based on flat physical design data. The timing error path extraction unit 2 extracts a path in which a timing error has occurred by the static timing analysis processing of the flat layout unit 1. The block division unit 3 divides the region including the timing error path extracted by the timing error path extraction unit 2 into HLBs.

  The timing constraint dividing unit 4 divides the timing constraint for each HLB divided by the block dividing unit 3. The block layout unit 5 performs a layout for each HLB divided by the block dividing unit 3 based on the timing constraints divided by the timing constraint dividing unit 4. The combining unit 6 combines the HLB data that has been laid out by the block layout unit 5 to generate flat physical design data.

  Specifically, the flat layout unit 1, the timing error path extraction unit 2, the block division unit 3, the timing constraint division unit 4, the block layout unit 5, and the combination unit 6 described above are, for example, the ROM 102 and the RAM 103 illustrated in FIG. 1. The control program recorded on a recording medium such as the HD 105 is executed by the CPU 101 using layout data or library data, or the function is realized by the I / F 109.

  Here, the layout data includes LSI logic design data, LSI physical design data, STA constraint data, LSI timing analysis results (STA data), and a timing error path list. The LSI logic design data is a chip top netlist including all functional modules. The LSI physical design data is physical arrangement data in the chip, and is flat and physical information after layout.

  The STA constraint data is data that is referred to at the time of placement processing considering STA. The STA constraint data describes circuit clock information, multipath, false path, and the like. The LSI timing analysis result is STA data indicating the result of the actual wiring STA process, and includes a list of path delay, slack, and error. The timing error path list is error path information output by the STA analysis program based on the LSI timing analysis result and the LSI physical design data.

  The library data includes a cell timing library and a physical cell library. The cell timing library is a unit cell and macro cell timing library. The physical cell library is an area library of unit cells and macro cells.

  The control program includes an STA analysis program, an HLB division program, an HLB combination program, and a net list generation program. The STA analysis program is a program that outputs error path information, arrangement coordinates, and slack based on the LSI timing analysis result and the LSI physical design data. The HLB division program is a program that determines and divides a division location based on the error path information and the HLB size.

  The HLB combining program is a program that combines flat HLB data and generates flat data. The netlist generation program is a program for generating a netlist after layout based on each HLB data and flat netlist updated by addition or deletion of buffers or cell swap.

(Layout design process)
Next, a processing procedure of the layout design apparatus according to the embodiment of the present invention will be described. FIG. 3 is a flowchart showing a processing procedure of the layout design apparatus according to the embodiment of the present invention. As shown in FIG. 3, first, the flat layout unit 1 starts layout design using flat physical design data, and after performing placement and wiring processing, actual wiring STA is performed (step S1). By performing this STA, a timing error path list is obtained.

  Next, the timing error path extraction unit 2 examines the location where the timing error has occurred based on the timing error path list, and analyzes the start point and end point paths listed in the list (step S2). By this analysis, a timing error path is extracted. Next, the block dividing unit 3 divides the location where the error occurred and cuts it out as an HLB (step S3). As a result, the region including the timing error path extracted by the timing error path extraction unit 2 is cut out as an HLB.

  Subsequently, the block dividing unit 3 examines the number of cells included in the HLB extracted in step S3 and converts it to the number of gates (step S4). Then, it is determined whether or not the number of gates included in the HLB is smaller than, for example, 1M gate (step S5). The reference for the number of gates is not limited to 1M gate. When it is larger than 1M gate (step S5: No), the block dividing unit 3 equally divides the HLB into two (step S6) and returns to step S4. At that time, the location where the error has occurred is examined and the size of the HLB is reviewed.

  Then, for each HLB divided into two, conversion from the number of cells to the number of gates (step S4) and determination of whether or not the number of gates is smaller than, for example, 1M gates are performed (step S5). When the number of gates of all HLBs including the timing error path becomes smaller than, for example, 1M gates (step S5: Yes), the block dividing unit 3 cuts out HLBs with the determined size (step S7). At this time, for a path extending over a plurality of HLBs, regardless of the presence or absence of a timing error, an HLB terminal is generated at the boundary between the HLBs, and the path is divided at the HLB terminal.

  Next, the timing constraint dividing unit 4 divides the timing constraint for each HLB divided by the block dividing unit 3 (step S8). For timing error paths that straddle multiple HLBs, the slack value is divided into the respective HLBs. At this time, for example, the slack value of the timing error path may be divided based on the ratio of the wiring length in each HLB of the path.

  Next, the block layout unit 5 performs layout for each HLB based on the timing constraint divided by the timing constraint dividing unit 4 (step S9). The layout of each HLB is performed in parallel. Next, it is determined whether or not each HLB satisfies the timing constraint of the STA divided for each HLB (step S10). If there is an HLB that does not satisfy the timing constraint (step S10: No), the timing ECO, that is, a circuit change for timing adjustment is repeated so as to satisfy the timing constraint for the HLB (step S11).

  If all the HLBs satisfy the timing constraints (step S10: Yes), the combining unit 6 combines the individual HLB data having been laid out into flat physical design data (step S12). Then, the actual wiring STA is performed using the newly obtained flat physical design data. The result is of course no timing error. Using this physical design data, the logical design data at the start of the layout is updated, and the process ends. Next, each step of the layout design process will be described in detail with a specific example.

  FIG. 4 is a chart showing an example of the timing error path list. Assume that the timing error path list 11 shown in FIG. 4, for example, is obtained as a result of the actual wiring STA in step S1. FIG. 5 shows an example of the timing error path extracted in step S2 based on the timing error path list shown in FIG. In FIG. 5, reference numeral 12 denotes a chip frame, and reference numeral 13 denotes a timing error path having a start point and an end point at points A and B, respectively.

  Hereinafter, the timing error path in which the start point and the end point are specified in this way is referred to as a timing error path AB using the start point and the end point. In FIG. 5, reference numerals 14, 15, 16 and 17 denote a timing error path CD, a timing error path EF, a timing error path GH and a timing error path IJ, respectively.

  FIG. 6 is a schematic diagram for explaining a method of determining a divided region when cutting out an HLB in step S3. As shown in FIG. 6, first, the region 21 of the timing error path AB13 is set as a first HLB 31. Subsequently, since the area 22 of the timing error path CD14 overlaps with the timing error path AB13, the area 22 of the timing error path CD14 is set as the first HLB 31. Subsequently, since the area 23 of the timing error path EF15 overlaps the timing error path CD14, the area 23 of the timing error path EF15 is set as the first HLB 31.

  On the other hand, since the area 24 of the timing error path GH16 does not overlap the first HLB 31, the area 24 of the timing error path GH16 is set as the second HLB 32. Subsequently, since the area 25 of the timing error path IJ17 overlaps the timing error path GH16, the area 25 of the timing error path IJ17 is set as the second HLB 32. In this way, two HLBs 31 and 32 are formed.

  FIG. 7 is a schematic diagram for explaining a method of determining a divided region when cutting out an HLB in steps S4 to S7. As shown in FIG. 7, first, for each of the first HLB 31 and the second HLB 32, the number of cells is converted into the number of gates (step S4), and it is determined whether or not the number of gates is smaller than, for example, 1M gate (step S5). ). Here, it is assumed that the number of gates of the first HLB 31 is 1 M or more and the number of second HLB 32 gates is smaller than the 1 M gate. Therefore, the second HLB 32 is determined in this area.

  For the first HLB 31, it is checked whether or not the size of the HLB can be changed from the timing error path, and the size of the first HLB 31 is changed. Here, the first HLB 31 is equally divided into two (step S6), one of which is the first HLB 33 and the other is the third HLB 34. Then, for each of the first HLB 33 and the third HLB 34, the number of cells is converted into the number of gates (step S4), and it is determined whether or not the number of gates is smaller than, for example, 1M gate (step S5).

  Here, it is assumed that the number of gates of both the first HLB 33 and the third HLB 34 is smaller than the 1M gate. Accordingly, the areas (sizes) of the first HLB 33 and the third HLB 34 are determined (step S7). When the number of gates of the first HLB 33 or the third HLB 34 is 1M or more, the division of the HLB is repeated until the number of gates becomes smaller than, for example, 1M gates. As a result of dividing the HLB in this way, the timing error path CD14 shown in FIG. 6 straddles the first HLB 33 and the third HLB 34.

  Therefore, the HLB terminal 35 is generated at the boundary portion between the first HLB 33 and the third HLB 34. Then, the timing error path CD14 is divided into a timing error path CK18 having the HLB terminal 35 as the end point K from the start point C, and a timing error path LD19 having the HLB terminal 35 as the start point L and the end point D. Similarly, for the path without the timing error (indicated by the dotted line in FIG. 7) straddling the first HLB 33 and the third HLB 34, the HLB terminal 36 is generated and the path is divided.

  8, FIG. 9, and FIG. 10 are tables showing lists obtained by dividing the timing error path list shown in FIG. 4 into the first HLB, the second HLB, and the third HLB, respectively. As shown in FIG. 8, the timing error path list 41 of the first HLB 33 includes No. 1 in the timing error path list 11 shown in FIG. 1 and the timing error path AB shown in FIG. CK of the timing error path CD indicated by 2 is included. As shown in FIG. 9, the timing error path list 42 of the second HLB 32 includes No. 1 in the timing error path list 11 shown in FIG. 4. The timing error paths GH and No. 4 shown in FIG. A timing error path IJ indicated by 5 is included.

  As shown in FIG. 10, the timing error path list 43 of the third HLB 34 has a No. in the timing error path list 11 shown in FIG. No. 2 in the timing error path CD shown in FIG. A timing error path EF indicated by 3 is included. Here, for example, based on the ratio of the wiring lengths of the timing error path CK and the timing error path LD, the slack value −1000 of the timing error path CD is equal to the slack value −400 of the timing error path CK and the timing error path LD. The slack value is divided into -600.

  FIG. 11 and FIG. 12 are schematic diagrams for explaining a method for determining a divided area when the HLB is cut out in step S7. As shown in FIG. 11, when the HLB is actually divided into HLBs, in order to prevent the logic cells 53 from being divided, the power supply wiring (strip) portions 54, that is, generally capacity cells are provided in the vertical direction of the HLBs 51 and 52. The horizontal direction is divided with the row 56 as a boundary. As shown in FIG. 12, when there is a macro 57 such as a memory at the boundary between the HLBs 51 and 52, one of the HLBs (HLB 52 in the illustrated example) absorbs the macro 57 and The boundary between the HLBs 51 and 52.

  FIG. 13 is a flowchart showing details of the processing for cutting out the HLB in step S7. As shown in FIG. 13, the flat physical design data 61 is converted into the first HLB physical design data 63 based on the divided portion data 62 that specifies the divided regions determined according to the method of determining the divided regions when the HLB is cut out. The second HLB physical design data 64 and the nth HLB physical design data 65 are divided. At that time, an HLB terminal is generated at a location where the wiring straddles (step S21). Here, n is an integer of 2 or more.

  FIG. 14 is a flowchart showing details of the process of dividing the timing constraint for each HLB in step S8. As shown in FIG. 14, first, based on the divided portion data 62, it is checked which HLB the unique name of the timing error path list 11 obtained by the first actual wiring STA belongs to (step S31). Next, it is determined whether or not a plurality of HLBs are straddled within one pass (step S32). In the case of straddling (step S32: Yes), the path is divided at the boundary of the net, that is, the HLB boundary, and the delay value is divided according to the length of each divided path (step S33). Proceed to S34.

  On the other hand, when the path does not straddle a plurality of HLBs (step S32: No), the process proceeds to step S34 as it is. In step S34, the timing constraint of the timing error path list 11 is divided for each HLB, and as the timing constraint for each HLB, the first HLB timing error path list 66, the second HLB timing error path list 67, and the nHLB timing error path. Listing 68 is obtained.

  FIG. 15 is a flowchart showing details of layout processing in each HLB in steps S9 to S11. As shown in FIG. 15, first, logical design data without a hierarchy (net list) is generated based on physical design data 63 (64, 65) divided for each HLB (step S41). Next, based on the logical design data (net list) and the timing constraints based on the physical design data 63 (64, 65) and the timing error path list 66 (67, 68) divided for each HLB, the timing is determined for each HLB. Adjustment is performed (step S42), and physical design data 69 (70, 71) satisfying the timing is obtained for each HLB.

  FIG. 16 is a flowchart showing details of the process of combining the HLB data in step S12. As shown in FIG. 16, first, physical design data 69, 70 and 71 satisfying the timing of each HLB are combined to generate flat data (step S51), and flat physical design data 72 is obtained. Then, the newly obtained flat physical design data 72 and the logical design data 73 before the division are compared, and the difference is applied to the logical design data 73 before the division to generate new logical design data (step) S52), final logic design data 74 is obtained.

  As described above, according to the embodiment, the layout is started on the basis of the flat physical design data, and is divided into HLB after the placement / wiring process, so that the HLB terminals along the actual wiring can be generated. Therefore, a timing error due to the HLB terminal position can be prevented. In addition, it is possible to prevent timing errors due to the size and position of the HLB and deterioration of wiring properties. Furthermore, since the layout of each HLB can be processed in parallel until the layout design is completed after the HLB division, the time until timing convergence is shortened and the development period can be shortened. Therefore, the TAT can be sufficiently shortened.

  The layout design method described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The program may be a transmission medium that can be distributed via a network such as the Internet.

(Additional remark 1) Timing error which extracts the path | route which a timing error generate | occur | produced by the flat layout process which performs arrangement | positioning / wiring process and timing analysis process based on the flat physical design data, and the static timing analysis process of the said flat layout process Dividing timing constraints for each of the hierarchical layout blocks divided by the path extracting step, the block dividing step for dividing the region including the timing error path extracted by the timing error path extracting step into hierarchical layout blocks, and the block dividing step And a block layout step for performing layout for each hierarchical layout block divided by the block division step based on the timing constraints divided by the timing constraint division step, Layout design method characterized by comprising a coupling step of generating physical design data flat by combining the data of the hierarchical layout blocks having undergone the layout by locking the layout step.

(Supplementary note 2) In the block division step, the number of cells included in the hierarchical layout block is converted into the number of gates, and the hierarchical layout block is divided so that the number of gates is smaller than a predetermined number. 2. The layout design method according to 1.

(Supplementary Note 3) In the timing constraint dividing step, a timing error path extending over a plurality of hierarchical layout blocks is divided into a path from the start point of the timing error path to the boundary of the hierarchical layout block, and the timing error path from the boundary to the timing error path. 3. The layout design method according to appendix 1 or 2, wherein a delay value of the timing error path is divided based on a length of each path by dividing the path up to an end point.

(Supplementary note 4) The layout design method according to supplementary note 3, wherein in the timing constraint dividing step, a terminal is generated at a boundary of a hierarchical layout block over which a timing error path extends.

(Supplementary Note 5) In the block division step, the hierarchical layout block is divided with the power supply wiring portion as a boundary in the vertical direction and the row as a boundary in the horizontal direction. Layout design method described in one.

(Supplementary note 6) The layout according to supplementary note 5, wherein, in the block dividing step, a hierarchical layout block is divided using a macro edge arranged over the power supply wiring portion or the row as a boundary. Design method.

(Additional remark 7) The layout design program characterized by making a computer perform the layout design method as described in any one of additional marks 1-6.

(Supplementary note 8) Flat layout means for performing placement / wiring processing and timing analysis processing based on flat physical design data, and timing error for extracting a path in which a timing error has occurred due to static timing analysis processing of the flat layout means A path extracting unit; a block dividing unit that divides an area including the timing error path extracted by the timing error path extracting unit into hierarchical layout blocks; and a timing constraint is divided for each hierarchical layout block divided by the block dividing unit. Timing constraint dividing means, block layout means for performing layout for each hierarchical layout block divided by the block dividing means based on the timing constraints divided by the timing constraint dividing means, Layout designing apparatus, characterized in that it comprises a coupling means for generating physical design data flat by combining the data of the hierarchical layout blocks having undergone the layout by locking the layout section.

(Supplementary note 9) The block division means converts the number of cells included in the hierarchical layout block into the number of gates, and divides the hierarchical layout block so that the number of gates is smaller than a predetermined number. 9. The layout design apparatus according to 8.

(Additional remark 10) The timing constraint dividing means includes a timing error path straddling a plurality of hierarchical layout blocks, a path from the start point of the timing error path to a boundary of the hierarchical layout block, and the timing error path from the boundary to the timing error path. The layout design apparatus according to appendix 8 or 9, wherein the layout design apparatus divides the path to the end point and divides the delay value of the timing error path based on the length of each path.

(Supplementary note 11) The layout design apparatus according to supplementary note 10, wherein the timing constraint dividing unit generates a terminal at a boundary of a hierarchical layout block over which a timing error path extends.

(Supplementary note 12) Any one of Supplementary notes 8 to 11, wherein the block dividing means divides a hierarchical layout block with a power supply wiring portion as a boundary in the vertical direction and a row as a boundary in the horizontal direction. Layout design device described in one.

(Supplementary note 13) The layout according to Supplementary note 12, wherein the block dividing means divides a hierarchical layout block with a border of a macro arranged over the power supply wiring portion or the row as a boundary. Design equipment.

  As described above, the layout design method, layout design program, and layout design apparatus according to the present invention are useful for LSI layout design, and are particularly suitable for designing LSIs by the hierarchical layout design method.

It is a block diagram which shows the hardware constitutions of the layout design apparatus concerning embodiment of this invention. It is a block diagram which shows the functional structure of the layout design apparatus concerning embodiment of this invention. It is a flowchart which shows the process sequence of the layout design apparatus concerning embodiment of this invention. It is a chart which shows an example of a timing error path list. It is a schematic diagram which shows an example of a timing error path. It is a schematic diagram explaining the determination method of a division area. It is a schematic diagram explaining the determination method of a division area. It is a graph which shows an example of the timing error path list | wrist of 1st HLB. It is a graph which shows an example of the timing error path list | wrist of 2nd HLB. It is a chart which shows an example of the timing error path list | wrist of 3rd HLB. It is a schematic diagram explaining the determination method of the division area at the time of cutting out HLB. It is a schematic diagram explaining the determination method of the division area at the time of cutting out HLB. It is a flowchart which shows the process which cuts out HLB. It is a flowchart which shows the process which divides | segments a timing constraint. It is a flowchart which shows the layout process of HLB. It is a flowchart which shows the combining process of HLB data.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flat layout part 2 Timing error path extraction part 3 Block division part 4 Timing constraint division part 5 Block layout part 6 Connection part 13, 14, 15, 16, 17, 18, 19 Timing error path 21, 22, 23, 24, 25 Area including timing error path 31, 32, 33, 34, 51, 52 HLB
35, 36 HLB terminal 54 Power supply wiring part 56 Low 57 Macro 61, 72 Flat physical design data

Claims (5)

Computer
Based on the flat physical design data, a flat layout process that performs placement / wiring processing and static timing analysis processing,
A timing error path extraction step for extracting a path in which a timing error has occurred by the static timing analysis processing of the flat layout step;
Wherein the obtained layout data by placement and routing processing flat layout step, a block dividing step of extracting including hierarchical layout blocks the timing error path extracted by the timing error path extraction step,
For each hierarchical layout blocks thus extracted to the block dividing step, and the timing constraints dividing step of dividing the timing error path,
A block layout step of laying out each hierarchical layout block after the division of the timing error paths that due to the timing constraints dividing step,
Combining hierarchical layout block data that has been laid out in the block layout step with the layout data, and updating the physical design data with the combined layout data ;
The layout design method characterized by performing . In the block dividing step, the number of cells included in the hierarchical layout block is converted into the number of gates, and the hierarchical layout block including the timing error path is extracted so that the number of gates is smaller than a predetermined number. The layout design method according to claim 1. In the timing constraint dividing step, a timing error path straddling a plurality of hierarchical layout blocks is divided into a path from the start point of the timing error path to a hierarchical layout block boundary and a path from the boundary to the end point of the timing error path. The layout design method according to claim 1, wherein the layout design method divides the delay value of the timing error path based on the length of each path. Layout design program characterized by executing the layout design method according to any one of claims 1 to 3 to the computer. Flat layout means for performing placement and wiring processing and static timing analysis processing based on flat physical design data;
A timing error path extracting means for extracting a path where a timing error has occurred by the static timing analysis processing of the flat layout means;
Wherein the obtained layout data by placement and routing processing flat layout section, a block dividing means for extracting including hierarchical layout blocks the timing error path extracted by the timing error path extraction means,
For each hierarchical layout blocks thus extracted to the block dividing unit, and timing constraints dividing means for dividing the timing error path,
A block layout device for performing layout for each hierarchy layout block after the division of the timing error paths that due to the timing constraints dividing means,
Combining means for combining hierarchical layout block data that has been laid out by the block layout means with the layout data, and generating the physical design data from the combined layout data ;
A layout design apparatus comprising:

Images