JP2013084211A - Automatic-laying wiring program for semiconductor device, automatic-laying wiring device, and automatic-laying wiring method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that conventional methods often prolong a processing time and deteriorate an area efficiency of a layout of an analog/digital mixed LSI.SOLUTION: An automatic-laying wiring program according to the present invention includes: first processing (S10) for extracting a module from circuit design information; second processing (S11) for setting module attributes representing the attributes of a circuit included in the module; third processing (S12) for generating a plurality of module shape candidates having a fixed area value and different vertical/horizontal sizes; and fourth processing (S13) for arranging a circuit element for a module shape candidate that accommodates to the shape of an upper module and generating a layout pattern. In the third processing (S13), a plurality of module shape candidates in which the height of a row or the width of a column are defined as a variation unit of the vertical/horizontal sizes are generated for the module of a first circuit attribute, and a plurality of module shape candidates in which the vertical/horizontal sizes are continuously changed are generated for the module of a second circuit attribute.

Description

  The present invention relates to a semiconductor device automatic placement and routing program, an automatic placement and routing apparatus, and an automatic placement and routing method, and more particularly to an automatic placement and routing program for a semiconductor device in which an analog circuit and a digital circuit are mixedly mounted. The present invention relates to a wiring device and an automatic placement and routing method.

  In recent years, the use of semiconductor devices in which analog circuits and digital circuits are mixed is increasing. In designing such a semiconductor device, with regard to digital circuits, the automatic placement and routing tool has been widely used, and the design time and layout area efficiency have been improved. However, with respect to analog circuits, there is a problem that development of an automatic placement and routing tool is not advanced and a long design time is required. In addition, the analog circuit has a problem that the area efficiency of the layout deteriorates due to a delay in development of the automatic placement and routing tool. Examples of a method for designing a semiconductor device including an analog circuit are disclosed in Patent Documents 1 to 3, for example.

  In Patent Document 1, the element area information is predicted for each element by referring to the element characteristic information for each circuit element. Thus, Patent Document 1 discloses a semiconductor device layout design method capable of automatically and accurately predicting the area of an analog circuit or the area of a circuit block in an analog / digital mixed integrated circuit. .

  Further, in Patent Document 2, based on a plurality of graphic data of modules and constraints such as positional relationship constraints, the layout of graphic data is calculated so as to satisfy the constraints, and a layout that better satisfies the evaluation criteria is selected from the calculated layouts To do. Thereby, in Patent Document 2, the dead space of the layout is reduced.

  In Patent Document 3, in the circuit diagram data having a hierarchical structure, the layout shape of the lower layer module is determined from the layout shape of the upper layer module. Further, in Patent Document 3, when determining the layout shape of a lower layer module, a plurality of shape candidates that fit within the upper layer layout shape are generated, and the layout shape of the lower layer module is determined from the plurality of shape candidates. select. As a result, Patent Document 3 realizes a reduction in design time and an improvement in layout area efficiency of a semiconductor device including an analog circuit.

JP 2001-338980 A JP 2005-267291 A JP 2008-299686 A

  However, in the techniques described in Patent Documents 1 to 3, a module including an analog circuit and a module including a digital circuit are mixedly mounted in the module, and the design time and area efficiency are improved for a layout in which the circuit has a hierarchical structure. There is a problem that cannot be done.

  According to one aspect of the automatic placement and routing program, automatic placement and routing apparatus, and automatic placement and routing method according to the present invention, the module shape calculation method and selection method are appropriately set according to the module attribute indicating the attribute of the circuit in the module. To do.

  According to the automatic placement and routing program, the automatic placement and routing apparatus, and the automatic placement and routing method according to the present invention, the layout data design time for the circuit diagram data in which the module including the analog circuit and the module including the digital circuit have a hierarchical structure. In addition, the area efficiency can be improved.

1 is a block diagram of an apparatus that executes an automatic placement and routing program according to a first embodiment; It is a figure which shows an example of the cell classification definition file concerning Embodiment 1. FIG. 3 is a flowchart showing an execution procedure of an automatic placement and routing program according to the first embodiment; 10 is a flowchart showing a procedure of module attribute analysis processing of the automatic placement and routing program according to the first embodiment; It is a figure for demonstrating the module attribute analyzed by the module attribute analysis process of the automatic placement and routing program according to the first embodiment. 10 is a flowchart showing a procedure when module shape analysis processing is performed on a digital module indicating an attribute of a digital circuit in the automatic placement and routing program according to the first embodiment. FIG. 3 is a schematic diagram showing a plurality of module shape candidates generated in the module shape analysis process according to the first embodiment; FIG. 3 is a schematic diagram showing selection criteria for module shape candidates selected in the module shape analysis process according to the first embodiment; FIG. 6 is a schematic diagram showing a plurality of module shape candidates selected in the module shape analysis process according to the first embodiment; 10 is a flowchart showing a procedure when module shape analysis processing is performed on an analog module indicating an attribute of an analog circuit in the automatic placement and routing program according to the first embodiment. FIG. 3 is a schematic diagram showing selection criteria for module shape candidates selected in the module shape analysis process according to the first embodiment; 1 is a schematic diagram of a layout of a semiconductor device generated by an automatic placement and routing program according to the first embodiment; It is the schematic of the layout of the semiconductor device produced | generated by the automatic place-and-route program which applied only the production | generation method of the module shape candidate with respect to an analog module. 1 is a block diagram of an automatic placement and routing apparatus according to a first embodiment. 10 is a flowchart showing details of layout processing of the automatic placement and routing program according to the second embodiment.

Embodiment 1
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The automatic placement and routing program according to the first embodiment is executed by an apparatus (for example, a computer) having a calculation unit and a storage unit. This apparatus functions as an automatic placement and routing apparatus by executing the automatic placement and routing program according to the first embodiment. Therefore, the automatic placement and routing apparatus according to the first embodiment will be described. FIG. 1 is a block diagram of an automatic placement and routing apparatus according to the first embodiment.

  As illustrated in FIG. 1, the automatic placement and routing apparatus according to the first embodiment includes a calculation unit 1, a display unit 2, an operation input unit 3, and storage units 10 to 15. In FIG. 1, a plurality of storage units are shown to clarify the input / output relationship of data. However, these storage units may be configured as a single storage unit.

  The storage unit 10 stores an automatic placement and routing program according to the first embodiment. The storage unit 11 stores an area control file. The area control file includes area restriction information that defines the upper limit value of the area of the module and dimension restriction information that defines the maximum value and the minimum value of the module size. In the initial state, the area restriction information and the dimension restriction information define, for example, the dimension of the highest layer of each module. The storage unit 12 stores circuit diagram data. The circuit diagram data includes a circuit diagram hierarchized for each module and an arrangement restriction for devices (or modules) in each layered circuit diagram.

  The storage unit 13 stores a cell type definition file. This cell type definition file includes a description that defines whether a circuit element has an attribute as an analog circuit or an attribute as a digital circuit. An example of this cell type definition file is shown in FIG. As shown in FIG. 2, in the cell type definition file, corresponding attribute information is described for each type of circuit element. For example, fet is defined as a device type for PMOS and NMOS transistors, bjt is defined as a device type for PNP transistors and NPN transistors, and a resister is defined as a device type for poly resistors. Capacitor is defined as the device type for the MOS capacitor, and standard_cell is defined as the device type for the NAND circuit.

  The storage unit 14 stores a layout pattern generated based on circuit diagram data stored in the storage unit 12. The storage unit 15 stores an error report indicating the error contents of the process when layout data that does not satisfy the standard is generated.

  The calculation unit 1 reads the automatic placement and routing program from the storage unit 10 and executes it. And the calculating part 1 implement | achieves the function as an automatic placement and routing apparatus by executing the automatic placement and routing program. The display unit 2 displays an interface for using the automatic placement and routing program. The operation input unit 3 is an interface for a user of the automatic placement and routing program to give an operation to the automatic placement and routing program.

  Subsequently, an execution procedure of the automatic placement and routing program according to the first embodiment will be described. FIG. 3 is a flowchart showing an execution procedure of the automatic placement and routing program according to the first embodiment.

  As shown in FIG. 3, the automatic placement and routing program according to the first embodiment first performs module Pcell generation processing as the first processing (step S10). In the module Pcell generation process, a module Pcell indicating a circuit arrangement unit is extracted from circuit design information (for example, circuit diagram data). The module Pcell is a cell (or module) having a variable layout dimension (in other words, a plurality of layout dimension options). For example, when the gate width or gate length of a MOS transistor (cell) is defined in the circuit diagram, the actual layout dimension of the MOS transistor can have a plurality of options. This is because the aspect ratio of the layout can be freely changed to some extent, for example, by making the gate a so-called fin structure. Thereby, the layout dimension of the module constituted by a combination of MOS transistors and the like can be freely changed to some extent.

  Subsequently, the automatic placement and routing program according to the first embodiment performs a module attribute analysis process as the second process (step S11). In the module attribute analysis process, a module attribute indicating an attribute of a circuit included in the module Pcell is set for each module Pcell. More specifically, in the module attribute analysis process, a module attribute that determines the device type of the circuit element included in the module Pcell based on the cell type definition file and indicates the attribute of the circuit in the module according to the number for each device type. Set. A more detailed operation of the module attribute analysis process will be described later.

  Subsequently, the automatic placement and routing program according to the first embodiment performs module shape analysis processing as the third processing (step S12). In the module shape analysis process, for each module, a plurality of module shape candidates having different area dimensions and different vertical and horizontal dimensions are generated. Here, in the module shape analysis process, the area value set for the module Pcell is used. For example, in the initial state, the area value given by the area control file is used as the area value of the module Pcell in the highest hierarchy. In the initial state, the area value of the lower layer module Pcell uses the area value determined by the position in the upper layer module Pcell and the number of circuit elements in the lower layer module Pcell.

  Further, in the module shape analysis process, the circuit elements arranged in the module are predetermined in size and have a characteristic of being arranged in a matrix. A plurality of module shape candidates having the height or the column width as a unit of change in vertical and horizontal dimensions are generated. Further, in the module shape analysis process, the vertical and horizontal dimensions are given to the module having the second circuit attribute indicating that the circuit element arranged in the module has a feature that the size and arrangement are arbitrarily set. A plurality of module shape candidates that change continuously are generated.

  Subsequently, in the automatic placement and routing program according to the first embodiment, layout processing is performed as the fourth processing (step S13). In the layout process, a module shape candidate that matches the shape of the upper module located in the upper layer of the processing target module is searched from a plurality of module shape candidates, and circuit elements of the module are arranged for the searched module shape candidates. Generate a layout pattern. The layout process includes an arrangement condition setting process (step S13a) and an automatic arrangement and wiring process (step S13b) in order to realize the above-described operation.

  The placement condition setting process is a process that is performed as the fourth process, and is performed as a pre-process of the automatic placement and routing process. In the arrangement condition setting process, an arrangement constraint condition that restricts the arrangement of the circuit elements of the module is set according to the module attribute. For example, in the arrangement condition setting process, when the module attribute is a first circuit attribute (for example, a digital module) mainly including circuit elements having a digital circuit attribute, an arrangement constraint condition for the digital module is given to the module. In the arrangement condition setting process, if the module attribute is a second circuit attribute (for example, an analog module) mainly including circuit elements having an analog circuit attribute, an arrangement constraint condition for the analog module is given to the module.

  The automatic placement and routing process performs the main process in the fourth process. In the automatic placement and routing process, circuit elements are placed in the module shape candidates while complying with the constraint conditions set in the placement condition setting process. Here, in the automatic placement and routing process, when the circuit element cannot be placed in the module shape candidate, the circuit element is placed in a region beyond the module shape candidate region.

  Subsequently, the automatic placement and routing program according to the first embodiment performs module area analysis processing as the fifth processing (step S14 and step S15). In the module area analysis process, it is determined whether or not there is a violation module having a layout that does not fit in the area specified by the module shape candidate in the module in which the arrangement of the circuit elements has been completed in the layout process (step S13). More specifically, as the process of step S14, the area of the module where the arrangement of the circuit elements is completed in the layout process (step S13) is calculated. Next, as the processing of step S15, whether or not there is a violation module having a layout in which the layout module does not fit in the area specified by the module shape candidate using the area of the layout module calculated in step S14. Judge. If it is determined in step S15 that there is no violation module, the layout information generated in the layout process (step S13) is output as layout pattern data.

  On the other hand, the automatic placement and routing program according to the first embodiment executes the seventh process of step S16 when it is determined that there is a violation module in the determination process of step S15. The seventh process is a loop condition determination process. In the loop condition determination process, it is determined whether to continue the loop process based on the determination result in the module area analysis process and the number of loop processes. More specifically, in the loop condition determination process, the module Pcell generation process (step S10, first process) to the layout process until the circuit element placement and routing process is completed within the shape of the module shape candidate corresponding to all modules. (Step S13, fourth process) is repeated until the limit number is reached. Then, in the loop condition determination processing, if the arrangement of the circuit elements cannot be completed within the shape of the module shape candidate corresponding to all the modules even in the limited number of times processing, an error report indicating the error content is generated, and the storage unit 15. The automatic placement and routing program according to the first embodiment performs an area control file update process (step S17) when it is determined in the loop condition determination process that the number of loops is smaller than the limit number.

  The area control file update process is performed as the sixth process. In the area control file update process, when the area of the violation module exceeds the area of the module shape candidate corresponding to the violation module, the area value used in the module shape analysis process S12 is updated with a larger value. Here, in the area control file update process, for the digital module, the area value is updated in units of row heights, and for the analog module, the area value with an arbitrary area change width and an arbitrary dimension change width. Update. In the area control file update process, the area value setting in the area control file is overwritten with the updated area value. At this time, if there is no set value related to the module to be updated in the area control file, the area value of the module to be updated is newly added.

  Here, the details of the module attribute analysis processing in step S11 will be described. FIG. 4 is a flowchart showing the procedure of module attribute analysis processing of the automatic placement and routing program according to the first embodiment.

  As shown in FIG. 4, in the module attribute analysis process, circuit diagram data is read, and a circuit element name (cell name) in the design is extracted for each module (step S20).

  Next, based on the extracted cell name and the cell type definition file, the cells in the design are classified into device types, and the number of devices is counted for each device type (step S21).

  Subsequently, the module attribute is determined for each module with reference to the number of devices of each device type for each module. More specifically, when the device type of the cell in the module is only standard_cell, the module attribute of the module is set to the digital module (steps S22 and S23). If the device type of the cell in the module is only fet, bjt, resister, or capacitor, the module attribute of the module is set to an analog module (steps S24 and S25). Further, it is determined whether or not fet, bjt, resister, capacitor, and standard_cell are mixed (step S26). If it is determined in step S26 that fet, bjt, resister, capacitor, and standard_cell are mixed, the process proceeds to step S28. On the other hand, if it is determined in step S26 that fet, bjt, resister, capacitor, and standard_cell are not mixed, that is, it is determined that there is another module belonging to a lower layer of the module, the module attribute of the module is set. A third circuit attribute (for example, a block module) is set (step S27). The block module is a module attribute set for a module including another module in a lower hierarchy than the own module in the own module.

  In step S28, the numbers of fet, bjt, resister, and capacitor used as an analog circuit and standard_cell used as a digital circuit are compared. If the number of fet, bjt, register, and capacitor is smaller than the number of standard_cell, the module attribute of the module is set to the digital module. On the other hand, when the number of fet, bjt, register, and capacitor is larger than the number of standard_cell, the module attribute of the module is set to an analog module.

  FIG. 5 is a diagram for explaining the module attributes of each module analyzed by the module attribute analysis process shown in FIG. As shown in FIG. 5, by performing the module attribute analysis process in step S11, the module attribute of the block module is set for the module having other modules in the lower hierarchy of the own module in the circuit diagram data having a hierarchical structure. Is done. The module attribute of the module belonging to the lowest layer is classified into either an analog module or a digital module.

  In the example shown in FIG. 5, circuit diagram data indicating the entire circuit diagram includes block A to block C. And about a block A, a block module is set based on having the blocks D and E in a lower hierarchy. For the block B, a digital module is set by having no other module in the lower layer and having a digital circuit. For the block C, an analog module is set by having no other module in the lower layer and having an analog circuit. For the block D, a digital module is set by having no other module in the lower layer and having a digital circuit. For block E, a block module is set based on having blocks F and G in the lower hierarchy. For the block F, an analog module is set by having no other module in the lower hierarchy and having an analog circuit. For the block G, an analog module is set by having no other module in the lower layer and having an analog circuit.

  Next, the module shape analysis process in step S12 will be described in detail. In the automatic placement and routing program according to the first embodiment, a module shape candidate generation method for a digital module is different from a module shape candidate generation method for an analog module. Therefore, in the following description, a module shape candidate generation method for a digital module and a module shape candidate generation method for an analog module will be described separately.

  First, a module shape candidate generation method for a digital module will be described. FIG. 6 is a flowchart showing a procedure when module shape analysis processing is performed on a digital module indicating an attribute of a digital circuit in the automatic placement and routing program according to the first embodiment.

  As shown in FIG. 6, in the module shape analysis process for the digital module, a plurality of module shape candidates having different module dimensions are generated with the module area being constant (step S31). At this time, in step S31, the module area is determined based on the module area data 18. The module area data 18 is data included in the area control file. The module area is calculated based on the circuit scale in the module in the initial state. However, the value of the module area data 18 may be updated in the area control file update process in step S17 of FIG. In step S31, the maximum and minimum values of the height and width that the processing target module can take in the upper layer module based on the layout data 17 are calculated, and the height and width that cannot be obtained from a plurality of module shape candidates. The module shape candidate is excluded.

  Subsequently, in the automatic placement and routing program according to the first exemplary embodiment, candidates for the number of cell arrangement rows (for example, the number of row steps) for configuring the module are extracted from the circuit diagram data (step S32). Since the number of circuit elements necessary for configuring the module is a known value, the number of candidates for the number of Row stages that can include this number of circuit elements is limited to a predetermined number.

  Subsequently, in the automatic placement and routing program according to the first embodiment, the minimum width and the maximum width of the module are calculated for each row stage number candidate extracted in step S32 (step S33). That is, in the automatic placement and routing program according to the first embodiment, for the digital module, the number of module shape candidates is further reduced by using the height of Row as a change unit. It is also possible to extract candidates for the number of arrangement columns of cells (for example, column number candidates) in step S32 and reduce the number of module shape candidates based on the column number candidates in step S33. is there. That is, it is possible to reduce the number of module shape candidates using the column width as a change unit.

  Subsequently, the automatic placement and routing program according to the first embodiment confirms whether or not all the row stage number candidates have been verified (step S34). In step S34, if there is an unverified Row stage number candidate, the process of step S32 is performed again. On the other hand, if it is determined that all the Row stage number candidates have been verified, a module shape constraint that defines that the plurality of module shape candidates selected in Step S33 are options is generated (Step S35), and the module shape constraint is generated. A module shape constraint file 19 describing the above is generated.

  Here, the module shape candidate generation procedure in step S31 will be described in more detail. First, FIG. 7 shows a schematic diagram of candidate module shapes in which the area value is constant and the vertical and horizontal dimensions are varied. As illustrated in FIG. 7, when the area value is simply constant, an infinite number of module shape candidates having different vertical and horizontal dimensions can be generated. Then, module shape candidates that do not satisfy the minimum value Wmin1 and the maximum value Wmax1 of the width that can be taken by the processing target module are excluded from the infinite number of module shape candidates. In the example shown in FIG. 7, the module shape candidate indicated by the dotted line is a module shape candidate to be discharged.

  Next, FIG. 8 shows a schematic diagram of module shape candidates including circuit elements that can constitute the module. As shown in FIG. 8, in the digital module, since the circuit elements are arranged in a matrix, the row height Trow has a constant value. In the automatic placement and routing program according to the first embodiment, the module shape candidate whose vertical dimension changes using the row height Trow as a change unit is selected as the module shape candidate used for the layout. In the example shown in FIG. 8, the module shape candidate indicated by the dotted line does not protrude from the area outside the module shape candidate, or the change unit does not become the row height Trow. Is excluded from the choices. In step S33, the minimum width Wmin2 of the module shape candidate and the maximum width Wmax2 of the module shape candidate are calculated.

  Next, FIG. 9 shows a schematic diagram of selected module shape candidates. As shown in FIG. 9, the number of selected module shape candidates is significantly smaller than the number of module shape candidates shown in FIG.

  Next, module shape analysis processing for an analog module will be described. FIG. 10 is a flowchart showing a procedure when module shape analysis processing is performed on an analog module indicating an attribute of an analog circuit in the automatic placement and routing program according to the first embodiment.

  As shown in FIG. 10, in the module shape analysis process for the analog module, a plurality of module shape candidates in which the module area is constant and the vertical and horizontal dimensions of the module continuously change are generated (step S41). At this time, in step S41, the module area is determined based on the module area data 18. The module area data 18 is data included in the area control file. The module area is calculated based on the circuit scale in the module in the initial state. However, the value of the module area data 18 may be updated in the area control file update process in step S17 of FIG. In step S41, the maximum and minimum values of the height and width that the processing target module can take in the upper layer module based on the layout data 17 are calculated, and the height and width that cannot be obtained from a plurality of module shape candidates. The module shape candidate is excluded. That is, the process in step S41 is practically the same as the process in step S31.

  Subsequently, in the automatic placement and routing program according to the first embodiment, a shape determining element for determining a module shape is extracted from circuit diagram data (step S42). The shape determining element in step S42 corresponds to the arrangement constraint included in the circuit diagram data. This arrangement restriction is generally provided in an automatic layout generation tool such as various layout attributes (constraints). Examples include device generation constraints that specify device placement directions, matching constraints that specify symmetrical placement such as differential devices, grid form constraints that specify group placement of multiple devices, and relative placement of devices. There are various things such as cell plan restrictions that stipulate.

  Subsequently, in the automatic placement and routing program according to the first embodiment, the minimum width and maximum width of the module are calculated for each shape determining element extracted in step S42 (step S43). In other words, in the automatic placement and routing program according to the first embodiment, for analog modules, the number of module shape candidates is further reduced by excluding module shape candidates from which shape determining elements cannot be placed from the choices of module shape candidates.

  Subsequently, the automatic placement and routing program according to the first embodiment confirms whether or not all shape determining elements have been verified (step S44). If there is an unverified shape determining element in step S44, the process of step S42 is performed again. On the other hand, if it is determined that all the shape determining elements have been verified, a module shape constraint is defined that defines the plurality of module shape candidates selected in step S43 as options (step S45), and module shape constraints are generated. A module shape constraint file 19 describing the above is generated.

  Here, FIG. 11 shows a schematic diagram of module shape candidates in which the shape determining elements in the module can be arranged. The example shown in FIG. 11 is an example of selecting a module shape candidate in a case where an arrangement constraint is given such that five devices M1 to M5 are arranged in one direction. In this case, in order to satisfy this restriction, it is necessary to secure at least the minimum width Wmin on one side of the module and the minimum width Hmin on the other side. Therefore, an option in which each side is less than these is not realized as an actual solution and can be excluded from the options. In the example shown in FIG. 11, the options can be limited to four cases. In step S43, the module shape candidate minimum width Wmin3 and the module shape candidate maximum width Wmax3 are calculated.

  From the above explanation, the automatic placement and routing program according to the first embodiment is adapted to the layout pattern of the upper layer by reducing the number of module shape candidates based on the layout, circuit diagram data, and module area data of the module of the upper layer. The time required for searching for the module shape can be reduced.

  Further, in the automatic placement and routing program according to the first embodiment, for a digital module mainly including a digital circuit, the height and the width of the circuit element arranged in a matrix or the width of the column are set as a change unit. A plurality of module shape candidates having different dimensions are generated. In the automatic placement and routing program according to the first embodiment, for an analog module mainly including an analog circuit, a plurality of module shape candidates whose vertical and horizontal dimensions continuously change are generated. That is, the module shape candidate is selected according to the attribute of the circuit arranged in the module. By generating module shape candidates in this way, the number of module shape candidates that can be placed with digital modules can be reduced from the number of module shape candidates for analog modules, so that the convergence of the shape of the digital module is accelerated. Can do.

  In the automatic placement and routing program according to the first embodiment, the area value is updated in consideration of the module attribute also in the area control file update process in step S17 of FIG. Thereby, in the automatic placement and routing program according to the first embodiment, it is possible to reduce the possibility that the digital module is subjected to layout processing beyond the module area after the update. That is, according to the automatic placement and routing program according to the first embodiment, the time required for layout can be reduced.

  In the automatic placement and routing program according to the first embodiment, the area efficiency of the layout can be improved by selecting the module shape candidate in consideration of the module attribute. When the same module shape candidate generation method as that of an analog module is applied to a digital module, the module dimensions are set regardless of the unit of row height or the unit of column width, resulting in useless areas. there is a possibility. Therefore, as an example, FIG. 12 shows a layout pattern of the semiconductor device generated using the automatic placement and routing program according to the first embodiment, and the semiconductor device 1 is generated by applying only the module shape candidate generation method for the analog module. The layout pattern is shown in FIG. The examples shown in FIGS. 12 and 13 are layouts for circuit diagrams having the same hierarchical structure as the hierarchical structure shown in FIG. As shown in FIG. 12, in the semiconductor device according to the first embodiment, circuits are densely arranged without causing a dead space. On the other hand, in the example shown in FIG. 13, dead space occurs due to the mismatch between the cell row height and the module shape in the block B. That is, according to the automatic placement and routing program according to the first embodiment, the layout area efficiency can be improved by classifying the placement characteristics of the circuits in the module as module attributes. When a dead space occurs, the chip area increases. However, the automatic placement and routing program according to the first embodiment also has an effect of reducing the dead space and reducing the chip area.

  In the above-described embodiment, the method of performing the layout by the automatic placement and routing program has been described. However, the layout method can also be executed by hardware having a function realized by the automatic placement and routing program. FIG. 14 is a block diagram of the automatic placement and routing apparatus according to the first embodiment.

  As shown in FIG. 14, the automatic placement and routing apparatus according to the first embodiment includes a first processing unit (for example, module Pcell generation unit 20), a second processing unit (for example, module attribute analysis unit 21), and a third processing. Section (for example, module shape analyzing section 22), fourth processing section (for example, layout processing section 23), fifth processing section (for example, module area analyzing section 24), and seventh processing section (for example, loop condition determining section 25). ), A sixth processing unit (for example, an area control file update processing unit 26).

  The module Pcell generation unit 20 executes the module Pcell generation process in step S10. The module attribute analysis unit 21 executes module attribute analysis processing in step S11. The module shape analysis unit 22 executes module shape candidate analysis processing in step S12. The layout processing unit 23 executes the layout process in step S13. The layout processing unit 23 includes an arrangement condition setting unit 23a and an automatic arrangement / wiring processing unit 23b. The arrangement condition setting unit 23a performs an arrangement condition setting process in step S13a. The automatic placement and routing processing unit 23b performs the automatic placement and routing process in step S13b. The module area analysis unit 24 performs module area analysis processing in step S14 and determination processing in step S15. The loop condition determination unit 25 performs a loop condition determination process in step S16. The area control file update processing unit 26 performs the area control file update process in step S17.

Embodiment 2
The automatic placement and routing program according to the second embodiment adds a function for properly using the automatic placement and routing tool according to the module attribute to the automatic placement and routing program according to the first embodiment. In the automatic placement and routing program according to the second embodiment, an automatic placement and routing tool selection process corresponding to the module attribute is added in the layout process (step S13) of FIG. FIG. 15 is a flowchart showing the layout processing operation in the automatic placement and routing program according to the second embodiment.

  As shown in FIG. 15, in the automatic placement and routing program according to the second embodiment, the processing of steps S51 to S54 is performed as the placement condition setting processing of step S13a. In the process of step S51, it is determined what kind of attribute the module to be processed has based on the module attribute for each module described in the module attribute description file.

  If it is determined in step S51 that the module attribute is an analog module, an analog restriction condition is set for the module (step S52). The analog constraints include, for example, device generation constraints that specify device placement directions, matching constraints that specify symmetrical placement such as differential devices, grid form constraints that specify group placement of multiple devices, There are various things such as cell plan restrictions that define the relative arrangement of devices.

  If it is determined in step S51 that the module attribute is a block module, block module constraint conditions are set for the module (step S53). The block module is a module attribute set for a module including another module in a lower hierarchy than the own module in the own module. Moreover, examples of the block module constraint conditions include a terminal layout constraint condition of a lower layer module, an inter-block wiring layout constraint condition, and the like.

  If it is determined in step S51 that the module attribute is a digital module, digital constraint conditions are set for the module (step S54). As the digital constraint condition, for example, the value of the number of Row stages used in generating the module shape candidate can be cited.

  In the automatic placement and routing program according to the second embodiment, the ninth process (for example, the automatic placement and routing tool selection process) is performed before the actual automatic placement and routing process in the automatic placement and routing process of step S13b. . In the example shown in FIG. 15, the automatic placement and routing tool is selected in steps S61 to S69, and the automatic placement and routing process is executed in step S70.

  More specifically, for an analog module, a use tool is selected in step S61 according to a description of a constraint condition or a user selection process. Then, the tool selected in step S61 is set as a tool used for automatic placement and routing processing (steps S62 and S63). The automatic placement and routing tool set in steps S62 and S63 is a tool that specializes in automatic placement and routing of analog circuits.

  For the block module, a use tool is selected in step S64 according to the description of the constraint condition or the user selection process. Then, the tool selected in step S64 is set as a tool used for automatic placement and routing processing (steps S65 and S66). The automatic placement and routing tool set in steps S65 and S66 is an automatic placement and routing tool that excels at automatic placement and routing between blocks. Note that if there is no automatic placement and routing tool between blocks for a block module, such tool selection processing may not be performed.

  For the digital module, a use tool is selected in step S67 according to the description of the constraint condition or the selection process of the user. Then, the tool selected in step S67 is set as a tool to be used for automatic placement and routing processing (steps S68 and S69). The automatic placement and routing tools set in steps S68 and S69 are good at automatic placement and routing of digital circuits.

  From the above description, in the automatic placement and routing program according to the second embodiment, a tool for performing circuit element placement and routing processing is selected according to the module attribute, and circuit element placement and routing processing is performed for each module using the selected tool. Do. By such selection processing, automatic placement and routing for each circuit can be performed by tools that are good at arrangement of analog circuits, digital circuits, and blocks. Further, by using a tool according to the circuit layout characteristics, it is possible to realize a reduction in processing time and an improvement in area efficiency.

  For example, a digital circuit usually has more circuit elements than an analog circuit. For this reason, when an automatic placement / wiring tool for analog circuits is used for a digital circuit, each circuit element of the digital circuit is arranged as an analog circuit, which requires an enormous amount of time for layout. In recent semiconductor devices, a control logic circuit for controlling an analog circuit tends to be large, so that there is a great merit in using an automatic placement and routing tool for a digital circuit for a digital circuit.

  In addition, there are many restrictions on the arrangement of circuit elements in order to obtain good circuit characteristics in analog circuits. However, many automatic placement and routing tools for digital circuits are not good at handling such arrangement restrictions. When an automatic placement and routing tool for digital circuits is used, analog circuits may not be properly laid out. In such a case, the designer needs to manually correct the layout in the correction process, and there is a problem that a lot of time is required for the process. For this reason, the advantage of using the automatic placement and routing tool for analog circuits is great for analog circuits.

  In addition, when an automatic placement and routing tool designed for an analog circuit is used, it is difficult to process the placement constraints of the digital circuit with the tool, and the layout area tends to increase. On the other hand, when an automatic placement and routing tool designed for a digital circuit is used, it is difficult to process the placement constraints of the analog circuit with the tool, and the layout area tends to increase. For these reasons as well, there are significant advantages to using automatic placement and routing tools that are used according to module attributes.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Calculation part 2 Display part 3 Operation input part 10-15 Memory | storage part 17-19, 30 File 20 Module Pcell production | generation part 21 Module attribute analysis part 22 Module shape analysis part 23 Layout processing part 23a Arrangement condition setting part 23b Automatic arrangement | positioning wiring process Unit 24 Module area analysis unit 25 Loop condition determination unit 26 Area control file update processing unit

Claims (9)

An automatic placement and routing program that is executed by a calculation unit and generates a layout pattern corresponding to the circuit design information using circuit design information read from a storage unit,
The automatic placement and routing program is:
A first process of extracting a module indicating a circuit arrangement unit from the circuit design information;
A second process for setting a module attribute indicating an attribute of a circuit included in the module for each module;
A third process for generating a plurality of module shape candidates having a constant area value and different vertical and horizontal dimensions for each module;
The module shape candidate that matches the shape of the upper module located in the upper hierarchy of the module to be processed is searched from the plurality of module shape candidates, and the circuit elements of the module are arranged with respect to the searched module shape candidate, and A fourth process for generating a layout pattern,
In the third process,
For the module of the first circuit attribute indicating that the circuit elements arranged in the module have characteristics that are pre-determined in size and arranged in a matrix, a row height or column Generating the plurality of module shape candidates having a width as a unit of change in the vertical and horizontal dimensions;
The vertical and horizontal dimensions continuously change for the module having the second circuit attribute indicating that the circuit element arranged in the module has a feature that the size and arrangement are arbitrarily set. An automatic placement and routing program for generating the plurality of module shape candidates. A fifth process for determining whether or not there is a violation module having a layout that does not fit in an area specified by the module shape candidate in the module in which the arrangement of the circuit elements is completed in the fourth process;
A sixth process for updating the area value used in the third process with a larger value if the area of the violating module exceeds the area of the module shape candidate corresponding to the violating module;
The sixth process includes
For the module showing the first circuit attribute, update the area value in row height units,
The automatic placement and routing program according to claim 1, wherein the area value is updated with an arbitrary area change width and an arbitrary dimension change width for the module indicating the second circuit attribute.   In the fifth process, the first process to the fourth process are repeated until the limit number of times is reached until the placement and routing process of the circuit element is completed within the area value of the module shape candidate corresponding to all the modules, 3. The automatic placement and routing program according to claim 2, further comprising a seventh process of generating an error report indicating an error content when all the modules do not satisfy the corresponding reference value even in the limit number of processes.   4. The automatic arrangement according to claim 1, wherein the fourth process includes an eighth process of setting an arrangement constraint condition that restricts the arrangement of the circuit elements of the module according to the module attribute. 5. Wiring program.   The fourth process includes a ninth process of selecting a tool for performing the placement and routing process of the circuit element according to the module attribute, and performing the placement and routing process of the circuit element for each module using the selected tool. The automatic placement and routing program according to claim 4, comprising: The module attribute includes a third circuit attribute set for the upper module,
The automatic placement and routing program according to claim 5, wherein the ninth process selects a tool for performing a wiring process between the modules when the module exhibits the third circuit attribute. The first circuit attribute is an attribute indicating that a circuit arranged in the module mainly includes a digital circuit,
The automatic placement and routing program according to any one of claims 1 to 6, wherein the second circuit attribute is an attribute indicating that a circuit arranged in the module mainly includes an analog circuit. A first processing unit for extracting a module indicating a circuit arrangement unit from circuit design information;
A second processing unit for setting a module attribute indicating an attribute of a circuit included in the module for each module;
A third processing unit that generates a plurality of module shape candidates having different vertical and horizontal dimensions with a constant area value for each module;
A module shape candidate that matches the shape of an upper module located in an upper layer of the module to be processed is searched from the plurality of module shape candidates, and a circuit element of the module is arranged and laid out with respect to the searched module shape candidate A fourth processing unit for generating a pattern,
In the third processing unit,
For the module of the first circuit attribute indicating that the circuit elements arranged in the module have characteristics that are pre-determined in size and arranged in a matrix, a row height or column Generating the plurality of module shape candidates having a width as a unit of change in vertical and horizontal dimensions;
The vertical and horizontal dimensions continuously change for the module having the second circuit attribute indicating that the circuit element arranged in the module has a feature that the size and arrangement are arbitrarily set. An automatic placement and routing apparatus for generating the plurality of module shape candidates. An automatic placement and routing method for generating a layout pattern corresponding to circuit design information using a program executed by an arithmetic unit,
A first step of extracting a module indicating a circuit arrangement unit from the circuit design information;
A second step of setting a module attribute indicating an attribute of a circuit included in the module for each module;
For each module, a third step of generating a plurality of module shape candidates having a constant area value and different vertical and horizontal dimensions;
The module shape candidate that matches the shape of the upper module located in the upper hierarchy of the module to be processed is searched from the plurality of module shape candidates, and the circuit elements of the module are arranged with respect to the searched module shape candidate, and A fourth step of generating a layout pattern,
In the third step,
For the module of the first circuit attribute indicating that the circuit elements arranged in the module have characteristics that are pre-determined in size and arranged in a matrix, a row height or column Generating the plurality of module shape candidates having a width as a unit of change in vertical and horizontal dimensions;
The vertical and horizontal dimensions continuously change for the module having the second circuit attribute indicating that the circuit element arranged in the module has a feature that the size and arrangement are arbitrarily set. An automatic placement and routing method for generating the plurality of module shape candidates.

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