JP2008257377A - Design method for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem of a conventional design flow: it takes a lot of design man-hours because performing layout correction by manual labor or automation technique, newly executing EM verification from LPE (Layout Parasitic Extraction), and continuing it until an EM error vanishes when EM standardized value violation occurs by performing the LPE after a layout design and executing the EM verification to a net list after the LPE. <P>SOLUTION: A wiring macrocell library E1 comprising a wiring macrocell group holding a plurality of related wiring information parameters is used for a circuit design and the layout design. A circuit design process S10 has processing for inserting a wiring macrocell (a circuit symbol) into a target net. A layout design process S30 has processing for selecting the wiring macrocell (a layout pattern) of the target net with a circuit simulation result E5 of the target net obtained by a circuit simulation process S20 and design restriction E3 such as a design condition for considering the electromigration (EM) as input. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly to a layout design technique for suppressing a failure caused by electromigration.

With the miniaturization of semiconductor processes, the possibility of causing disconnection of metal wiring called electromigration (EM) is increasing due to an increase in current density and a decrease in wiring cross-sectional area. In the conventional design flow, as shown in FIG. 31, parasitic element extraction (LPE) of layout data is performed after layout design, EM verification is performed on the net list after LPE, and the amount of current passing through each wiring and via Is measured, and it is determined whether or not the EM standard value regarding the wiring and via determined for each process rule is violated. When an EM standard value violation occurs, layout correction is performed manually or by an automated method, and EM verification is performed again from the LPE until the EM error is eliminated. As a correction method when an EM error occurs, Patent Document 1 increases the number of wiring branches so as to avoid the EM error at a location where the EM error has occurred in the verification after layout design. In Patent Document 2, the amount of current at each branch point of the wiring is calculated, and the wiring width is increased with respect to the wiring data causing the EM error.
JP-A-11-97541 (page 4-5, Fig. 1-3) JP 2002-217296 A (page 3-7, Fig. 1-3)

  In the layout design of a custom core such as an analog core or a memory core, it is necessary to perform device layout and wiring design in consideration of circuit operation characteristics and area, and the design is mainly performed manually. Necessary information is passed from the circuit designer to the layout designer, but usually only the wiring interval etc. is instructed to some signal lines so that noise etc. does not appear on the circuit diagram and signal wiring. . For this reason, it is basically difficult to design a layout in consideration of electromigration (EM), and errors are likely to occur. In order to detect an EM error, parasitic element extraction and EM verification are performed after layout design. In this case, the man-hours required for parasitic element extraction and EM verification increase as the number of elements increases. When correcting wirings and vias that violate EM, it is necessary to make corrections while considering the above-mentioned restrictions, and when the surrounding layout shape needs to be corrected, the number of correction steps increases.

  The present invention has been created in view of such circumstances, and it is possible to avoid an increase in design man-hours when performing a layout design manually, and to provide an efficient and highly reliable method for designing a semiconductor integrated circuit. It is intended to provide.

A method for designing a semiconductor integrated circuit according to the present invention includes:
From the wiring macrocell insertion step of inserting a wiring macrocell into a target net in circuit design from a wiring macrocell library having a wiring macrocell group holding a plurality of wiring information parameters related to circuit design and layout design. A circuit design process comprising:
A circuit simulation step of performing a circuit simulation using a netlist obtained by the circuit design step;
Semiconductor using the netlist, circuit simulation results of the target net obtained by the circuit simulation process, design constraints for taking into account physical phenomena that may occur on the semiconductor integrated circuit, and pre-defined process information An arrangement step for arranging circuit blocks constituting an integrated circuit, a wiring macrocell selection step for selecting a wiring macrocell of a target net in a layout design by using the wiring macrocell library, the circuit simulation result, and the design constraint as inputs; and a semiconductor integrated circuit, And a layout design process including wiring steps for wiring the circuit blocks to be configured.

  According to this semiconductor integrated circuit design method, by using a wiring macrocell that holds a plurality of wiring information parameters related to each other for circuit design and layout design, for example, a wiring pattern that can only be known after layout design is obtained. If parasitic wiring resistance, wiring capacitance, and the like are set in advance in the circuit design stage as expected or desired values as parameters of the wiring macrocell, a wiring layout pattern linked to the parameters can be generated. Therefore, it is possible to generate a wiring layout pattern that takes into account various design constraints such as timing, wiring / via EM, and power supply voltage drop, from the parameters of the wiring macrocell of the target net set in circuit design and circuit simulation results. Therefore, it is possible to create a layout that is less likely to cause errors in various design constraint verifications after layout design.

  In the semiconductor integrated circuit design method, the circuit simulation result includes current information of a target net, and the process information includes an EM standard value that is allowable current information related to wiring / via electromigration (EM), There is a mode in which the arrangement step includes a wiring macrocell selection step of selecting a wiring macrocell of a target net in a layout design by using the wiring macrocell library, the current information, and the EM standard value as input, and the wiring step.

  With this configuration, it is possible to generate a wiring layout pattern considering the EM standard value from the current net information obtained from the wiring macrocell parameter of the target net set in the circuit design and the circuit simulation result. Therefore, it is possible to create a layout in which EM errors are unlikely to occur even in EM verification after layout design.

  In the above-described semiconductor integrated circuit design method, the connection terminal distance information of the circuit block arranged in the arrangement step is used as an arrangement constraint, and wiring information considering electromigration (EM) is obtained while satisfying the arrangement restriction. is there.

  With this configuration, it is determined whether the EM-considered wiring information is satisfied when the placement constraint is satisfied. If not, the wiring information can be changed in a timely manner. It is possible to create a layout that is less likely to generate an EM error in EM verification after layout design while satisfying the requirements.

  In the above-described semiconductor integrated circuit design method, the wiring macrocell library includes wiring layer, wiring length, wiring width, wiring interval, number of vias, wiring parasitic resistance, wiring parasitic capacitance, allowable current value, current information as wiring information parameters. There is an aspect in which one or more wiring macrocells configured by any one of the connection information, the wiring layout shape, or a combination thereof are included.

  With this configuration, it is possible to control the wiring layout shape according to various parameters, so by providing parameters according to design constraints, it is possible to generate a wiring layout shape that satisfies the constraints. Become.

  In the above-described semiconductor integrated circuit design method, the wiring macrocell library fixes a wiring length in a predetermined unit (unit) length, and the wiring width is equal to or larger than a minimum wiring width and can be any of a plurality of different fixed widths or arbitrary widths. And having a wiring macrocell having one or more of a linear shape using a single wiring layer, an L shape of a bent portion of a wiring, a T shape of a branch portion of a wiring, or a cross shape. Yes (* 1).

  With this configuration, it is possible to form various wiring layout patterns composed of a single wiring layer by connecting a combination of a linear shape, an L shape, a T shape, and a cross shape. Furthermore, since the wiring length of the wiring macrocell is fixed in unit length (unit), one unit becomes a wiring grid, and a standardized wiring layout pattern can be formed.

  In the above-described semiconductor integrated circuit design method, the wiring macrocell library fixes a wiring length in a predetermined unit (unit) length, and the wiring width is equal to or larger than a minimum wiring width and can be any of a plurality of different fixed widths or arbitrary widths. One or more wiring macrocells of any of a straight line shape using a plurality of wiring layers and one or more vias connecting them, an L shape of a wiring bent portion, a T shape of a wiring branching portion, or a cross shape (* 2).

  If constituted in this way, in addition to being able to form various wiring layout patterns consisting of the above-mentioned single wiring layer, another wiring can be obtained by connecting the wiring macrocells in the present invention in combination. Since switching to a layer is possible, various wiring layout patterns composed of a plurality of wiring layers can be formed, and the degree of freedom is increased. Furthermore, since the wiring length of the wiring macrocell is fixed in unit length (unit), one unit becomes a wiring grid, and a standardized wiring layout pattern can be formed.

  In the above-described semiconductor integrated circuit design method, the wiring macrocell library fixes a wiring length in a predetermined unit (unit) length, and the wiring width is equal to or larger than a minimum wiring width and can be any of a plurality of different fixed widths or arbitrary widths. In addition, the wiring interval is set to one of a plurality of different fixed intervals or arbitrary intervals that are greater than or equal to the minimum wiring interval, and a plurality of single wiring layers are arranged in parallel and connected by the same wiring layer, or a plurality It has one or more wiring macrocells of any one of a wiring layer and a straight line connected by using one or more vias connecting them, an L shape of a bent part of a wiring, a T shape of a branching part of a wiring, or a cross. (* 3).

  With this configuration, it is possible to form various wiring layout patterns composed of a plurality of wiring layers as described above, and furthermore, by connecting the wiring macrocells according to the present invention in combination, one single unit can be formed. Since it is possible to divide the wiring of one wiring layer into a plurality of lines, it becomes possible to form various wiring layout patterns consisting of a single wiring layer and a plurality of divided wirings of a plurality of wiring layers, and further flexibility In addition, it is possible to easily cope with a process in which a wide wiring (maximum wiring width) regulation is provided in a single wiring layer. Furthermore, since the wiring length of the wiring macrocell is fixed in unit length (unit), one unit becomes a wiring grid, and a standardized wiring layout pattern can be formed.

  The wiring macrocell library has a mode in which the wiring macrocell library includes a wiring macrocell configured by combining at least any one of the above (* 1), (* 2), and (* 3).

  With this configuration, a single wiring layer mesh wiring layout pattern, a linear wiring layout pattern having a plurality of unit lengths, a linear wiring layout pattern in which a plurality of wiring layers are run in parallel to have a plurality of unit lengths, and the like are used as one wiring. It can be handled as a macro cell. As a result, the amount of data can be reduced as compared with the case where a plurality of various wiring macrocells each having a wiring length of one unit are combined to form their wiring layout pattern.

  Further, in the above-described semiconductor integrated circuit design method, in the wiring macrocell library, the wiring parasitic element of the wiring macrocell having a wiring width equal to or larger than the minimum wiring width and a plurality of different fixed widths may be applied to each wiring macrocell. The result obtained by extracting in advance by the LPE process is stored as a parameter of the wiring macrocell, and the wiring parasitic element of the wiring macrocell in which the wiring width is not less than the minimum wiring width and an arbitrary width has a plurality of wiring widths not less than the minimum wiring width. There is a mode in which a model equation that complements the wiring parasitic elements between the fixed widths is obtained from the result of the LPE process for each of the wiring macrocells having different fixed widths and stored as parameters of the wiring macrocells.

  With this configuration, it becomes possible to obtain information on the wiring parasitic elements of wiring macrocells of arbitrary widths based on the information on the wiring parasitic elements of a limited number of different fixed width wiring macrocells. It is possible to configure a wiring macrocell library with a high degree of freedom.

  In the above-described semiconductor integrated circuit design method, the placing step includes wiring connection of the net in the circuit block along a grid set in a lattice shape by a unit length defined as a wiring length of the wiring macrocell. There is a mode in which terminals are arranged.

  With this configuration, since the distance between the connection terminals takes into account the unit length grid, only the wiring macrocell library in which the wiring length is fixed at a predetermined unit (unit) length is standardized according to the unit length. It is possible to configure a layout wiring pattern. Therefore, there is an effect of suppressing variations in the finished shape of the wiring, and it is possible to reduce the number of prepared wiring macrocell libraries.

  According to the present invention, layout design in consideration of electromigration (EM) is achieved by setting wiring information desired to be handed over to layout design in circuit design, information obtained by circuit simulation, etc. as design constraints and holding them as parameters of a wiring macrocell library. Therefore, it is possible to create a layout in which an error is unlikely to occur in EM verification after layout design, and it is effective in shortening the design man-hour by suppressing the backtracking of the design.

  Hereinafter, a method for designing a semiconductor integrated circuit according to an embodiment of the present invention will be described in detail with reference to the drawings. In the following description of the drawings, the same portions are denoted by the same reference numerals and description thereof is omitted.

<Overall flow>
FIG. 1 is a diagram showing a design flow relating to a method for designing a semiconductor integrated circuit according to an embodiment of the present invention. In this design flow, in the circuit design step S10, a circuit diagram is created using the wiring macrocell library E1, the process information E2, and the design constraint E3, and a net list (circuit information) E4 is output. Here, the wiring macrocell library E1 includes a wiring macrocell group capable of setting and holding a plurality of wiring information parameters related to each other for circuit design and layout design. Process information E2 includes design rules such as the minimum wiring width and minimum wiring interval specified in advance, reliability standards such as EM standards and hot carrier standards, device specifications such as transistor characteristics and wiring sheet resistance, wiring film thickness and wiring It includes wiring structure information such as interlayer films. The design constraint E3 is for considering a physical phenomenon that can occur on the semiconductor integrated circuit specified by the designer.

  Next, in the circuit simulation step S20, a plurality of process information E2 and simulation conditions (not shown) are set for the netlist (circuit information) E4 obtained in the circuit design step S10, and then a desired circuit is obtained by circuit simulation. The characteristics are confirmed, and a circuit simulation result E5 is obtained.

  Next, in the layout design step S30, a layout is created using the netlist (circuit information) E4, circuit simulation result E5, wiring macrocell library E1, process information E2, and design constraint E3, and a layout result E6 is output.

  Next, in the verification step S40, the layout result E6 and the process information E2 are used to finally confirm whether or not the layout creation satisfying the process information such as the design rule is performed. If there is a problem, the circuit design step S10 and the layout are performed. Returning to the design process S30, redesign is performed, and if there is no problem, the process proceeds to the next process.

<Wiring macrocell library>
Here, the wiring macrocell library E1 will be described in detail. The wiring macrocell library E1 has a circuit symbol used for circuit design and a layout pattern used for layout design for each wiring macrocell, and shares a plurality of wiring information parameters with each other. The wiring information parameter is one of a wiring layer, wiring length, wiring width, wiring interval, number of vias, wiring parasitic resistance, wiring parasitic capacitance, allowable current value, current information, connection information, wiring layout shape, or a combination thereof. It consists of In addition, the wiring information parameter set in the circuit symbol used for the circuit design of the wiring macrocell becomes a design constraint such as a design condition specified by the designer in the circuit design process S10. On the other hand, the wiring information parameter of the layout pattern used for the layout design of the wiring macrocell has a parameter for selecting (generating) a layout pattern from the wiring macrocell library E1 and a wiring parameter determined by the selected (generated) layout pattern. It will be.

  For example, the wiring length and the wiring width can be set to predetermined values in the wiring information parameter within a range that satisfies a predetermined design rule. Therefore, if a predetermined symbol length and width, a wiring layout shape, a wiring layer and the number of vias constituting the shape are set as wiring information parameters in a circuit symbol used for circuit design, a layout corresponding to the wiring information parameter is set. A pattern can be immediately selected (generated).

  Further, since the parasitic element information is extracted in advance by LPE (Layout Parasitic Extraction) and stored as a wiring information parameter in the layout pattern that can be selected (generated) from the wiring macrocell library E1, the selected (generated) layout pattern. The wiring parasitic resistance value, wiring parasitic capacitance value, etc. can be easily obtained. Conversely, the relationship between the wiring length and the wiring width of the layout pattern to be selected (generated) can be obtained by setting desired parasitic element information.

<Overall concept>
Hereinafter, each step will be described in detail.

  FIG. 2 is a diagram showing the configuration of the circuit design process S10.

  In the circuit diagram creation step S11, for example, as inst 01 and inst 02 in FIG. 3 are connected, transistors and macroblocks are connected to create a circuit diagram.

  In the wiring macrocell (circuit symbol) insertion step S12, for example, a desired wiring macrocell (circuit symbol) S03 is selected and inserted from the wiring macrocell library E1 into the target net for connecting Inst01 and Inst02 in FIG. 4 to create a circuit diagram. . In the inserted wiring macrocell (circuit symbol) S03, in addition to the terminal information and connection information as the wiring information parameter 04, the parasitic element information (wiring parasitic resistance) as the design constraint E3 assumed or desired in advance at the circuit design stage by the designer. Value, wiring parasitic capacitance value) and wiring layer to be used. Note that the wiring parasitic resistance value and the wiring parasitic capacitance value, which are the parasitic element information, may be set by adding a degree of variation allowable for the designer, such as ± 10%.

  In this case, the net list (circuit information) E4 output from the circuit design step S10 is the parasitic element information (wiring parasitic resistance value, wiring parasitic capacitance value) set in the target net, as shown in the net list 05 of FIG. Therefore, in the circuit simulation step S20, circuit simulation considering parasitic element information (wiring parasitic resistance value, wiring parasitic capacitance value) becomes possible. When there is a problem in circuit characteristics in the circuit simulation, the problem is improved by updating the assumed or desired parasitic element information (wiring parasitic resistance value, wiring parasitic capacitance value). As described above, when the wiring parasitic resistance value and the wiring parasitic capacitance value are set to a degree of variation allowable as a designer, a circuit simulation is performed in consideration of the degree of variation, and the degree of variation is regarded as a circuit characteristic. If it is confirmed whether it is acceptable, the degree of freedom in selecting (generating) a layout pattern from the wiring macrocell library E1 increases.

  Next, FIG. 5 is a diagram showing the configuration of the layout design step S30.

  The placement step S31, the wiring macrocell (layout pattern) selection step S32, and the wiring step S33 are performed using the netlist (circuit information) E4 and the process information E2 obtained in the circuit design process S10. Note that the placement step S31, the wiring macrocell (layout pattern) selection step S32, and the wiring step S33 can be performed in any order as necessary.

  In the placement step S31, for example, as shown by Inst01 and Inst02 in FIG. 10, a layout cell such as a transistor or a macroblock is placed at a desired position, and a wiring path 11 indicated by a broken line is used using a conventional wiring path search algorithm. obtain.

  In the wiring macrocell (layout pattern) selection step S32, for example, as shown in FIG. In the wiring macro cell wiring information parameter 04, terminal information, connection information, wiring parasitic resistance values and wiring parasitic capacitance values, which are design constraints E3 reflecting the circuit simulation result E5, and wiring layer information to be used are set. Yes. For the wiring path segments 07a, 07b, and 07c in the wiring path 11, wiring lengths L07a, L07b, and L07c are obtained, respectively. Based on the wiring lengths L07a, L07b, L07c and wiring parasitic element information obtained from the LPE (parasitic element extraction) held by the wiring macrocell, the wiring width W07a satisfying the wiring parasitic resistance value and the wiring parasitic capacitance value is satisfied. , W07b and W07c are selected (generated) as wiring macrocells (layout patterns) P08a, P08b and P08c. And the wiring pattern P08 which combined them is comprised, and it wires as shown in FIG.

  In the above description, the case of selecting (generating) a wiring macrocell (layout pattern) composed of only the first wiring layer has been described. However, the present invention is not limited to this. For example, as shown in FIGS. 13 to 15, a wiring macrocell (layout pattern) including other wiring layers including the second wiring layer and vias connecting different wiring layers is prepared as a wiring macrocell library E1. . With this configuration, even when a different net wiring pattern 06 exists on the wiring path 11, it is possible to flexibly cope with the change of wiring.

  In the wiring step S33, when the net to be wired does not set the design constraint E3, wiring is performed using the conventional wiring algorithm.

  The wiring macrocell library E1 has the characteristics described above. Therefore, for design constraints such as design conditions specified by the designer, for example, wiring resistance and wiring capacitance that are parasitic on wiring patterns that were not known after layout design are assumed or desired in advance at the circuit design stage. Set and store parameters for wiring macrocell. By doing so, it is possible to select (generate) a wiring layout pattern linked to the parameter. Therefore, according to the above design flow, the wiring macrocell library E1 can create a layout in which the design constraint E3 considered in the circuit design step S10 is taken into consideration in the layout design step S30 together with the circuit simulation result E5. As a result, in the result of the verification step S40, it is possible to suppress the backtracking of the design.

  In the above description, the design method of the semiconductor integrated circuit considering the circuit characteristics with the wiring parasitic resistance and the wiring parasitic capacitance in the signal wiring as design constraints has been described as an example. However, the present invention is not limited to this. For example, the power supply wiring may be the target net, or it can be applied as a semiconductor integrated circuit design method considering wiring / via electromigration (EM), power supply voltage drop, crosstalk noise, etc. due to design constraints. is there.

<EM consideration>
In the following, a method for designing a semiconductor integrated circuit particularly considering EM will be described in detail.

  FIG. 6 is a diagram showing a design flow relating to a method for designing a semiconductor integrated circuit in consideration of EM in the embodiment of the present invention. The design flow shown in FIG. 1 includes a layout design process S50 considering EM, an EM verification process S60, process information E2 ′ including an EM standard value, a circuit simulation result E5 ′ including current information, The layout result E6 ′ considering EM is different. Since the circuit design process S10 and the circuit simulation process S20 are as described above, description thereof will be omitted.

  In the design flow shown in FIG. 6, process information E2 ′ including the EM standard value is used in the circuit design step S10. In the layout design process S50 considering EM, the circuit simulation result E5 ′ including the current information obtained in the circuit simulation process S20, the net list (circuit information) E4, the wiring macrocell library E1, and the design constraint E3 are used. A layout is created, and a layout result E6 ′ considering EM is output.

  Next, in the EM verification step S60, a layout that satisfies the process information E2 ′ including the EM standard value is created using the layout result E6 ′ considering the EM and the process information E2 ′ including the EM standard value. Finally check whether or not. If there is a problem, the circuit design process S10 and the layout design process S50 in consideration of the EM are returned to perform redesign. If there is no problem, the process proceeds to the next process.

  Hereinafter, the processing flow of the layout design process S50 considering EM will be described in detail with reference to FIG.

  In step S51, from the net list (circuit information) E4 obtained in the circuit design process S10, the target net to be processed inserts a wiring macrocell in the circuit design process S10 and holds the wiring information parameter, that is, performs EM consideration. Judge whether it is a target net.

  If it is not an EM consideration target net, the process proceeds to the placement process S52, and a layout cell such as a transistor or a macro block is placed at a desired position using the net list (circuit information) E4 obtained in the circuit design step S10 as in the past. Arrangement position information E7 such as the coordinates is obtained.

  In the wiring route search process S53, the wiring route information E8 of the terminal to be connected as before is obtained using the arrangement position information E7.

  In the wiring process S54, wiring is performed as usual using the wiring route information E8, and a layout result E6 ′ (not particularly considering EM for this net) is obtained.

  On the other hand, if it is determined in step S51 that the net is an EM consideration target, the process proceeds to the EM allowable minimum wiring width / via number calculation process S55, and the circuit simulation result E5 ′ including the current information obtained in the circuit simulation process S20 is obtained. Using the EM standard value E22, allowable minimum wiring width information E9 and allowable minimum via number information E10 are obtained. Regarding the allowable minimum wiring width and the allowable minimum number of vias here, when the EM standard value E22 is different for each wiring layer or for each via layer, the allowable minimum wiring width and the allowable minimum number of vias for the wiring layer and the via layer are obtained. deep. For example, assuming that the wiring layer to be used is the first wiring layer, the allowable current density of the first wiring layer is 1.0 [mA / μm] as the EM standard value E22, and the target is the circuit simulation result E5 ′ including current information. In the case where the current value of the net is 0.4 [mA], an allowable minimum wiring width Wb = 0.4 [μm] is obtained.

  In the wiring width / via number / wiring length determination processing S56, the wiring width / via number / wiring length information in the target net using the allowable minimum wiring width information E9, the allowable minimum via number information E10, the design constraint E3, and the wiring macrocell library E1. E11 is obtained. For example, assuming that the wiring layer to be used is the first wiring layer as described above, the sheet resistance value of the first wiring layer is 0.1 [ohm / sheet] as the design rule E21, and the wiring macrocell library E1 is inserted into the target net. In the case where 10 [ohm] is held as the design constraint E3 in the wiring resistance value of the wiring information parameter of the formed wiring macrocell, first, the desired wiring width W is determined to be equal to or larger than the allowable minimum wiring width Wb. Here, it is assumed that W = 0.5 [μm]. Next, since the relational expression of wiring resistance value = sheet resistance value × wiring length L / wiring width W holds, wiring length L = 50 [μm] is obtained.

  In the wiring macrocell selection processing S57, wiring pattern information E12 is obtained using the wiring width / via number / wiring length information E11 and the wiring macrocell library E1. For example, as shown in FIG. 29, assuming that the wiring layer to be used is the first wiring layer in the same manner as described above, the results of wiring width W = 0.5 [μm] and wiring length L = 50 [μm] are obtained. In this case, the wiring macrocell (layout pattern) P12a, P13a, P13b, and P13c stored in the wiring macrocell library E1 in segment units in the desired wiring shape pattern while maintaining the wiring length L depending on the wiring width W and the Manhattan distance. And P14a, P14b, and P14c are selected (generated), and desired wiring shape patterns P13, P14, and P15 are configured.

  Further, the layout process S58 places (connects) layout cells such as transistors and macroblocks so as to match the wiring shape pattern (for example, P13) as the wiring pattern information E12, and the layout result in consideration of EM as shown in FIG. E6 'is obtained.

  According to this embodiment, it is possible to define a wiring resistance value as a design constraint desired by the designer, and to create a layout in consideration of the EM while keeping the design constraint.

<EM consideration>
In addition, another example will be specifically described regarding a method of designing a semiconductor integrated circuit particularly considering EM.

  Since the design flow regarding the design method of the semiconductor integrated circuit in consideration of EM is the same as FIG. 6 used in the above description, the description is omitted. The difference from the example described above is that layout design is performed in consideration of EM while satisfying the design constraints while maintaining the arrangement constraints of transistors and macro cell blocks as much as possible. Therefore, since the processing flow of the layout design process S50 considering the EM shown in FIG. 6 is different, description will be made with reference to FIG.

  In the placement process S61, a layout cell such as a transistor or a macroblock is placed at a desired position using the net list (circuit information) E4 obtained in the circuit design step S10 as in the past, and placement position information E7 such as its coordinates is used. obtain.

  In the wiring route search processing S62, the wiring position information E8 of the terminals to be connected as usual and the connection terminal distance information (temporary wiring length) E13 are obtained using the arrangement position information E7.

  In the target net determination process S63 after the wiring route search process S62, the target net to be processed inserts a wiring macrocell in the circuit design step S10 and holds the wiring information parameter, that is, the target net to be considered in EM. Determine whether or not.

  If the net is not an EM consideration target net, the process proceeds to the wiring process S64, and wiring is performed as usual using the wiring path information E8, and a layout result E6 ′ (EM is not particularly considered for this net) is obtained.

  On the other hand, if it is determined in step S63 that the net is an EM consideration target, the process proceeds to provisional wiring width calculation processing S65, and is connection terminal distance information (temporary wiring length) E13 and process information E2 ′ including the EM standard value. Provisional wiring width information E14 is obtained using the design rule E21, the design constraint E3, and the wiring macrocell library E1. For example, assuming that the wiring layer to be used is the first wiring layer, the temporary wiring length La based on the connection terminal distance information (temporary wiring length) E13 is 75 [μm], and the sheet resistance value of the first wiring layer is 0 as the design rule E21. .1 [ohm / sheet], a case where 10 [ohm] is held as the design constraint E3 in the wiring resistance value of the wiring information parameter of the wiring macrocell inserted into the target net as the wiring macrocell library E1 will be explained. Since the relational expression of width Wa = temporary wiring length La × sheet resistance value / wiring resistance value is established, provisional wiring width Wa = 0.75 [μm] is obtained.

  In the EM allowable minimum wiring width / via number calculation process S66, the circuit simulation result E5 ′ including the current information obtained in the circuit simulation step S20 and the EM standard value E22 which is the process information E2 ′ including the EM standard value. Is used to obtain allowable minimum wiring width information E9 and allowable minimum via number information E10. Regarding the allowable minimum wiring width and the allowable minimum number of vias here, when the EM standard value E22 is different for each wiring layer or for each via layer, the allowable minimum wiring width and the allowable minimum number of vias for the wiring layer and the via layer are obtained. deep. For example, assuming that the wiring layer to be used is the first wiring layer, the allowable current density of the first wiring layer is 1.0 [mA / μm] as the EM standard value E22, and the target is the circuit simulation result E5 ′ including current information. In the case where the current value of the net is 0.4 [mA], an allowable minimum wiring width Wb = 0.4 [μm] is obtained.

  Next, in the comparison process S67, the temporary wiring length / temporary wiring width information E15 is obtained using the temporary wiring width information E14 and the allowable minimum wiring width information E9. For example, when the temporary wiring width Wa = 0.75 [μm] is obtained as the temporary wiring width information E14 and the allowable minimum wiring width Wb = 0.4 [μm] is obtained as the allowable minimum wiring width information E9, Wa ≧ Wb is established. Therefore, the temporary wiring width Wa obtained based on the wiring resistance value as the design constraint and the temporary wiring length La as the layout constraint satisfies the EM standard value while satisfying the design constraint.

  Next, in the temporary wiring processing S68, the wiring route information E8, the temporary wiring length / temporary wiring width information E15, and the information are additionally stored in the wiring information parameter, and the temporary wiring process is performed by wiring using the layout pattern of the desired wiring macrocell. A wiring result E16 is obtained.

  Next, in the wiring macrocell selection process S69, the temporary wiring result E16, the allowable minimum wiring width information E9, the allowable minimum via number information E10, and the layout result E6 ′ in consideration of EM are obtained using the wiring macrocell library E1. For example, if the temporary wiring result E16 is a desired result, the layout result may be output as it is. However, it is necessary to change the wiring width within a range satisfying the EM standard value or to change the wiring using another wiring layer. If there is, the wiring information parameter held by the wiring macrocell is changed so as to satisfy the allowable minimum via number information E10, a new layout pattern of the wiring macrocell is newly selected, and the layout result is output.

<Wiring macrocell library>
Next, a wiring macrocell library E1 ′ in which the wiring length of each wiring macrocell is fixed in a predetermined unit (hereinafter referred to as a unit) will be described.

  19 to 22 show an example of a wiring macrocell (layout pattern) in the wiring macrocell library E1 ′. The wiring length is fixed at a predetermined unit length Lu, and the wiring width Wu is a plurality of different fixed widths (Wu1, Wu2,...) That are equal to or larger than the minimum wiring width of a preset design rule. The wiring macrocell (layout pattern) includes a straight line shape (a1 to a4) using a single wiring layer, an L shape (b1 to b4) of a bent portion of the wiring, and a T shape (c1 to c4) of a branch portion of the wiring. The wiring layout has a cross shape (d1 to d4).

  23 to 26 also show an example of a wiring macrocell (layout pattern) in the wiring macrocell library E1 ′. The wiring length is fixed at a predetermined unit length Lu, and the wiring width Wu is a plurality of different fixed widths (Wu1, Wu2,...) That are equal to or larger than the minimum wiring width of a preset design rule. The wiring macrocell (layout pattern) includes a plurality of wiring layers and a straight line shape (a5 to a8) using one or more vias connecting them, an L shape (b5 to b8) of a bent portion of the wiring, and a branching portion of the wiring T-shaped (c5 to c10) and cross (d5 to d9) wiring layout shapes.

  FIG. 27 shows an example of a wiring macrocell (layout pattern) in the wiring macrocell library E1 ′. The wiring length is fixed at a predetermined unit length Lu, and the wiring width Wu is a plurality of different fixed widths (Wu1, Wu2,...) That are equal to or larger than the minimum wiring width of a preset design rule. Further, the wiring interval Su has a plurality of different fixed widths (Su1, Su2,...) That are equal to or larger than the minimum wiring interval of a preset design rule. In the wiring macrocell (layout pattern), a plurality of single wiring layers are arranged in parallel and connected by the same wiring layer, or a plurality of wiring layers and a straight line (a9 to a11) using one or more vias connecting them. ) Have a wiring layout shape.

  FIG. 28 shows an example in which wiring macrocells (layout patterns) in the wiring macrocell library E1 ′ described above are combined. The wiring macrocell (layout pattern) has a single wiring layer mesh shape (e1) wiring layout shape using a plurality of wiring macrocells.

  In the design flow using the wiring macrocell library E1, a change is made in addition to the wiring macrocell library E1 that a wiring macrocell library E1 ′ in which the wiring length of each wiring macrocell is fixed at a predetermined unit length is also used. By using the layout pattern (for example, P10a, P10b, P10c) of the wiring macrocell library E1 ′ preferentially in combination, it becomes possible to wire between transistors and macroblocks as shown in FIG.

  As shown in FIG. 16, when the wiring path 11 cannot be followed due to the predetermined unit length of the wiring macrocell library E1 ′, the path may be changed while maintaining the Manhattan distance in the wiring path 11.

  Further, when the wiring connection is not completed only by the wiring macrocell library E1 ′ due to the arrangement positional relationship of the transistors and macroblocks, the wiring macrocell library E1 (for example, P10d) may be complemented as shown in FIG.

  In addition, each wiring macrocell performs LPE processing in advance, extracts parasitic components such as wiring parasitic resistance, wiring parasitic capacitance, and parasitic inductance as parasitic element information, and stores them as wiring information parameters of each wiring macrocell. As a result, the parasitic element information of the wiring macrocell is accurate even for a complicated layout shape such as a wiring macrocell using a plurality of wiring layers and one or more vias connecting them, or an L-shape, T-shape, or cross shape. Since it can be held, the parasitic element information of the entire wiring layout pattern obtained by combining these wiring macrocells can be easily obtained.

  The example of the wiring macrocell library E1 ′ in which the wiring width is a plurality of different fixed widths (Wu1, Wu2...) And the wiring interval is a plurality of different fixed widths (Su1, Su2...) Has been described above. It is not a thing. For example, from the parasitic element information obtained by LPE for these different fixed value shapes, a model formula that complements the parasitic element information between the fixed values is obtained and stored as the wiring information parameter of the wiring macrocell. As a result, a more flexible wiring macro cell library corresponding to an arbitrary wiring width and wiring interval exceeding the minimum wiring width and the minimum wiring interval of the preset design rule can be provided.

  It should be noted that when obtaining the model formula, naturally, it is possible to further improve the accuracy by obtaining from the parasitic element information with respect to more fixed value shapes. However, in consideration of the number of cells to be prepared, the number of LPE processing steps, etc., for example, wiring It is desirable to consider the trade-off with accuracy, such as using a model formula with a plurality of different fixed values for the interval.

  As a result, it is possible to configure a standardized layout wiring pattern according to the unit length in addition to performing layout design in consideration of design constraints while maintaining the arrangement constraints of transistors and macro cell blocks as much as possible. It is also effective in suppressing variations in the finished shape.

  In addition, since the wiring macrocell library E1 'prepares L-shape, T-shape, cross shape, etc. considering bending and branching in the wiring shape pattern, the parasitic element information of that portion is obtained in advance by LPE with higher accuracy and stored. The parasitic element information of the wiring pattern obtained by combining these wiring shape patterns can be obtained relatively easily.

  In addition, since the wiring macrocell library E1 is used to supplement a wiring path that is less than the unit length, the number of wiring macrocells to be prepared can be reduced.

<Arrangement process>
Next, the wiring length of the wiring macrocell library E1 ′ is fixed to a predetermined unit length, and at the same time, the wiring connection points (terminals) of the target net of the macroblock along the grid set by the unit length. ) Will be described.

  In the design flow using the placement processes S52 and S61, the replacement of the placement processes S52 and S61 and the wiring route search processing 53 and S62 with the placement processing and the wiring route search processing in consideration of the unit length grid is a change. By doing so, it is possible to wire between macroblocks as shown in FIG.

  As a result, the wiring route information E8 and the connection terminal distance information (temporary wiring length) E13 take into account the unit length grid, so that only the wiring macrocell library E1 ′ forms a standardized layout wiring pattern according to the unit length. Therefore, the effect of suppressing variation in the finished shape of the wiring is further increased, and the wiring can be completed with only the wiring macrocell library E1 ′, so that the wiring macrocell library E1 can be deleted.

  Since the semiconductor integrated circuit design method of the present invention has a wiring macrocell, layout design can be performed in consideration of design constraints and circuit simulation results at the circuit design stage, and therefore, it is possible to suppress the backtracking of the design. In particular, it is useful in the design of a semiconductor integrated circuit in which electromigration should be considered.

7 is a flowchart showing a processing procedure of a method for designing a semiconductor integrated circuit in an embodiment of the present invention. The figure which shows the structure of the circuit design process in embodiment of this invention. Example of a circuit diagram in an embodiment of the present invention Example of circuit diagram in which wiring macro cell (circuit symbol) is inserted in the embodiment of the present invention The figure which shows the structure of the layout design process in embodiment of this invention. The flowchart which shows the procedure of the process of the design method of the semiconductor integrated circuit in consideration of EM in embodiment of this invention in embodiment of this invention The flowchart which shows the procedure of the process of the layout design process in consideration of EM in embodiment of this invention The flowchart which shows the procedure of another process of the layout design process in consideration of EM in embodiment of this invention Example of netlist in the embodiment of the present invention Explanatory drawing of the operation example of the arrangement | positioning step of the layout design process in embodiment of this invention Explanatory drawing of the operation example of the wiring macrocell (layout pattern) selection step of the layout design process in the embodiment of the present invention FIG. 6 is a layout result example diagram using a wiring pattern in which wiring macrocells (layout patterns) made of the first wiring layer in the embodiment of the present invention are combined. Explanatory drawing of the operation example of the arrangement step of the layout design process in the embodiment of the present invention (with different net wiring patterns) Explanatory drawing of the operation example of the wiring macrocell (layout pattern) selection step in the layout design process in the embodiment of the present invention (with wiring patterns of different nets) Example layout results using wiring patterns combining wiring macrocells (layout patterns) in the embodiment of the present invention (with wiring patterns of different nets) FIG. 6 is a layout result example diagram (with different net wiring patterns) in which the wiring route is changed in the embodiment of the present invention. Example layout results using a wiring pattern in which a wiring macrocell (layout pattern) having a unit length and a wiring macrocell (layout pattern) having no unit length are combined in the embodiment of the present invention (with wiring patterns of different nets) Example layout result using a wiring pattern in which only wiring macrocells (layout patterns) having unit lengths in the embodiment of the present invention are combined (with wiring patterns of different nets) Illustration of wiring macrocell (layout pattern) in an embodiment of the present invention Illustration of wiring macrocell (layout pattern) in an embodiment of the present invention Illustration of wiring macrocell (layout pattern) in an embodiment of the present invention Illustration of wiring macrocell (layout pattern) in an embodiment of the present invention Illustration of wiring macrocell (layout pattern) in an embodiment of the present invention Illustration of wiring macrocell (layout pattern) in an embodiment of the present invention Illustration of wiring macrocell (layout pattern) in an embodiment of the present invention Illustration of wiring macrocell (layout pattern) in an embodiment of the present invention Illustration of wiring macrocell (layout pattern) in an embodiment of the present invention Example of configuration combining wiring macrocells (layout pattern) in the embodiment of the present invention Illustration of wiring shape pattern combining wiring macrocell (layout pattern) considering EM in the embodiment of the present invention Exemplary layout results considering EM in the embodiment of the present invention Flow chart showing design flow procedure in the prior art

Explanation of symbols

04 Wiring information parameter E1 Wiring macrocell library E2 Process information E2 'Process information including EM standard value E21 Design rule E22 EM standard value E3 Design constraint E4 Net list (circuit information)
E5 Circuit simulation result E5 'Circuit simulation result including current information E6 Layout result E6' Layout result in consideration of EM E7 Arrangement position information E8 Wiring path information E9 Allowable minimum wiring information E10 Allowable minimum via number information E11 Wiring width and number of vias・ Wiring length information E12 Wiring pattern information E13 Connection terminal distance information (temporary wiring length)
E14 Temporary Wiring Width Information E15 Temporary Wiring Length / Temporary Wiring Width Information E16 Temporary Wiring Result S10 Circuit Design Process S11 Circuit Diagram Creation Step S12 Wiring Macro Cell (Circuit Symbol) Insertion Step S20 Circuit Simulation Process S30 Layout Design Process S31 Arrangement Step S32 Wiring Macro Cell (Layout Pattern) Selection Step S33 Wiring Step S40 Verification Process S50 Layout Design Process Considering EM S51 Target Net Judgment Process S52 Placement Process S53 Placement Route Search Process S54 Wiring Process S55 EM Allowable Minimum Wiring Width / Via Number Calculation Process S56 Wiring Width Via number / wiring length determination processing S57 Wiring macro cell selection processing S58 Placement processing S60 EM verification process S61 Placement processing S62 Placement route search processing S63 Target net determination processing S64 Wiring processing S65 Temporary wiring width calculation processing S66 EM allowable minimum wiring width / via number calculation processing S67 Comparison processing S68 Temporary wiring processing S69 Wiring macrocell selection processing

Claims (10)

From the wiring macrocell insertion step of inserting a wiring macrocell into a target net in circuit design from a wiring macrocell library having a wiring macrocell group holding a plurality of wiring information parameters related to circuit design and layout design. A circuit design process comprising:
A circuit simulation step of performing a circuit simulation using a netlist obtained by the circuit design step;
Semiconductor using the netlist, circuit simulation results of the target net obtained by the circuit simulation process, design constraints for taking into account physical phenomena that may occur on the semiconductor integrated circuit, and pre-defined process information An arrangement step for arranging circuit blocks constituting an integrated circuit, a wiring macrocell selection step for selecting a wiring macrocell of a target net in a layout design by using the wiring macrocell library, the circuit simulation result, and the design constraint as inputs; and a semiconductor integrated circuit, A method for designing a semiconductor integrated circuit, comprising: a layout design process comprising wiring steps for wiring circuit blocks to be configured.   The circuit simulation result includes current information of a target net, and the process information includes an EM standard value that is allowable current information regarding wiring / via electromigration. The placement step, the wiring macrocell library, and the current information 2. The semiconductor integrated circuit design method according to claim 1, further comprising: a wiring macrocell selection step of selecting a wiring macrocell of a target net in a layout design using the EM standard value as an input, and the wiring step.   3. The method for designing a semiconductor integrated circuit according to claim 2, wherein the connection terminal distance information of the circuit block arranged in the arrangement step is used as an arrangement constraint, and wiring information considering electromigration is obtained while satisfying the arrangement constraint.   The wiring macrocell library is one of wiring layer, wiring length, wiring width, wiring interval, number of vias, wiring parasitic resistance, wiring parasitic capacitance, allowable current value, current information, connection information, wiring layout shape as wiring information parameters. 4. The method for designing a semiconductor integrated circuit according to claim 1, further comprising one or more wiring macrocells configured by a combination thereof.   The wiring macrocell library fixes a wiring length in a predetermined unit (unit) length, sets the wiring width to a plurality of different fixed widths or arbitrary widths that are equal to or larger than the minimum wiring width, and sets a single wiring layer. 5. The method of designing a semiconductor integrated circuit according to claim 4, comprising one or more wiring macrocells of any one of a linear shape, an L shape of a bent portion of wiring, a T shape of a branch portion of wiring, and a cross shape.   The wiring macrocell library fixes a wiring length by a predetermined unit (unit) length, and sets a wiring width by a plurality of different fixed widths or arbitrary widths that are equal to or larger than the minimum wiring width, and a plurality of wiring layers and those 5. The wiring macrocell according to claim 4, wherein the wiring macrocell has one or more wiring macrocells of any one of a straight line shape using one or more vias for connecting the wires, an L shape of a bent portion of the wiring, a T shape of a branching portion of the wiring, and a cross shape. A method for designing a semiconductor integrated circuit.   Furthermore, the wiring macrocell library fixes the wiring length in a predetermined unit (unit) length, sets the wiring width to a minimum wiring width or any of a plurality of different fixed widths or arbitrary widths, and further minimizes the wiring interval. More than one wiring interval is set at one of a plurality of different fixed intervals or arbitrary intervals, and a plurality of single wiring layers are arranged in parallel and connected by the same wiring layer, or a plurality of wiring layers and one or more connecting them 5. The semiconductor integrated circuit according to claim 4, further comprising one or more wiring macrocells of a straight line connected using vias, an L shape of a bent portion of wiring, a T shape of a branching portion of wiring, or a cross shape. Design method.   A method of designing a semiconductor integrated circuit, wherein the wiring macrocell library includes a wiring macrocell configured by a combination of at least any one of claims 5, 6, and 7.   In the wiring macrocell library, the wiring parasitic element of the wiring macrocell whose wiring width is equal to or larger than the minimum wiring width and has a plurality of different fixed widths is obtained by previously extracting each wiring macrocell by LPE processing. The wiring parasitic element of the wiring macrocell, which is stored as a parameter of the wiring macrocell and whose wiring width is equal to or larger than the minimum wiring width, corresponds to each of the wiring macrocells having a wiring width equal to or larger than the minimum wiring width and a plurality of different fixed widths. 5. The method of designing a semiconductor integrated circuit according to claim 4, wherein a model formula for complementing a wiring parasitic element having a fixed width is obtained from a result of the LPE process and stored as a parameter of the wiring macrocell.   5. The semiconductor according to claim 4, wherein in the arranging step, the wiring connection terminals of the net in the circuit block are arranged along a grid set in a lattice shape by a unit length defined as a wiring length of the wiring macrocell. Integrated circuit design method.

Images