JP2001135726A - Semiconductor integrated circuit and layout method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent wiring from becoming impossible, rearranging, and further increasing in the number of rearrangements in an automatic wiring layout of an integrated circuit using a basic cell. SOLUTION: Cells 3, 8, 12, 17, each of which has a small number of input/ output terminals with respect to the width of the cell (which has a complex inner configuration such as a flip-flop, full adder or the like) are disposed directly under a reinforcing power wiring 1 (or a ground wiring). This reduces the number of terminals, which become a cause for the concentration of wirings and hence reduces time and area necessary for arranging the wirings.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit in which a basic cell base using multilayer wiring is integrated, and a layout method.

[0002]

2. Description of the Related Art Conventionally, in an automatic layout and wiring layout of an integrated circuit using a basic cell, in a process of three metal layers or less, a reinforcing power supply / ground is provided in a wiring layer higher than the wiring used in the basic cell. Wiring is difficult, and the area is increased due to the space required for the reinforcing power / ground wiring portion.

In recent years, advances in process technology have made it possible to use processes with four or more layers of metal wiring. Reinforcement power / ground wiring is wired in a wiring layer higher than the wiring used in the basic cell, and directly below it. By arranging the basic cells at the same time, it is possible to suppress an increase in area.

[0004]

However, in the case where the reinforcing power supply / ground wiring is wired in a wiring layer higher than the wiring used in the basic cell and the basic cell is arranged immediately below the wiring, the conventional layout creation is required. In the method, for example, the method disclosed in Japanese Patent Application Laid-Open No. 11-214523, the cells can be stored without paying attention to the local reduction of the wirable places (hereinafter referred to as wiring tracks) generated by the reinforcing power supply / ground wiring. Due to the placement, wiring concentration is likely to occur due to detouring of wiring around the power supply and ground wiring for reinforcement, which may make wiring impossible, increasing the number of redoing and redoing wiring. There was a problem of doing.

That is, when a cell having a large number of input / output terminals (a basic cell such as a NAND, NOR, INV, or D-FF) with respect to the cell width is arranged immediately below the reinforcing power supply / ground wiring, the highest priority is given. Since the number of connections to the input / output terminals increases, the number of wirings increases despite the small number of wiring tracks. For this reason, the wiring tracks overflow and detour wiring is generated in the vicinity of the reinforcing power supply / ground wiring, whereby wiring concentration occurs in the vicinity of the reinforcing power supply / ground wiring and wiring becomes impossible.

An object of the present invention is to eliminate the above-mentioned problems and to provide a method for avoiding wiring failure even when a basic cell is arranged immediately below a reinforcing power / ground wiring, and to provide a layout having a small area. And

[0007]

A semiconductor integrated circuit according to the present invention uses a plurality of basic cells as a unit and uses a power supply / ground wiring for reinforcement by using a layer above a wiring layer used in the plurality of basic cells. A semiconductor integrated circuit in which a basic cell is also arranged directly below the reinforcing power / ground wiring, and as a basic cell disposed immediately below the reinforcing power / ground wiring, The ratio of the number of input / output terminals of each basic cell to the width of the basic cell is determined, and those having a ratio smaller than a certain threshold value are preferentially arranged.

[0008] A first layout method of the present invention comprises:
When automatically arranging and routing the basic cell, the reinforcing power / ground wiring is drawn using a layer higher than the wiring layer used in the basic cell, and the basic cell is also placed immediately below the reinforcing power / ground wiring. As a procedure for creating the arranged layout, a first step of reading a netlist, a second step of performing a floor plan, a third step of drawing the reinforcing power / ground wiring,
A fourth step of obtaining a ratio between the number of input / output terminals of each basic cell and the width of the basic cell for a plurality of basic cells described in the netlist; And a fifth step of arranging a plurality of basic cells described in the netlist while arranging the plurality of basic cells under the reinforcing power / ground wiring.

[0009] A second layout method of the present invention comprises:
The first and second steps, the third step of arranging a plurality of basic cells described in the netlist, the width and the number of the reinforcing power supply / ground wiring, and the place where the approximate wiring is to be drawn A fourth step of designating a plurality of the arranged basic cells in the wiring area when wiring is performed with the width in the vicinity of the designated location for each of the reinforcing power supply / ground wirings. A fifth step of counting the number of output terminals and scanning a place where the number of input / output terminals is minimized in the vicinity of the designated place;
A sixth step of wiring the ground wiring is provided.

[0010] A third layout method of the present invention comprises:
The first and second steps, a third step of arranging a plurality of basic cells described in the netlist, and rough routing performed according to the netlist to calculate an expected congestion degree of the wiring. A fourth step, a fifth step of specifying the width and number of the reinforcing power supply / ground wiring and a place where the approximate wiring is to be drawn, and, for each of the reinforcing power supply / ground wiring, in the vicinity of the specified place. A sixth step of comparing the expected congestion degree of the wiring in the wiring area when the wiring is routed with the width, and scanning a place where the expected congestion degree of the wiring is minimized in the vicinity of the designated place; A seventh step of wiring the reinforcing power / ground wiring at the minimum location and an eighth step of performing detailed wiring are provided.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor integrated circuit according to the present invention uses a plurality of basic cells as a unit and uses a power supply layer or ground wiring for reinforcement by using a layer above a wiring layer used in the plurality of basic cells. A semiconductor integrated circuit in which at least one of the basic cells is disposed immediately below the reinforcing power / ground wiring, wherein the plurality of basic cells are disposed as the basic cells disposed immediately below the reinforcing power / ground wiring. Among them, the ratio between the number of input / output terminals of each basic cell and the width of the basic cell is obtained, and the cell having the ratio smaller than a certain threshold value is preferentially arranged.

As described above, a cell having a small number of input / output terminals with respect to the cell width immediately below the reinforcing power / ground wiring (a cell having a complicated internal configuration such as a flip-flop or a full adder).
The number of terminals that cause wiring concentration is reduced,
Area saving can be achieved in a short time.

At present, it is common practice to design an LSI layout on a basic cell basis using automatic placement and routing CAD. Even in this case, according to the layout method of the present invention (claim 2), after reading the netlist, performing floorplanning, drawing the power supply / ground wiring for reinforcement, the plurality of basic information described in the netlist are read. By taking the ratio of the number of input / output terminals of each basic cell to the width of the basic cell for each cell, those with a numerical value smaller than a certain threshold value are preferentially arranged under the reinforcing power supply / ground wiring to reduce wiring concentration. It is possible to reduce the number of terminals that cause the problem, and to reduce the area in a short time.

When a library including a plurality of basic cells is constructed and the automatic placement and routing CAD is used, the number of input / output terminals of each basic cell and the width of the basic cell are previously stored in the library as features of the basic cell. It can also be used by adding the ratio.

Furthermore, the second case in which the layout of an LSI is designed on a basic cell basis using the automatic placement and routing CAD.
According to the layout method of the present invention (claim 4), a floor plan is performed by reading a netlist, a plurality of basic cells described in the netlist are arranged first, Designate the width and number of the reinforcing power / ground wires and the approximate location where the wires are to be drawn.

[0016] Then, in the vicinity of the designated location, when wiring is performed with the same width, a location where the number of input / output terminals is minimized near the designated location is searched for, and the reinforcing power / ground wiring is wired. Wiring concentration can be reduced, and area can be saved in a short time.

Further, according to the layout method of the present invention (claim 5), it is not necessary to specify the approximate location of the reinforcing power supply / ground wiring, so that the layout work can be further automated.

As a third method for designing an LSI layout on a basic cell basis using the automatic placement and routing CAD, according to the layout method of the present invention (claim 6),
Load the netlist and perform a floor plan, place a plurality of basic cells described in the netlist,
The general routing is performed according to the netlist to calculate an expected congestion degree of the wiring.

Next, the width and number of the reinforcing power supply / ground wiring and the approximate location where the wiring is to be drawn are specified, and the expected congestion degree of the wiring in the wiring area is compared. By arranging the reinforcing power / ground wiring at the place where the expected congestion degree is the minimum, the wiring concentration can be reduced and the area can be saved in a short time.

Further, according to the layout method of the present invention (claim 7), since it is not necessary to specify the approximate location of the reinforcing power supply / ground wiring, the layout work can be further automated.

In general, the reinforcing power supply / ground wiring is linearly wired, but may be bent in a crank shape or the like.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing an example of a layout of a semiconductor integrated circuit according to a first embodiment of the present invention (claim 1).

The reinforcing power supply wiring 1 is pulled by the fourth wiring layer, and the cells A2, B3, C
4, cell D5, cell E6, cell F7, cell G8, cell H
9, cell I10, cell J11, cell K12, cell L1
3, cell M14, cell N15, cell O16, cell P1
7, cell Q18, and cell R19 are all laid out below the first wiring layer.

From the input / output terminal of each cell, a signal is taken out by a second layer wiring through a contact between the first and second layers wiring. The wiring track 20 indicates a routable portion derived from the rule (pitch) of each wiring layer, and the wiring of each wiring layer is drawn on this line. The contact between the second and third layers is a contact between the second and third layers, and the third and fourth layers
The layers are connected by contacts between the 3-4 layer wirings.

Immediately below the reinforcing power supply wiring 1, power is supplied through a reinforcing power contact to a cell placed thereunder. At this time, wiring other than the power supply wiring cannot be drawn for any layer in that area.

In the layout of FIG. 1, cells B3 and G
8. A cell having a small number of input / output terminals with respect to the lateral width, such as the cell K12 and the cell P17, is placed immediately below the reinforcing power supply wiring 1. With such a layout, it is possible to reduce the influence of the reduction in the number of wiring tracks in the fourth layer due to the reinforcing power supply wiring 1 and the reduction in the number of tracks in the 1-4 layer wiring due to the reinforcing power supply contact portion.

FIG. 2 shows the third layer and the fourth layer in order to make it easy to see the portion which is difficult to see in the layout of FIG.
This is a semi-transparent layer wiring.

FIG. 3 shows a layout in which the connection state between the cells is the same as the layout of FIG. 1, and a cell having a large number of input / output terminals with respect to the width of the cell such as the cell I10 is arranged.

As is apparent from the figure, in such a case, the wiring cannot be performed unless the wiring is passed through a region where wiring is impossible, such as immediately below the power supply contact region 21, that is, a state where wiring cannot be performed occurs. .

(Embodiment 2) FIG. 4 is a diagram showing a layout method according to a second embodiment of the present invention (claim 2).

A net list 101 and basic cell information 102 such as the number of input / output terminals, cell width, and logic are read in a net list reading step 103. Next, in a floor plan step 104, a block for arranging the basic cells is floor-planned, an area for arranging the cells is generated, and reinforcing power / ground wiring is wired.

At the cell input / output terminal number / cell width ratio calculation step 105, the cell input / output terminal number / cell width ratio of the basic cell to be used is calculated from the basic cell information 102.

In the cell placement step 106, for each cell described in the netlist 101, while comparing the calculated cell input / output terminal number to cell width ratio with the threshold information 107, And the basic cell having a ratio equal to or higher than a threshold value is preferentially arranged below the reinforcing power / ground wiring in a portion where the reinforcing power / ground wiring is not provided. Note that the priority may be ignored if necessary in order to reduce the remaining places or shorten the delay time.

After the placement in the cell placement step 106 is completed, the input / output terminals of each basic cell are wired and connected according to the netlist 101 in the wiring step 108, and the layout 1
09. As a result, a layout as shown in FIG. 1 is formed.

FIG. 5 is a diagram showing a layout method according to the present invention (claim 3). In the cell classification step 202, the ratio of the number of cell input / output terminals to the cell width is calculated from the basic cell library 201 including basic cell information such as the number of input / output terminals, cell width, and logic, and the ratio is compared with the threshold information 203. Then, the layout is classified into small and large ratios, and the information is added to the basic cell library 201 to create a layout library 204.

Next, the layout library 204 and the netlist 205 are read in the netlist read step 20.
In step 6, a block for arranging a basic cell is floor-planned in step 207 to generate an area for arranging cells and to wire power and ground wiring for reinforcement.

In the cell arranging step 208, for each cell described in the netlist 205, a basic cell having a ratio smaller than the threshold information 203 is added to the reinforcing cell according to the classification information added to the layout library 204. Under the power / ground wiring, a basic cell having a higher ratio is preferentially arranged in a portion where there is no reinforcing power / ground wiring. In addition, there are few remaining places,
Alternatively, in order to reduce the delay time, the priority may be ignored if necessary.

After the placement in the cell placement step 208 is completed, the input / output terminals of each basic cell are wired and connected in accordance with the netlist 205 in the wiring step 209, and the layout 2
Get 10. As a result, a layout as shown in FIG. 1 is formed.

(Embodiment 3) FIG. 6 is a diagram showing a layout method according to the present invention (claim 4). FIG. 7 is a diagram showing a state in which the reinforcing power supply / ground wiring is scanned.

The netlist 301 and basic cell information 302 such as the number of input / output terminals, cell width, and logic are read in a netlist reading step 303. Next, in a floor plan step 304, a block for arranging a basic cell is floor-planned and only an area for arranging cells is generated.
In the cell placement step 305, each cell described in the netlist 301 is placed.

Step 30 for specifying approximate position of power supply wiring for reinforcement
In step 6, the width of the reinforcing power supply / ground wiring, the minimum interval between them, and the maximum scan amount are specified, and from these numerical values, the position to scan the reinforcing power supply / ground wiring is determined as shown in FIG. I do. First, the positions of the reinforcing power sources 401 and 402 are determined in advance at the left and right ends of the block.

Next, a first position separated by a minimum interval 403 given from the reinforcing power source 401 at the left end is determined, and a second position separated from the position by a maximum scan amount 404 is determined. Minimum distance 403 from the second position
When the position separated by the maximum scan amount 404 from the third position that is only separated from the third position does not reach the rightmost reinforcing power source 402, the maximum scan amount 4 from the third position and the position.
A fourth position separated by 04 is determined. If not, the third position is deleted and the process proceeds to the next input / output terminal number scan step 307.

After the fourth position is determined, the same operation is repeated to determine the position for scanning the reinforcing power / ground wiring until reaching the right end.

In the number of input / output terminals scan step 307, the position between the first position and the second position, and the position between the third position and the fourth position, which are determined in the step 306, are specified. The section is scanned while counting the number of input / output terminals within the specified reinforcing power supply width 405 (input / output terminal count area 406,
407), a position where the counted number of the input / output terminals is minimum is determined. If there are a plurality of minimum positions, any of them may be selected.

After scanning each section to determine the position of the reinforcing power / ground wiring, wiring of the reinforcing power / ground wiring is performed in the next reinforcing power wiring step 308, and the netting is performed in the wiring step 309. According to the list 301, input / output terminals of each basic cell other than the reinforcing power / ground wiring are connected by wiring, and a layout 310 is provided.
Get.

(Embodiment 4) FIG. 8 is a diagram showing a layout method according to a fourth embodiment of the present invention (claim 6). FIG. 9 is a diagram showing a state of scanning the reinforcing power supply / ground wiring, which will be described below with reference to these figures.

The net list 501 and basic cell information 502 such as the number of input / output terminals, cell width, and logic are read in a net list reading step 503. Next, in a floor plan step 504, a block for arranging basic cells is floor-planned and only an area for arranging cells is generated.
In the cell placement step 505, each cell described in the netlist 501 is placed.

In the schematic wiring step 506, an approximate wiring path for wiring the input / output terminals of each basic cell other than the power supply / ground wiring for reinforcement in accordance with the netlist 501 is defined as a unit of the block area 601 shown in FIG. Is determined as path information in units of the unit wiring area 604. At this time, there is a difference in the number of wiring paths passing through a certain unit wiring area, and this is classified for each number of stages. In FIG. 9, it is indicated by the darkness, and the darker one indicates that the number is larger.

Step 50 for specifying approximate position of power supply wiring for reinforcement
In step 7, the width of the reinforcing power / ground wiring, the minimum interval between them, and the maximum scan amount are specified, and from these numerical values, the position to scan the reinforcing power / ground wiring is determined as shown in FIG. I do.

First, the positions of the reinforcing power supplies 602 and 603 are determined in advance at the left and right ends of the block.

Next, a first position separated by the minimum interval 605 given from the reinforcing power source 602 at the left end is determined, and a second position separated from the position by the maximum scan amount 606 is determined.

If the position separated by the maximum scan amount 606 from the third position separated from the second position by the minimum interval 605 does not reach the rightmost reinforcing power source 603,
The third position and a fourth position separated from the third position by a maximum scan amount 606 are determined. If not, the third position is deleted and the next congestion degree scanning step 508 is performed.
Move to

After the fourth position is determined, the same operation is repeated to determine the position for scanning the reinforcing power supply / ground wiring until the right end is reached.

In the congestion degree scanning step 508, the interval between the first position and the second position, and the interval between the third position and the fourth position determined in the reinforcing power supply wiring approximate position specifying step 507 are determined. Is scanned while counting the number of schematic wirings in each of the unit wiring areas 604 within the specified reinforcing power supply width 607 (wiring congestion count areas 608 and 609), and the counted number of schematic wirings is minimized. Is determined.

In FIG. 9, each of the thin unit wiring regions 604
Means scanning locations that contain many If there are a plurality of minimum positions, any of them may be selected.

After each section is scanned to determine the position of the power supply / ground wiring for reinforcement, the power supply / ground wiring for reinforcement is wired in the next power supply wiring step for reinforcement 509, and the detailed wiring step 510 is performed in step 510. According to the netlist 501, the input / output terminals of each basic cell other than the power supply / ground wiring for reinforcement are wired and connected in detail, not schematically, to obtain a layout 511.

In the above embodiment, the reinforcing power / ground wiring is shown as a straight wiring, but is not limited to a straight wiring. That is, the reinforcing power / ground wiring is generally wired linearly, but may be bent in a crank shape or the like.

[0059]

According to the semiconductor integrated circuit of the present invention (claim 1), a cell (flip-flop,
Since a complex cell with an internal configuration such as a full adder is placed,
The number of terminals that cause wiring concentration is reduced, and area can be saved in a short time.

In addition, according to the layout method of the present invention (claim 2), even when the layout design of the LSI is performed on the basis of the basic cell, the power supply / ground wiring for reinforcement is described in the netlist. By taking the ratio of the number of input / output terminals of each basic cell and the width of the basic cell for a plurality of basic cells, by placing those with a numerical value smaller than a certain threshold value preferentially under the reinforcing power supply / ground wiring, The number of terminals that cause wiring concentration can be reduced, and area can be saved in a short time.

In the case where a library including a plurality of basic cells is constructed and the automatic placement and routing CAD is used as in the present invention (claim 3), each of the basic cells is previously stored in the library as a feature of the basic cells. The ratio between the number of input / output terminals of the cell and the width of the basic cell can be additionally used.

Further, as a second method for designing an LSI layout on a basic cell basis, according to the layout method of the present invention (claim 4), a plurality of basic cells previously described in the netlist are described. Are arranged, and the width and the number of the power / ground wiring for reinforcement and the place where the approximate wiring is to be drawn are specified. Then, in the vicinity of the designated place, when wiring is performed with the width, a place where the number of the input / output terminals is minimized in the vicinity of the designated place is searched, and the reinforcing power supply / ground wiring is wired to reduce wiring concentration. The area can be reduced in a short time.

According to the layout method of the present invention (claim 5), it is not necessary to specify the approximate location of the reinforcing power supply / ground wiring, so that the layout work can be further automated.

As a third method for designing the layout of an LSI on a basic cell basis, according to the layout method of the present invention (claim 6), rough wiring is performed according to a netlist to predict wiring. Calculate the congestion degree.
Next, the width and number of the reinforcing power supply / ground wiring and the approximate location where the wiring is to be drawn are specified, and the expected congestion degree of the wiring in the wiring area is compared. By arranging the reinforcing power / ground wiring at the minimum location, the wiring concentration can be reduced and the area can be saved in a short time.

According to the layout method of the present invention (claim 7), it is not necessary to specify the approximate location of the reinforcing power supply / ground wiring, so that the layout work can be further automated.

[Brief description of the drawings]

FIG. 1 is a diagram showing a layout state of a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 illustrates a layout 3 according to the first embodiment of the present invention.
Diagram of semi-transparent fourth layer wiring

FIG. 3 is a diagram showing a layout when cell arrangement is different;

FIG. 4 is a diagram showing a layout method according to a second embodiment of the present invention;

FIG. 5 is a diagram showing a layout method according to a second embodiment of the present invention using a basic cell library;

FIG. 6 is a diagram showing a layout method according to a third embodiment of the present invention;

FIG. 7 is a diagram showing a scan state according to the third embodiment of the present invention;

FIG. 8 is a diagram showing a layout method according to a fourth embodiment of the present invention;

FIG. 9 is a diagram illustrating a scan state according to the fourth embodiment of the present invention;

[Explanation of symbols]

 1 Reinforcement power supply wiring 2-19 Basic cell 101 Netlist 102 Basic cell information 103 Netlist reading step 104 Floor plan step 105 Cell input / output terminal number to cell width ratio calculation step 106 Cell arrangement step 107 Threshold information 108 Wiring step 109 Layout 201 Basic Cell Library 202 Cell Classification Step 203 Threshold Information 204 Layout Library 306 Reinforcement Power Supply Wiring Outline Position Designation Step 307 Input / Output Terminal Number Scan Step 308 Reinforcement Power Supply Wiring Step 401, 402 Reinforcement Power Supply 403 Minimum Interval 404 Maximum Scan Amount 405 Reinforcement power supply width 406, 407 Input / output terminal count area 506 Schematic wiring step 507 Reinforcement power wiring schematic position designation step 508 Congestion degree scan step Flop 509 reinforcing power lines step 510 detailed routing step 601 block area 602, 603 reinforcing supply 604 unit wiring region 605 minimum interval 606 maximum scan volume 607 reinforcing power width 608, 609 wiring congestion count area

Claims (8)

[Claims] 1. A power supply / ground wiring for reinforcement is drawn by using a plurality of basic cells as a unit and using a layer higher than a wiring layer used in the plurality of basic cells, and directly under the power / ground wiring for reinforcement. A semiconductor integrated circuit in which basic cells are also arranged, wherein the number of input / output terminals of each basic cell and the number of basic cells are determined from among the plurality of basic cells as basic cells to be disposed immediately below the reinforcing power / ground wiring. A semiconductor integrated circuit wherein a ratio of cell widths is determined, and a cell having a ratio smaller than a certain threshold value is preferentially arranged. 2. When automatically arranging and routing a basic cell, a reinforcing power / ground wiring is drawn by using a layer higher than a wiring layer used in the basic cell, and immediately below the reinforcing power / ground wiring. As a procedure for creating a layout in which basic cells are also arranged, a first step of reading a netlist, a second step of floorplanning, a third step of drawing the reinforcing power / ground wiring, A fourth step of taking the ratio between the number of input / output terminals of each basic cell and the width of the basic cell for a plurality of basic cells described in the list; A fifth step of arranging a plurality of basic cells described in the netlist while arranging the cells under the reinforcing power / ground wiring. Layout method characterized by comprising a. 3. A method of preparing available basic cell types as a library and automatically arranging and wiring the layout to create a layout, wherein the number of input / output terminals and the basic cell number are determined in advance for each of the available basic cell types. Take the ratio of the width of, and classify those whose ratio value is smaller than a certain threshold value and those that are not, and reflect the classification in the fifth step without performing the fourth step, Of the basic cells described in the netlist read in the first step, those having a numerical value of the ratio smaller than a certain threshold are preferentially arranged under the reinforcing power / ground wiring, 3. The layout method according to claim 2, wherein the basic cells described in the netlist are arranged. 4. When automatically arranging and wiring a basic cell, a reinforcing power / ground wiring is drawn by using a layer higher than a wiring layer used in the basic cell, and immediately below the reinforcing power / ground wiring. As a procedure for creating a layout in which basic cells are arranged, a first step of reading a netlist, a second step of floorplanning, and arranging a plurality of basic cells described in the netlist A fourth step of specifying the width and number of the reinforcing power / ground wiring and a place where the approximate wiring is to be drawn; and each of the reinforcing power / ground wiring,
In the vicinity of the specified location, when wiring with that width,
A fifth step of counting the number of input / output terminals of the plurality of arranged basic cells in the wiring area, and scanning a location near the designated location where the number of input / output terminals is minimized; A layout method, comprising: a sixth step of wiring the reinforcing power / ground wiring at a location. 5. The fourth step is to specify the width of the reinforcing power supply / ground wiring, the minimum interval between them, and the maximum scan amount, and the fifth step is to specify the width of the area formed by the floor plan. While scanning in the direction (X-axis) up to the maximum scan amount, the number of input / output terminals of the arranged plurality of basic cells in the area where the reinforcing power / ground wiring is drawn with the width is counted. ,
In the scan, a location where the number of input / output terminals is minimized is searched, and as a sixth step, one of the reinforcing power supply or ground wiring is wired at the searched location, and a seventh step is performed.
As for the reinforcing power supply or ground wiring not wired in the sixth step as a step, scanning is performed in the same manner as in the fifth step from the position separated by the minimum distance from the wired X coordinate, and Count the number of input / output terminals of the plurality of arranged basic cells in the area where the reinforcing power / ground wiring is drawn,
In the scan, a location where the number of input / output terminals is minimized is searched, and as a eighth step, a reinforcing power supply or ground wiring not wired in the sixth step is wired to the searched location, 5. The layout method according to claim 4, wherein the step of repeating is repeated until the scanning in the horizontal direction reaches the end on the opposite side of the floor-planned area, thereby wiring the reinforcing power / ground wiring. . 6. When automatically arranging and routing a basic cell, a reinforcing power / ground wiring is drawn by using a layer higher than a wiring layer used in the basic cell, and immediately below the reinforcing power / ground wiring. As a procedure for creating a layout in which basic cells are arranged, a first step of reading a netlist, a second step of floorplanning, and arranging a plurality of basic cells described in the netlist A third step of performing approximate routing according to the netlist and calculating an expected congestion degree of the wiring; and wanting to draw approximate widths and numbers of the reinforcing power supply / ground wirings. A fifth step of specifying a location, and for each of the reinforcing power and ground wirings,
When wiring is performed with the width in the vicinity of the specified location, the expected congestion degree of the wiring in the wiring area is compared, and a location where the expected congestion degree of the wiring is minimized in the vicinity of the specified location is scanned. 6. A layout method, comprising: a sixth step; a seventh step of wiring the reinforcing power / ground wiring at the minimum location; and an eighth step of performing detailed wiring. 7. The fifth step is to specify the width of the reinforcing power / ground wiring, the minimum interval between them, and the maximum scan amount, and the sixth step is to specify the width of the area formed by the floor plan. While scanning up to the maximum scanning amount in the direction (X-axis), the expected congestion degree of the wiring in the wiring area when the reinforcing power / ground wiring is drawn with the width is compared, and the expected congestion of the wiring is performed. A location where the degree is minimized is searched, and as a seventh step, one of the reinforcing power supply or ground wiring is wired at the search location, and as an eighth step, a reinforcing power supply not wired in the seventh step Or about the ground wiring,
Estimated congestion of the wiring in a region where the scanning is performed in the same manner as in the sixth step from the position separated by the minimum distance from the wired X coordinate and the reinforcing power / ground wiring is drawn with the width. And a search is made for a location where the expected congestion degree of the wiring is minimized. As a ninth step, the reinforcing power supply or ground wiring not wired in the seventh step is wired to the searched place, 7. The power supply / ground wiring for reinforcement is formed by repeating steps 6 to 9 until the scanning in the horizontal direction reaches the opposite end of the floor-planned area. The layout method described. 8. The layout method according to claim 5, wherein one of the reinforcing power / ground wirings is wired at both ends in the horizontal direction of the floor-planned area.