JPH05259285A - Wiring path processing method and wiring path processing system - Google Patents

Abstract

PURPOSE:To provide the technology for easily obtaining wiring paths which pass the desired positions. CONSTITUTION:Formation of wiring path passing the desired points can be realized by setting virtual points to the desired positions in the unwired sections and then determining wiring paths using the preset virtual points as the starting points for searching wiring paths. Moreover, wiring patterns passing the wiring layers having the highest priority are intentionally formed by setting the virtual points to the wiring layer having the highest priority and thereby repair of wiring layer of multilayer wiring can be done very easily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout technique of a wiring pattern or a wiring path on a semiconductor integrated circuit such as a gate array, a standard cell, a custom LSI, or a wiring board.

[0002]

2. Description of the Related Art Conventional methods generally adopted for automatic wiring design of semiconductor integrated circuits include a pattern limiting method, a maze method, a line search method and a channel assignment method.

In the pattern limiting method, the terminals are connected in a predetermined pattern shape such as an L shape, but since the available wiring patterns are limited, the automatic wiring ability is low. It can only be applied to simple wiring patterns.

The maze method is a method of managing the availability of wiring on a wiring grid basis and searching for a path from a starting point terminal to an ending point terminal by shifting one wiring grid in a predetermined direction.
In this maze method, since the search is performed on a wiring grid basis, the processing time is long and a huge working storage area is required for the search processing.

In the line search method, the unit of search is a line segment along the wiring grid, and the wiring pattern is searched while extending the line segment vertically and horizontally so as to bypass the wiring prohibited area. Since the line search method advances the search in line segment units, the processing time is shortened as compared with the maze method, but the processing time and the working storage area are also limited.

The channel allocation method is a method of connecting a branch line to a trunk line in units of cell columns. According to this method, the processing time is shortened, but it is difficult to handle the chip model in which the wiring prohibited area is complicatedly defined.
It is difficult to apply to multi-layer wiring of more layers.

Today, the logic scale of a semiconductor integrated circuit is increasing along with the high integration of the semiconductor integrated circuit and the miniaturization of circuit elements, and accordingly, the processing time for the automatic wiring route processing is increased. There is a demand for shortening and support for multilayer wiring. As an example of a document which describes a technique for coping with such a request, there is a "CMOS device handbook" (Nikkan Kogyo Shimbun, September 29, 1987, P15).
9-P164) and "VLSI computer CAD"
(Industrial books, October 31, 1983, P87-P9
There is 6).

[0008]

In the semiconductor integrated circuit chip, the wiring pattern may be cut or repaired under certain conditions. This wiring repair is generally relatively easy for the pattern of the uppermost wiring layer, but it becomes more difficult for the lower wiring layer. When the number of wiring layers is increased from the current three layers to four layers in the future, the number of cases in which wiring repair becomes impossible will be significantly increased by halving the number of patterns including the pattern using the uppermost layer of all nets. Have been found by the inventor. It is desirable to design the wiring route so that the number of patterns using the uppermost wiring layer becomes large, but in the conventional technology, basically, the purpose is to connect the unwired section, and the shape of the wiring route and its It has been said that where the wiring route passes, etc., it is not particularly considered, nor is it necessary to be considered unless it becomes redundantly long. Therefore, in such a conventional method, it is not possible to intentionally obtain a wiring pattern that passes through the uppermost wiring layer.

An object of the present invention is to provide a technique for easily obtaining a wiring route passing through an arbitrary position.

Another object of the present invention is to provide a technique for facilitating wiring repair in a multilayer wiring by intentionally forming a wiring pattern passing through the uppermost wiring layer.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, in a wiring route processing method for determining a wiring route for connecting terminals, a first step of setting a virtual point at an arbitrary position in an unwired section, and a set virtual point as a starting point of a wiring route search. Or a second step of determining a wiring route so as to pass through the virtual point. In a more specific aspect, a step of determining a candidate point of the virtual point, a step of determining whether or not the candidate point belongs to the uppermost wiring layer according to library information, and a periphery of the candidate point are a wirable area. And the step of determining whether or not is included in the first step.

The wiring route processing system is configured to obtain physical wiring pattern information for connecting the required terminals by using the above method. For example, the logical connection relationship of the circuit blocks, the physical pattern layout result of the circuit blocks determined based on the logical connection relationship, the layout rule of the semiconductor integrated circuit, and the condition for setting the virtual points. When a library is input, it is configured to output the physical wiring pattern information for connecting the terminals of the circuit block by determining the wiring route using the set virtual point as the starting point of the wiring route search. be able to.

[0015]

According to the above means, the virtual point is set at an arbitrary position in the unwired section, and the wiring route is determined by using the set virtual point as the starting point or the relay point of the wiring route search.
It is possible to form a wiring path that passes through the starting point or the relay point. Further, setting the virtual points in the uppermost wiring layer enables formation of a wiring pattern that passes through the uppermost wiring layer, and facilitates wiring repair in multilayer wiring.

[0016]

FIG. 2 shows an embodiment in which the present invention is applied to an automatic placement and routing technique for a semiconductor integrated circuit.

In the figure, 1 is an automatic placement system, and 2 is an automatic wiring system, each of which has its own operation program and executes processing in accordance with parameters input by a key or a card. Although the automatic placement system 1 and the automatic wiring system 2 are illustrated as different blocks in FIG. 2, a workstation or a computer as hardware can also be used.

Information on the logical file 3 and the LSI structure library 4 is given to the automatic placement system 1. The logic file 3 includes logic circuit diagram information such as logic gates for forming a semiconductor integrated circuit and logical connection information between the gates. The LSI structure library 4 includes information such as the size of the LSI, the cell shape, the wiring prohibited area, the layout rule, and the cell mountable area required in advance in the case of a gate array or a standard cell.

The automatic placement system 1 reads the information of the logic file 3 and the LSI structure library 4, and allocates various gates for constructing a required logic circuit to cells on a virtual chip according to the information. The cell allocation result is stored in the placement result file 5.

The automatic wiring system 2 reads the information of the placement result file 5, the logic file 3 and the LSI structure library 4, finds the wiring route between the cells according to the information, and stores the coordinate information in the wiring result file 6. The details of the wiring route search processing performed by the automatic placement system 2 will be described later. A virtual point is set at an arbitrary position in an unwired section, and the set virtual point is used as the starting point of the wiring route search. I am trying to decide. The work area required for data processing at this time is assigned to all or part of the main memory 7.

FIG. 3 is a partial plan view of a semiconductor integrated circuit formed according to the arrangement and wiring information obtained by the system shown in FIG.

In the figure, reference numeral 10 denotes a semiconductor substrate, and an external electrode 11 such as a bonding pad or a CCB pad and an input / output buffer circuit 12 are arranged on the edge portion thereof.
A large number of predetermined internal cells 13 are arranged in the central portion. In FIG. 2, the internal cells 13 are regularly arranged in the column direction with a constant width like a gate array.
The invention is not so limited.

Although not particularly limited, the semiconductor integrated circuit of FIG. 3 has four wiring layers. In the figure, wirings from the terminals S to T of the internal cell 13 are shown as representatives, 14 is a first layer wiring formed in the first wiring layer, and 15 is a second wiring.
The third layer wiring, 16 is the third layer wiring, 17 is the fourth layer wiring, and the end portions of the adjacent wiring layers are through holes 18, 1.
They are connected via 9, 20. First layer wiring 1
The fourth and third layer wirings 16 are mainly formed of a conductive pattern such as aluminum extending in the X direction, and the second layer wiring 15 and the fourth layer wiring 17 are mainly conductive patterns such as aluminum extending in the Y direction. Formed by.

An example of the processing executed by the automatic wiring system 2 is performed according to the following procedure shown in FIG.

When the unwired section is input (step 31), the virtual point first candidate point is obtained based on the virtual point library 36. This virtual point first candidate point is set as the center of gravity of the unwired section (step 32). Next, the initial value of the Manhattan distance L is set to 0 (step 33). That is, L = 0. A point deviated from the first candidate point of the virtual point by the Manhattan distance L is represented by coordinates (X, Y), and is set as a virtual point candidate point. Initially, the initial value of L = 0 is still set in step 33, so the coordinate (X, Y) is the first virtual point candidate point, that is, the center of gravity of the unwired section. And the coordinates (X, Y)
However, it is judged whether or not it matches the predetermined virtual point condition library 36 (step 35). here,
The virtual point condition library 36 defines rules such as setting a virtual point in the uppermost wiring layer and setting a virtual point in an unwired section. The contents of the virtual point condition library can be changed as appropriate, and the setting position of the virtual points can be changed by changing the contents. When it is determined that the coordinates (X, Y) match the virtual point condition library 36 (YES) in the determination in step 35, it is determined whether or not the coordinates (X, Y) can be wired. Is performed (step 37), and if it is determined that it is possible, it is further determined whether or not wiring is possible on the left, right, top and bottom of the coordinate (X, Y) (step 38). , If it is determined to be possible,
The coordinates (X, Y) are determined as virtual points (step 3).
9). On the other hand, the coordinates (X, Y) do not match the virtual point condition library in the determination in step 35 (N
If it is determined to be O), or if it is determined that the wiring at the coordinates (X, Y) is impossible (NO) in the determination in step 37, the coordinates (X, Y) are determined in the determination in step 38. If it is determined that the wiring on the left, right, top, and bottom of Y) is impossible (NO), it is inappropriate to set it as a virtual point, so the Manhattan distance L is incremented (+1), and Is updated, the determination in steps 35, 36, and 37 is performed for a new virtual point candidate point, that is, the coordinate (X, Y). As such, finally in step 38 YE
When it is judged as S, the virtual point is determined in step 39.

After the virtual points are set as described above,
Although not particularly limited, according to a predetermined algorithm such as a maze method, which is a method of managing the availability of wiring on a wiring grid basis and searching a route from a start point to an end point by shifting one wiring grid in a predetermined direction, The virtual point is searched as the starting point of the wiring route search, and the wiring route is determined thereby. That is, according to the conventional technique, as shown in FIG. 4 (A), a search is performed while shifting one wiring grid from the terminal 51 as a starting point in the path from the terminal 51 to the terminals 52, 53, while In the embodiment method, the search start point is not used as a terminal, and the virtual point finally determined in step 39 is used as the search start point. Therefore, as shown in FIG. 60 to terminal 51 direction, terminal 5
Searched in 2,53 directions. In other words, a wiring route that surely passes through the position is formed with the position arbitrarily set by the contents of the virtual point condition library 36 as the starting point. In this embodiment, the virtual point condition library 36 is defined so that the virtual point 20 is set in the uppermost layer. Therefore, a part of the wiring route passing through the virtual point 20 is always integrated in the semiconductor. It is formed on the top layer of the circuit. Therefore, even if the number of wiring layers of the semiconductor integrated circuit is increased from the current three layers to four layers, by forming a part of the wiring route which may be the target of the wiring repair or may be the uppermost layer, Therefore, it is possible to avoid a large decrease in the number of nets used at the highest level, thereby facilitating the repair of wiring.

Further, as shown in FIG. 5, when the starting point of the conventional wiring route search is the terminal 51 and the search range is a square having a side length of 2R, the area of the square 71 is increased. Is set to 4R ² (= 2R × 2R), whereas the search range when the virtual point 60 is set at the center of the terminals as shown in FIG.
Since the square 72 has a side length of R, and the area of the square 72 is R ² , the search range is consequently ¼ of that in the conventional method, and the wiring path formation processing time by the maze method is shortened. Can be promoted.

According to the above embodiment, the following operational effects can be obtained.

(1) Setting the virtual point 60 at an arbitrary position in the unwired section and determining the wiring route with the set virtual point as the starting point of the wiring route search means forming a wiring route passing through the arbitrary point. Is possible. Further, by setting the virtual point in the uppermost wiring layer, the wiring pattern passing through the uppermost wiring layer can be intentionally formed, so that the wiring repair in the multilayer wiring can be facilitated.

(2) Utilizing the above wiring route processing method,
By obtaining the physical wiring pattern information for connecting the required terminals, it is possible to configure the wiring route processing system having the effect (1).

(3) Logical connection relation of circuit blocks, physical pattern layout result of circuit blocks determined based on the logical connection relation, layout rule of semiconductor integrated circuit, and virtual point setting By inputting the condition library for, and determining the wiring route using the set virtual point as the starting point of the wiring route search.
It is possible to obtain a wiring route processing system having the effects of

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, although the maze method is adopted in the above embodiment, a pattern limiting method for connecting terminals in a predetermined pattern shape such as an L-shape, or a search unit for wiring. It is also possible to adopt a line search method or the like in which line segments are arranged along a lattice, and the line patterns are searched while extending the line segments vertically and horizontally so as to bypass the wiring prohibited area.

In the above embodiment, the search starting point is not a terminal but the virtual point finally determined in step 39 of FIG. 1 is set as the search starting point. By changing, it is possible to determine the wiring route so as to pass through the set virtual point as a relay point. For example, if a virtual point is set outside the congestion area in the chip to avoid the congestion area, a wiring path that avoids the congestion area is formed. In particular, it is effective when it is desired to form a wiring route while avoiding a wiring congestion portion. Further, it is possible to set a plurality of virtual points as relay points and pass any one of the plurality of virtual points in the search. In that case, since there are a plurality of destination points in the search, the possibility of reaching the virtual point in the search can be improved as compared with the case where one virtual point is set as the relay point as described above.

In the above description, the case where the invention made by the present inventor is mainly applied to the layout technology of the semiconductor integrated circuit which is the background field of application has been described, but the present invention is not limited thereto. It can also be widely applied to a wiring route determination method for a mounting substrate or a wiring substrate.

The present invention can be applied to a device provided that it includes at least a wiring route processing step for determining a wiring route for connecting terminals.

[0037]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the virtual point is set at an arbitrary position in the unwired section, and the set virtual point is determined as the wiring path search starting point or the relay point to determine the wiring path.
It is possible to form a wiring path that passes through an arbitrary point. At this time, by setting the virtual point on the uppermost wiring layer, the wiring pattern passing through the uppermost wiring layer can be intentionally formed, and as a result, the wiring repair in the semiconductor integrated circuit adopting the multilayer wiring can be performed. Can be facilitated.

[Brief description of drawings]

FIG. 1 is a flowchart of determining a virtual point in a method according to an embodiment of the present invention.

FIG. 2 is a system configuration diagram of an embodiment when the present invention is applied to an automatic placement and routing technique for a semiconductor integrated circuit.

FIG. 3 is a schematic plan view of an example of a semiconductor integrated circuit according to a placement and routing result obtained by the system according to the first embodiment.

FIG. 4 is an explanatory diagram of pattern comparison between the conventional method and the method of this embodiment when the maze method is adopted.

FIG. 5 is an explanatory diagram of comparison of search ranges between the conventional method and the present embodiment method when the maze method is adopted.

[Explanation of symbols]

 1 Automatic Placement System 2 Automatic Wiring System 3 Logic File 4 LSI Structure Library 5 Placement Result File 6 Wiring Result File 7 Main Memory 10 Semiconductor Substrate 11 External Electrode 12 I / O Buffer Circuit 13 Internal Cell 14 First Layer Wiring 15 Second Layer Eye wiring 16 Third layer wiring 17 Fourth layer wiring 18 Through hole 19 Through hole 20 Through hole 51 terminal 52 terminal 53 terminal 60 Virtual point

Claims (5)

[Claims] 1. A wiring route processing method for determining a wiring route for connecting terminals, comprising: a first step of setting a virtual point at an arbitrary position in an unwired section; and a wiring route search for the set virtual point. And a second step of determining a wiring route as a starting point of the wiring route processing method. 2. A wiring route processing method for determining a wiring route for connecting terminals, comprising: a first step of setting a virtual point at an arbitrary position in an unwired section, and passing through the set virtual point. And a second step of determining a wiring route. 3. The first step comprises: determining a candidate point of the virtual point; determining whether the candidate point belongs to the uppermost wiring layer according to library information; and surrounding the candidate point. 3. The wiring route processing method according to claim 1, further comprising a step of determining whether or not the wiring path is a wirable area. 4. A wiring route processing system for obtaining physical wiring pattern information for connecting a required terminal by using the wiring route processing method according to claim 1, 2. 5. A logical connection relationship between circuit blocks, a physical pattern layout result of the circuit blocks determined based on the logical connection relationship, a layout rule of the semiconductor integrated circuit, and virtual point setting. And a condition library for inputting, the wiring that outputs the physical wiring pattern information for connecting the terminals of the circuit block by determining the wiring path using the set virtual point as the starting point of the wiring path search. Route processing system.