JP3599017B2 - Adjustment method of clock propagation delay time - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock wiring structure and a method of adjusting a clock propagation delay time, and more particularly to a clock wiring structure of a semiconductor integrated circuit and a method of adjusting a clock propagation delay time using the clock wiring structure.
[0002]
[Prior art]
At present, a synchronous circuit synchronized with a clock is mainly used for a semiconductor integrated circuit. However, problems have been pointed out regarding clock distribution with the recent increase in the degree of integration and speed of circuits, and various methods have been proposed to solve them.
[0003]
For example, a clock signal in a synchronous circuit is required to simultaneously reach all FFs (flip-flop circuits) and the like in the circuit due to its nature. In reality, there are variations in arrival times called clock skew due to various factors related to design, manufacture, and use. Clock skew not only hinders speeding up of the clock, but also causes malfunction of the circuit.
[0004]
As the speed of the clock increases, the influence on the performance of the clock skew becomes relatively large. Therefore, it is necessary to reduce the clock skew as much as possible. In order to adjust the clock skew, it has been practiced to adjust the wiring length from the clock distribution source to the supply destination, and to insert a buffer or the like as a delay element. However, there is a problem that the method of adjusting the wiring length generates a redundant clock wiring, and the method of inserting a delay element cannot perform fine adjustment.
[0005]
For example, in the clock distribution circuit disclosed in Japanese Patent Application Laid-Open No. 4-326411, regarding such a problem, the clock skew can be adjusted by changing the wiring width of the clock wiring and adjusting the wiring capacitance and the wiring resistance. . FIG. 7 is a block diagram showing the configuration of the clock distribution circuit in Japanese Patent Application Laid-Open No. 4-326411. The clock drivers 41-1 to 41-n connected to the clock generation circuit 30 have clock wires 42-1 to 42-n whose wiring width is adjustable on the output side, and the circuit blocks 50-1 to 42-n. To 50-n are connected. Then, the wiring widths of the clock wirings 42-1 to 42-n are adjusted so that the propagation delay time between each clock driver 41-1 to 41-n and each circuit block 50-1 to 50-n becomes equal, Low clock skew is realized.
[0006]
Next, in a clock distribution circuit in a semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. H11-175183, shield wirings 20 are provided on both sides of clock wirings 21 as shown in FIG. By attaching a ring, the wiring capacitances C11, C12, and C13 at each width of the clock wiring 21 can be gradually reduced. As a result, variations in the clock wiring capacitance of the clock distribution circuit are absorbed, and the clock skew is adjusted.
[0007]
[Problems to be solved by the invention]
In the clock distribution circuit disclosed in Japanese Patent Application Laid-Open No. 4-326411, since the shield wiring is not provided around the clock wiring, the wiring capacity of the clock wiring fluctuates due to other signal wiring around the clock wiring. However, there is a drawback that errors tend to occur in the data, and there is also a problem that the data is easily affected by electromagnetic noise. Further, since the wiring resistance is changed by changing the wiring width of the clock wiring, there is a problem that the current value also changes when the clock wiring is connected to a constant voltage source.
[0008]
In the clock distribution circuit in the semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. H11-175183, the wiring width of the clock wiring 15 is merely adjusted. Therefore, when the wiring capacitance is reduced, the wiring resistance is increased. There is also a problem that the current value changes in accordance with the change in the wiring resistance due to the change in the width. Further, since the shield wiring 20 is only on both sides of the clock wiring 21, there is a problem that the wiring capacitance of the clock wiring 21 is easily affected by other signal wirings under the layer and electromagnetic noise.
[0009]
An object of the present invention is to provide a clock wiring structure and a method for adjusting a clock propagation delay time which solve the above problems.
[0010]
[Means for Solving the Problems]
The clock wiring structure according to the present invention includes a clock wiring (1 in FIG. 1) for transmitting a clock signal provided in one layer, and a pair of clock wiring provided on both sides of the one layer along the clock wiring in the one layer. And the line width of the pair of shield wires is adjusted in accordance with the propagation delay time required for the clock wires .
[0011]
The clock wiring structure according to the present invention includes a clock wiring (1 in FIG. 1) for transmitting a clock signal provided in one layer, and a pair of clock wiring provided on both sides of the one layer along the clock wiring in the one layer. Wherein the line width of the clock line and the line width of the pair of shield lines are adjusted in accordance with the propagation delay time required for the clock line. . Further, the clock wiring structure of the present invention includes the lower layer and the upper layer of the one layer or an adjacent layer shield wiring provided along the clock wiring and the pair of shield wirings in any one of these layers. You can also.
[0012]
In the method for adjusting a clock propagation delay time according to the present invention, a pair of shield wirings (2 in FIG. 1) are provided along the clock wiring on the same layer as a clock wiring (1 in FIG. 1) for transmitting a clock signal. A propagation delay time of the clock signal in the clock wiring is adjusted by changing a line width of the pair of shield wirings.
[0013]
In the method for adjusting a clock propagation delay time according to the present invention, a pair of shield wirings (2 in FIG. 1) are provided along the clock wiring on the same layer as a clock wiring (1 in FIG. 1) for transmitting a clock signal. A propagation delay time of the clock signal in the clock wiring is adjusted by changing a line width of the clock wiring and a line width of the pair of shield wirings.
[0014]
In the method for adjusting a clock propagation delay time according to the present invention, a pair of shield wirings (2 in FIG. 1) are provided along the clock wiring on the same layer as a clock wiring (1 in FIG. 1) for transmitting a clock signal. The width of the clock wiring and the width of the shield wiring, and the length of the clock wiring and the intervening clock driver such that the propagation delay time of the clock signal distributed by the clock wiring to each of the plurality of circuits is equal. (S1, S2 in FIG. 5), the propagation delay time of the clock signal to each of the plurality of circuits is evaluated (S3, S4 in FIG. 5), and the line width of the shield wiring is changed to change the clock signal. The transmission delay time to each of the plurality of circuits is made equal (S5 in FIG. 5).
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
FIG. 1 is a partial perspective view showing a clock wiring structure of a semiconductor integrated circuit according to an embodiment of the present invention.
[0017]
In FIG. 1, a pair of shield wires 2 are arranged in parallel on both sides of a clock wire 1, and a shield wire 3 is provided in parallel below the clock wire 1 and the shield wire 2. The shield wirings 2 and 3 are connected to the ground of the semiconductor integrated circuit.
[0018]
The lower part of the clock wiring 1 and the shield wiring 2 is filled with an insulator except for the shield wiring 3, but FIG. 1 omits the insulator. In addition, the clock wiring 1 and the shield wirings 2 and 3 are partially cut away. In general, the clock wiring 1 extends in many cases and includes a bent portion and a branch portion in many cases. However, if the clock wiring 1 is bent, the shield wiring 2 also bends accordingly and the clock wiring 1 branches. For example, the signal is branched in accordance with this and wired along the clock wiring 1. Similarly, the shield wiring 3 is wired along the clock wiring 1 and the shield wiring 2.
[0019]
3A to 3E are plan views of the clock wiring structure of the semiconductor integrated circuit shown in FIG.
[0020]
FIG. 3A shows a clock wiring structure that is used as a reference when designing wiring. The clock wiring 1 is formed with a width W1, and the shield wiring 2 is formed with a width W2. FIG. 3B shows a case where the width of the shield wiring 2 is increased with respect to the reference clock wiring structure of FIG. 3A. The clock wiring 1 is formed with a width W1, and the shield wiring 2 is formed with a width W3. FIG. 3C shows a case where the width of the shield wiring 2 is reduced to W4. When the width W3> the width W2> the width W4, the wiring capacitance of the clock wiring 1 of FIG. 3B is larger than that of FIG. 3A, and the wiring capacitance of the clock wiring 1 of FIG. (A) (the same conditions are applied except for the width of the shield wiring 2). By changing the width of the shield wiring 2 in this manner, the wiring capacitance of the clock wiring 1 can be changed, and the propagation delay time of the clock signal on the clock wiring 1 can be adjusted.
[0021]
FIGS. 3D and 3E show the case where the line width of the clock line 1 is changed together with the line width of the shield line 2 with respect to the reference clock line structure. The shield line 2 shown in FIG. The clock wiring 1 is formed with a wide width W5, the shield wiring 2 in FIG. 3E is formed with a width W4, and the clock wiring 1 is formed with a narrow width W6. The width W5> the width W1> the width W6, and the wiring capacitance of the clock wiring 1 in FIG. 3D is larger than that in FIG. 3B, and the wiring capacitance of the clock wiring 1 in FIG. 3 (c).
[0022]
The clock wiring structures shown in FIGS. 3B to 3E are examples, and the adjustment of the clock propagation delay time according to the present invention is not limited to these. can do.
[0023]
The line width of the shield wiring 3 may or may not match the line width of the clock wiring 1 or the shield wiring 2. FIG. 3 shows only the case where the width of the pair of shield lines 2 on both sides of the clock line 1 is equal. However, the present invention is not limited to this, and the line width of the pair of shield lines 2 may be different.
[0024]
FIG. 3 shows the case where the width W7 of the entire clock wiring structure, that is, the interval between the outer edges of each of the pair of shield wirings 2 is made constant. However, the present invention is not limited to this, and the width W7 may be changed. However, by keeping the entire width W7 of the clock wiring structure constant and changing only the width of the shield wiring 2 or the width of the clock wiring 1 and the shield wiring 2, the propagation delay time of the clock signal is adjusted. There is an effect that adjustment can be performed without affecting wirings and elements other than 1.
[0025]
FIG. 4 shows a clock distribution circuit when clock signals are distributed in a tree shape to five FFs 6a to 6e by two-stage clock drivers 4, 5a, and 5b using the clock wiring structure shown in FIG.
[0026]
The clock input terminal 11 is connected to the clock driver 4 by the clock wiring unit 7, and the clock driver 4 is connected to the branch point 12 by the clock wiring unit 8, and the branch point 12 is connected to the clock driver 5a by the clock wiring units 8a and 8b. , 5b. The clock drivers 5a and 5b are connected to branch points 13 and 15 at clock wiring sections 9 and 10, the branch point 13 is connected to FFs 6a and 6b at clock wiring sections 9a and 9b, and the branch point 15 is connected to a clock wiring section. 10a and 10b are connected to the FFs 6a and 6b. Further, a branch point 14 provided in the middle of the clock wiring section 9b is connected to the FF 6c by the clock wiring section 9c.
[0027]
At least the clock wiring portions 8a, 8b, 9a to 9c, 10a, and 10b are configured by the clock wiring structure shown in FIG. 1, and the line width of the clock wiring 1 of the clock wiring portions 8a, 8b, 9a to 9c, 10a, and 10b By changing the line width of the shield line 2 or the line width of the shield line 2 and the line width of the clock line 1 variously as shown in FIG. 3, the propagation delay time of the clock signal from the clock input terminal 11 to the FFs 6a to 6e can be adjusted. it can.
[0028]
FIG. 5 is a flowchart showing a method for automatically wiring a clock distribution circuit by CTS (Clock Tree Synthesis) using the clock wiring structure shown in FIG. 1 and adjusting a clock propagation delay time as necessary.
[0029]
In step S1, the number of clock drivers 4, 5a and 5b to be inserted, the number of fan-outs, and the like are determined from the initial circuit information. In step S2, the clock drivers 4, 5a and 5b are inserted, and a tree-shaped clock distribution circuit is generated by the balance wiring and the bypass wiring. In this initial generation, the clock wiring units 8a, 8b, 9,..., 10b have a reference composed of a clock wiring 1 and a shield wiring 2 all having the same line width, as shown in FIG. The adjustment of the propagation delay time by the clock wiring portions 8a, 8b, 9,..., 10b is performed by adjusting the respective lengths of the clock wiring portions 8a, 8b, 9,. .
[0030]
In step S3, delay calculation is performed, and in step S4, timing determination is performed. If the difference between the arrival times of the clock signals at the FFs 6a to 6e is within the allowable range, the timing determination is passed and the generation of the clock distribution circuit by the clock tree is completed.
[0031]
If the timing determination is unsuccessful, in step S5, the shield wiring of the clock wiring units 8a, 8b, 9a to 9c, 10a, and 10b after the branch point 12 of the clock tree is reduced so that the difference in clock delay time is reduced. 2 or the line width of the clock wiring 1 is adjusted as shown in FIG. The delay calculation is performed again (step S6), and the timing is determined (step S4). This loop process is executed until the timing judgment is passed.
[0032]
The delay calculations in steps S3 and S6 are performed on a computer. FIG. 6 is a circuit diagram for explaining this delay calculation method. A wiring 16 from a starting point A to a branch point B to which a signal is input, a wiring 17 from a branch point B to a terminal D, and a wiring 17 from the branch point B to a terminal This is a branched wiring consisting of the wiring 18 up to E.
[0033]
The wiring 16 has on-resistance R1, transistor resistances R2, R3 and wiring capacitances C2, C3 of the transistor, and the wiring 17 has wiring resistances R4, R7 and wiring capacitances C4, C7, and is connected to the load capacitance C8. ing. The wiring 18 has wiring resistances R5 and R6 and wiring capacitances C5 and C6. Load capacitors C9 and C10 are connected to the terminals D and E, respectively. The load capacitances C8 to C10 are for transistors.
[0034]
In the wiring branched as shown in FIG. 6, the delays of the branched nodes are independently calculated as described below, and the respective values are added to obtain the output delay. (In the following formulas, R1, R2... Indicate the on-resistance and the wiring resistance indicated by the symbols, and C2, C3... Indicate the wiring capacitance or the load capacitance indicated by the symbols.)
Delay time from starting point A to branching point B T (A, B) = R1 (C2 + C3 + C4 + C5 + C6 + C7 + C8 + C9 + C10) + R2 (C2 / 2 + C3 + C4 + C5 + C6 + C7 + C8 + C9 + C10) + R3 (C3 + C + 9 + C4 + C5)
Delay time from branch point B to end D T (B, D) = R4 (C4 / 2 + C7 + C8 + C9) + R7 (C7 / 2 + C9)
Delay time from branch point B to end E T (B, E) = R5 (C5 / 2 + C6 + C10) + R6 (C6 / 2 + C10)
Delay time from start A to end D T (A, D) = T (A, B) + T (B, D)
Delay time from start A to end E T (A, E) = T (A, B) + T (B, E)
Skew (delay time difference) at terminals D and E Tskew = | T (A, D) -T (A, E) | = | T (B, D) -T (B, E) | = | R4 (C4 / 2 + C7 + C8 + C9) ) + R7 (C7 / 2 + C9)-{R5 (C5 / 2 + C6 + C10) + R6 (C6 / 2 + C10)} |
Normally, the wiring capacitance is much larger than the load capacitance of the transistor, and C8 to C10 << C2 to C7. Therefore, the skew at the ends D and E Tskew = | T (A, D) −T (A, E) | = | T (B, D) -T (B, E) | to | R4 (C4 / 2 + C7 + C8) + R7 (C7 / 2)-{R5 (C5 / 2 + C6) + R6 (C6 / 2)} |
[0035]
As shown in FIG. 3, the line capacitance and the line resistance are adjusted by variously changing the line width and the interval of the shield line 2 and the clock line 1 so that the value of the skew Tskew becomes zero.
[0036]
Instead of the delay calculation in step S6, a prototype of a semiconductor integrated circuit may be manufactured and the line width of the shield wiring 2 may be further adjusted based on the actual measurement result of the skew of the clock signal of the clock distribution circuit. It is.
[0037]
FIG. 2 is a partial perspective view showing a clock wiring structure of a semiconductor integrated circuit according to another embodiment of the present invention.
[0038]
In FIG. 2, a pair of shield wires 2 are arranged in parallel on both sides of the clock wire 1, and a thick shield wire 19 is provided in parallel below the clock wire 1 and the shield wire 2. The layer shield wiring 19 is composed of a single wide wiring covering at least portions corresponding to the lower layer clock wiring 1 and a pair of the same layer shield wiring 2. Further, the shield wiring 19 of the wide wiring can be formed in a mesh shape by forming a large number of holes.
[0039]
Further, the clock wiring structure and the method of adjusting the clock propagation delay time according to the present invention are not limited to a clock distribution circuit having a tree structure, but also include a clock distribution circuit of another clock distribution circuit (not specifically shown, such as an H-tree structure or a mesh structure). It can also be applied to wiring.
[0040]
FIGS. 1 and 2 show an example in which the shield wirings 3 and 19 are arranged only in the lower layer except for the shield wiring 2 on both sides of the clock wiring 1. It goes without saying that a shield wiring may be provided along the clock wiring.
[0041]
【The invention's effect】
The first effect is that the delay time between each element of the clock signal can be finely adjusted by adjusting the wiring capacitance and the wiring resistance of the clock wiring by changing the line width of the shield wiring and the clock wiring. A clock distribution circuit with a small clock skew can be provided without providing a detour wiring more than necessary or a dummy gate of a clock driver.
[0042]
Also, when changing only the line width of the shield wiring without changing the line width of the clock wiring, and changing the wiring capacitance of the clock wiring to adjust the propagation delay time of the clock signal, the wiring resistance of the clock wiring does not need to be changed. In addition, a change in the propagation delay time of the clock signal can be determined only by a change in the wiring capacitance, and the delay time can be easily estimated and adjusted.
[0043]
Furthermore, when changing only the line width of the shield line without changing the line width of the clock line and changing the line capacitance of the clock line to adjust the propagation delay time of the clock signal, the line resistance of the clock line does not need to be changed. In addition, there is an effect that the current value from a power supply having a constant voltage can be kept unchanged, and the effect is particularly large for a DC component.
[0044]
When the line width of the clock line is changed along with the line width of the shield line, the line resistance of the clock line is also changed. This has the effect of reducing the change in
[0045]
The second effect is that by enclosing both sides of the clock wiring and the lower layer, the upper layer, or both layers with shield wiring, fluctuations in the wiring capacity of the clock wiring due to other signal wiring around the wiring can be prevented, and delay time can be easily estimated. And that electromagnetic noise can be prevented.
[Brief description of the drawings]
FIG. 1 is a partial perspective view of a clock wiring structure according to an embodiment of the present invention.
FIG. 2 is a partial perspective view of a clock wiring structure according to another embodiment of the present invention.
3A and 3B are plan views showing a method of adjusting a propagation delay time of a clock signal having the clock wiring structure shown in FIG. 1, wherein FIG. 3A is a reference clock wiring structure and FIG. 3B is a shield of the reference clock wiring structure; A clock wiring structure in which the line width of the wiring 2 is increased, (c) is a clock wiring structure in which the line width of the shield wiring 2 is reduced, and (d) is a clock in which the line width of the clock wiring 1 and the line width of the shield wiring 2 are widened. FIG. 5E is a diagram of a clock wiring structure in which the line width of the clock wiring 1 and the line width of the shield wiring 2 are reduced.
FIG. 4 is a circuit diagram of an example of a clock distribution circuit to which the clock wiring structure of FIG. 1 is applied;
5 is a flowchart showing a method of adjusting a propagation delay time of a clock signal having a clock wiring structure shown in FIG. 1;
FIG. 6 is a circuit diagram for explaining delay calculations S3 and S5 in FIG. 5;
FIG. 7 is a circuit diagram of a conventional clock distribution circuit.
FIG. 8 is a plan view showing a clock wiring structure of another conventional clock distribution circuit.
[Explanation of symbols]
Reference Signs List 1 clock wiring 2 shield wiring 3 shield wiring 4 clock drivers 5a and 5b clock drivers 6a to 6e FF
7 clock wiring sections 8a, 8b clock wiring sections 9a to 9c clock wiring sections 10a, 10b clock wiring section 12 branch point 13 branch point 14 branch point 15 branch point 16 clock wiring 19 shield wiring 20 shield wiring 21 clock wiring 30 clock generating circuit 41-1 to 41-n Clock Driver 42-1 to 42-n Clock Wiring 50-1 to 50-n Circuit Block A Start B Branch D, E End C2 to C7 Wiring Capacities C8 to C10 Load Capacitors C11 to C13 Wiring Capacitance R1 ON resistance R2 to R7 Wiring resistance

Claims (3)

A pair of shield lines are provided along the clock line on the same layer as the clock line for transmitting the clock signal, and the line width of the pair of shield lines is changed to adjust the propagation delay time of the clock signal in the clock line. A method of adjusting a clock propagation delay time. A pair of shield lines are provided along the clock line on the same layer as the clock line for transmitting the clock signal, and the line width of the clock line and the line width of the pair of shield lines are changed to change the clock of the clock signal. A method for adjusting a clock propagation delay time, comprising adjusting a propagation delay time in a wiring. A pair of shield wirings are provided along the clock wiring on the same layer as a clock wiring for transmitting a clock signal, the width of the clock wiring and the width of the shield wiring are fixed, and a clock distributed by the clock wiring is provided. After determining the length of the clock wiring and the intervening clock driver so that the propagation delay time of the signal to each of the plurality of circuits becomes equal, the propagation delay time of the clock signal to each of the plurality of circuits is evaluated. A method of adjusting a clock propagation delay time, characterized in that a line width of a wiring is changed so that propagation delay times of a clock signal to each of the plurality of circuits become equal.

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