WO2005001926A1

WO2005001926A1 - Integrated circuit and design method thereof

Info

Publication number: WO2005001926A1
Application number: PCT/JP2004/009190
Authority: WO
Inventors: Mamoru Mukuno
Original assignee: Sanyo Electric Co., Ltd
Priority date: 2003-06-30
Filing date: 2004-06-30
Publication date: 2005-01-06
Also published as: JPWO2005001926A1

Abstract

In Fig. 13 (a), for a wire Le4, the wire in the proximity in the horizontal direction excluding the one immediately below is a wire Le 2 and a wire Le6 arranged at the wire layer lower by one layer. Moreover, for a wire Le3, the wire in the proximity in the horizontal direction excluding the one immediately below is a wire Le1 and a wire Le5 arranged at the wire layer lower by one layer. Accordingly, the wire Le4 and the wire Le3 are set so as to reduce the capacity between the wire Le2 and Le1 and between the wire Le6 and the wire Le5. Moreover, in Fig. 13 (b), a wire Lf1 and wire Lf2 as well as the wire Lf2 and a wire Lf3 are connected in series so as to reverse the propagation direction of the signal of each other.

Description

Integrated circuit and design method thereof

Technical field

The present invention relates to an integrated circuit having a multilayer wiring structure formed on a substrate.

[0002] In recent years, it has become mainstream to design a semiconductor integrated circuit layout using a general-purpose automatic placement and routing tool that aims to achieve both high integration of the semiconductor integrated circuit and shortening of the design period. . In such an automatic placement and routing tool, a grid defined so as to satisfy a design rule required by a semiconductor integrated circuit manufacturing process is set, and wiring can be laid on the grid.

[0003] This grid is set in the X-axis direction and the Y-axis direction perpendicular thereto, and the X-axis direction or the Y-axis direction is specified alternately for each wiring layer. The grids are set in a stripe shape running parallel to each other. These grid intervals are set so as to correspond to the wiring pitch satisfying the design rule. Under these settings, in the layout design using the automatic placement and routing tool described above, trial and error are repeatedly performed for the placement mode and the routing of the wiring so as to satisfy both the design rules and the required circuit characteristics. Determine the mask layout.

[0004] However, in a layout design performed using such a grid, a wiring layer that is not effectively used may occur, and a desired result is not always obtained from the viewpoint of effective wiring. Did not. Therefore, for example, as disclosed in Patent Document 1, a method has been proposed in which a grid is set in an oblique direction intersecting the X-axis direction and the Y-axis direction in addition to the X-axis direction and the Y-axis direction. .

Patent Document 1: Japanese Patent Application Laid-Open No. 7-86407

Disclosure of the invention

Problems to be solved by the invention

[0005] By the way, with the recent miniaturization of semiconductor integrated circuits, the width of wiring in semiconductor integrated circuits has been increasing. Increasing the wiring resistance due to the reduction in the wiring, the increase in the capacitance between the wirings due to the reduction in the distance between the adjacent wirings, etc., increase the voltage drop (IR drop) in the wiring, increase the crosstalk noise, It causes problems such as electromagnetic interference (EMI) and electoral port migration, and is becoming a serious problem that cannot be ignored in circuit design.

In semiconductor circuit design, it is necessary to lay out circuit elements and wiring in a limited space and to realize a circuit that satisfies desired characteristics. The above-mentioned increase in resistance and capacitance between wirings has a great effect on signal propagation.However, if the wiring is simply made thicker to reduce the resistance and capacitance, it is limited. It becomes difficult to form a desired circuit in the space provided.

With the automatic placement and routing tools developed to efficiently connect each part of a semiconductor integrated circuit, it is becoming difficult to address the various problems associated with miniaturization. That is, even if a trial and error for connection by the automatic wiring tool is performed, it is extremely difficult to obtain a solution that satisfies design constraints such as timing due to the above problems. This has increased the load on the design and development of semiconductor integrated circuits, and has caused a new problem of prolonging the development period.

[0007] The present invention has been made in view of such circumstances, and an object of the present invention is to provide a more efficient design that satisfies desired circuit characteristics while suppressing an increase in the space in which an integrated circuit is formed. And a design method thereof.

Means for solving the problem

[0008] One embodiment of the present invention relates to an integrated circuit having a multilayer wiring structure formed on a substrate, and has a feature in a wiring configuration laid in a multilayer wiring layer. The features are as follows.

[0009] A second wiring layer is provided separately from the first wiring layer on which the first wiring required to connect two desired points of the integrated circuit is laid. In the second wiring layer, an auxiliary second wiring different from one wiring connecting desired two points is laid. This auxiliary second wiring is connected to the first wiring via via holes in various modes such as straight IJ and parallel. By combining the wirings formed in this way, the resistance and inductance of the wiring connecting the desired two points of the integrated circuit, the parasitic capacitance generated between adjacent wirings, and the signal propagation It plays a role in adjusting electrical characteristics such as delay time.

[0010] When the first wiring layer and the second wiring layer are set so as to be adjacent to each other, the first wiring and the second wiring can be easily connected to each other through the via hole. Further, when the first wiring and the auxiliary second wiring are laid in such a manner that the projection onto the substrate overlaps, the mask of both wiring layers can be made the same, and the via hole The wiring can be easily connected via the.

[0011] Another embodiment of the present invention relates to a method for designing an integrated circuit. The outline of the design method of this integrated circuit is as follows.

A plurality of circuit elements constituting the integrated circuit are laid out in advance. The laid out circuit elements are connected by temporary wiring based on the wiring settings characterized by the virtual physical wiring layer, which is a virtual wiring layer. The arithmetic means determines whether or not the electrical characteristics of the circuit block formed by the temporary wiring satisfy the desired characteristics. The wiring laid on the temporary physical wiring layer is developed as real wiring on the real wiring layer. You. In the above-described determination, when the processing of changing the wiring of one temporary physical wiring layer to the real wiring of one real wiring layer is performed, the temporary wiring of the circuit block that is determined not to satisfy the desired characteristics is temporarily determined. The physical wiring layer is additionally laid as a real wiring formed by transferring the physical wiring layer to a plurality of real wiring layers. At this time, the circuit block is laid so as to satisfy desired characteristics by adjusting the length of the wiring and the capacitance between the wirings by using the above-described various wiring laying forms of the integrated circuit.

[0012] Conventionally, when the circuit block does not satisfy the desired characteristics, provisional wiring is performed again from the beginning, and this is repeated until the desired characteristics are obtained. In the present invention, when the circuit block does not satisfy the desired characteristics, the provisional wiring is performed again by using the additional wiring layer, and the electrical characteristics of the wiring are adjusted. Since the temporary wiring is performed again based on a predetermined rule, the calculation load can be reduced as compared with the conventional method in which the temporary wiring is redone from the beginning.

The invention's effect

According to the present invention, it is possible to suppress an increase in the space in which an integrated circuit is formed, and Can be designed more efficiently.

Brief Description of Drawings

FIG. 1 is a plan view showing a configuration of a first embodiment of an integrated circuit according to the present invention.

FIG. 2 is a view showing a wiring structure that is useful in the same embodiment.

FIG. 3 is a diagram showing a wiring structure that is useful in the same embodiment.

FIG. 4 is a diagram showing a wiring structure that is useful in the same embodiment.

FIG. 5 is a block diagram showing an overall configuration of the integrated circuit design support device according to the same embodiment.

FIG. 6 is a flowchart showing a procedure for designing an integrated circuit that is useful in the same embodiment.

FIG. 7 is a diagram showing a relationship between a circuit diagram and a layout using temporary physical wiring of the circuit diagram in the same embodiment.

FIG. 8 is a diagram showing a relationship between a circuit diagram and a layout using temporary physical wiring of the circuit diagram in the same embodiment.

FIG. 9 is a view showing a mask created in the same embodiment.

FIG. 10 is a diagram showing a wiring structure of an integrated circuit according to a second embodiment of the present invention.

FIG. 11 is a diagram showing a wiring structure according to the same embodiment.

FIG. 12 is a view showing a mask created in the same embodiment.

FIG. 13 is a diagram showing a wiring structure according to the first and second embodiments.

FIG. 14 is a flowchart showing a design procedure of an integrated circuit according to a third embodiment of the integrated circuit according to the present invention.

FIG. 15 is a block diagram showing an overall configuration of an integrated circuit design support device that is useful for an integrated circuit according to a fourth embodiment of the present invention.

FIG. 16 is a flowchart showing a design procedure of an integrated circuit according to a fourth embodiment of the integrated circuit according to the present invention.

FIG. 17 is a diagram exemplifying a partition setting mode in the embodiment.

FIG. 18 is a diagram showing a connection state between adjacent sections in the same embodiment.

FIG. 19 is a diagram showing a connection state between adjacent sections in the embodiment. FIG. 20 is a diagram showing a wiring structure according to a fifth embodiment of the integrated circuit according to the present invention. Garden 21] is a flowchart showing a procedure of designing an integrated circuit working in the same embodiment.

Garden 22] is a diagram showing a connection state between adjacent sections in the same embodiment.

Garden 23] is a diagram showing a connection state between adjacent sections in the same embodiment.

FIG. 24 is a diagram showing a setting mode of partitions in a sixth embodiment of the integrated circuit according to the present invention.

FIG. 25 is a flowchart showing an integrated circuit design procedure according to a seventh embodiment of the integrated circuit according to the present invention.

FIG. 26 is a plan view showing a wiring structure according to the same embodiment.

Garden 27] FIG. 27 is a plan view showing a wiring structure according to the same embodiment.

FIG. 28 is a cross-sectional view showing a wiring structure according to the same embodiment.

FIG. 29 is a diagram showing a wiring structure according to an eighth embodiment of the integrated circuit according to the present invention. Garden 30] It is a diagram showing a mask created in the same embodiment.

Garden 31] is a diagram showing a wiring structure of an integrated circuit according to a ninth embodiment of the present invention. Garden 32] is a diagram showing a mask created in the same embodiment.

FIG. 33 is a perspective view showing a wiring structure in a modification of each of the above embodiments.

Garden 34] It is a circuit diagram of the wiring of each embodiment.

FIG. 35 is a schematic diagram showing a wiring structure in a modification.

FIG. 36 is a schematic diagram showing a wiring structure in a modification.

FIG. 37 is a schematic diagram showing a wiring structure in a modification.

FIG. 38 is a schematic diagram showing a wiring structure in a modification.

FIG. 39 is a schematic diagram showing a wiring structure in a modification.

FIG. 40 is a schematic diagram showing a wiring structure in a modification.

FIG. 41 is a schematic diagram showing a wiring structure in a modification.

FIG. 42 is a schematic diagram showing a wiring structure in a modification. FIG. 43 is a schematic diagram showing a wiring structure in a modified example.

FIG. 44 is a schematic diagram showing a wiring structure in a modification.

FIG. 45 is a plan view showing the configuration of the eleventh embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 46 is a view showing a wiring laying mode in the embodiment.

FIG. 47 is a view showing a wiring laying mode in the embodiment.

FIG. 48 is a view showing a wiring laying mode in the embodiment.

FIG. 49 is a plan view showing the configuration of the semiconductor integrated circuit design support device in the same embodiment.

FIG. 50 is a flowchart showing a design procedure of the semiconductor integrated circuit in the embodiment.

[0015] 10: library, 12: design specification storage unit, 14: process parameters, 16: temporary physical wiring layer rule, 20: circuit variable calculation unit, 22: automatic placement unit, 24: automatic wiring unit, 30: timing Analysis part, 32… Circuit variable determination part, 34… Wiring layer development part, 40 ··· Mask calculation part, 42… Division setting part, 50… Input part, 52… Image display part, 54… Control part, 1010… Library 1012: Design specification storage unit, 1014: Process parameter, 1020: Automatic placement unit, 1022: Automatic wiring unit, 1030: Timing analysis unit, 1040: Input unit, 1042: Image display unit, 1050: Control unit.

BEST MODE FOR CARRYING OUT THE INVENTION

First, an outline of an embodiment will be described.

(1) An integrated circuit according to one embodiment is an integrated circuit having a multilayer wiring structure formed on a substrate, having substantially the same path direction as each other, and Wiring is provided on a plurality of wiring layers so that the projection of the circuit onto the substrate overlaps each other. Wirings laid in a plurality of wiring layers are connected via via holes to form one wiring connecting two desired points of an integrated circuit, and each specific terminal of any two elements is connected. Wiring to be connected, wiring to fix the potential of a specific terminal of an arbitrary element, and wiring with one end of the wiring being substantially open Constitute. For example, various wiring structures shown in FIGS. 2 to 4, FIG. 10, FIG. 11, and FIG. 13 correspond to this mode.

Here, “the projections on the substrate overlap each other” means that a plurality of wirings laid in different wiring layers have substantially the same path direction, and the plurality of wirings are projected on the substrate. If one projected image coincides with another projected image, one projected image is completely included in another projected image, and one projected image and another projected image are partially This includes cases where two wirings are overlapped and two wirings can be connected via via holes.

(2) An integrated circuit according to an embodiment is an integrated circuit having a multilayer wiring structure formed on a substrate, and a first wiring connecting two desired points of the integrated circuit. And a second wiring laid on a different wiring layer from the wiring layer on which the first wiring is laid. The first wiring and the second wiring are laid in such a manner that projections onto the substrate overlap each other, and are connected via via holes to form one wiring connecting the desired two points. . This wiring may be one of wiring connecting between specific terminals of any two elements, wiring fixing the potential of a specific terminal of any element, or wiring in which one end of the wiring is substantially open Function as 1 wiring. For example, various wiring structures shown in FIGS. 2, 4, 20 (a), (b), (d) and the like correspond to this mode.

[0020] According to this integrated circuit, a route is determined for each single actual wiring layer, and actual wiring is laid. Therefore, various problems associated with miniaturization can be easily dealt with.

(3) An integrated circuit according to an embodiment is an integrated circuit having a multilayer wiring structure formed on a substrate, and includes a first wiring connecting two desired points of the integrated circuit. And a second wiring parallel to the first wiring laid on a different wiring layer from the wiring layer on which the first wiring is laid. By electrically connecting the second wiring to the first wiring in parallel, the first wiring and the second wiring constitute one wiring connecting desired two points.

According to this integrated circuit, the wiring resistance can be reduced by the second wiring connected in parallel with the first wiring as compared with the case where two points are connected only by the first wiring. FIG. 3 shows an example of this mode.

[0022] Note that the first wiring and the second wiring are arranged such that projections on the substrate overlap with each other. Alternatively, it may be formed. In this case, it is possible to easily connect the first wiring and the second wiring via the via hole, and to reduce the wiring resistance while minimizing the area where the wiring is laid. And the inductance can also be reduced. Further, it is preferable that another signal transmission wiring is not laid between the first wiring and the second wiring. As a result, it is possible to suitably avoid and suppress the first wiring and the second wiring from electrically interfering with other signal propagation wirings.

Further, the first wiring and the second wiring may be laid on wiring layers adjacent to each other. By arranging the wiring layers adjacent to each other, it is possible to avoid or suppress electric interference between the wiring and the other wiring that occurs when the wiring is laid in an intermediate layer.

(4) The integrated circuit according to one embodiment is an integrated circuit having a multilayer wiring structure formed on a substrate, and a plurality of wirings are formed in such a manner that projections on the substrate overlap with each other. It has a plurality of wirings laid in parallel to the layers. The plurality of wirings are electrically connected in series via via holes in a manner to reverse the signal propagation direction for each wiring layer, thereby forming one wiring connecting desired two points of the integrated circuit. I do. FIG. 3 shows an example of this embodiment.

According to this integrated circuit, the resistance of the wiring can be positively increased without increasing the area where the wiring is laid. This increase in the resistance value can be applied to adjustment of the amount of delay of a signal, generation of a reference potential, and the like in an integrated circuit. It also increases the wiring inductance.

[0024] Further, it is preferable that another signal transmission wiring is not laid between the plurality of wirings.

As a result, it is possible to preferably avoid and suppress electrical interference of a plurality of wirings with other signal transmission wirings.

Further, the plurality of wirings may be laid on wiring layers adjacent to each other. By arranging the wiring layers adjacent to each other, it is possible to avoid or suppress electric interference between the wiring and the other wiring that occurs when the wiring is laid in the intermediate layer.

(5) The integrated circuit according to one embodiment is an integrated circuit having a multilayer wiring structure formed on a substrate, and the wiring laying direction and the wiring interval are substantially between wiring layers adjacent to each other. Are provided with the same region. In this region, the wiring layer That is, the wiring laid on one wiring layer is offset from the wiring laid on the other wiring layer in a direction perpendicular to the laying direction within a range smaller than the wiring laying interval. . FIG. 10 shows an example of this embodiment.

Here, the “laying interval” of the wiring refers to the distance between the center lines of the wirings provided in parallel. According to this integrated circuit, by laying the wirings of adjacent wiring layers offset from each other, it is possible to preferably reduce the capacity between the wirings of the P-connected wiring layer without increasing the horizontal spacing of the wirings. can do.

(6) An integrated circuit according to one embodiment is an integrated circuit having a multilayer wiring structure formed on a substrate, and a first wiring and a second wiring are provided in one wiring layer. Where either one of them is laid, the other wiring is laid so as to escape to another wiring layer. At this time, the first wiring and the second wiring are laid in parallel so that the projections on the substrate are adjacent to each other. FIG. 11 shows an example of this embodiment.

That is, an integrated circuit having a multilayer wiring structure formed on a substrate, comprising a first wiring and a second wiring adjacent to each other when projected onto the substrate. The first wiring and the second wiring can be laid in an adjacent manner on one wiring layer in terms of space. However, either the first wiring or the second wiring is laid on the one wiring layer. And lay it out in such a way that the other wiring escapes to another wiring layer. As a result, the first wiring and the second wiring allow the projection on the power board to be adjacent to each other, but have the same wiring layer as compared to the case where the one wiring layer is laid in an adjacent state. The adjacent length is shortened. According to this integrated circuit, the length of the pair of wirings adjacent to each other in the horizontal direction in the same wiring layer can be shortened, and the capacitance between the pair of wirings can be suitably reduced.

[0028] Further, it is preferable that another wiring for signal propagation is not laid between the pair of wirings.

As a result, it is possible to preferably avoid and suppress the first wiring and the second wiring from electrically interfering with other signal propagation wirings.

Further, the pair of wirings may be laid on wiring layers adjacent to each other. By arranging the wiring layers adjacent to each other, it is possible to avoid or suppress electric interference between the wiring and the other wiring that occurs when the wiring is laid in the intermediate layer. (7) An integrated circuit according to one embodiment is an integrated circuit having a multi-layer wiring structure formed on a substrate, and is provided adjacent to and parallel to a predetermined wiring layer. One pair of wirings and a second pair of wirings laid in parallel with each other on a wiring layer different from the predetermined wiring layer. The second pair of wirings is provided in such a manner that the first pair of wirings and the projection on the substrate overlap each other, and one end is connected to the first pair of wirings via via holes. The two pairs of wirings are formed as dummy wirings whose other ends are substantially open. FIG. 4 shows an example of this embodiment.

According to this integrated circuit, since the wirings are adjacent to each other in a plurality of wiring layers, the capacitance between the wirings can be increased, the delay amount of a signal propagating through the wirings can be adjusted, and impedance matching can be performed. You can go. In addition, it is not necessary to extend the wiring length to increase the capacitance value, which may cause restrictions on the design rail or increase the resistance. Note that, in this integrated circuit, the first pair of wirings and the second pair of wirings may be laid so that the projections on the substrate coincide. This makes it possible to make the mask pattern the same at least for the wiring layer on which the first pair of wirings are laid and the wiring layer on which the second pair of wirings are laid.

Further, it is preferable that no other signal transmission wiring is laid between the first pair of wirings and the second pair of wirings. As a result, it is possible to preferably avoid and suppress electrical interference between the first pair of wirings and the second pair of wirings with other signal transmission wirings.

Further, the wiring layer on which the first pair of wirings are laid and the wiring layer on which the second pair of wirings are laid may be adjacent to each other. By arranging the wiring layers adjacent to each other, it is possible to avoid and suppress electric interference between the wiring and the other wiring when the wiring is laid in the intermediate layer.

(8) The integrated circuit according to one embodiment is an integrated circuit having a multilayer wiring structure formed on a substrate, and wirings laid in a plurality of wiring layers are arranged in parallel via via holes. A first wiring connected to the first wiring. The integrated circuit further includes a second wiring configured by connecting wirings laid on the same wiring layer as a plurality of wiring layers on which the wiring configuring the first wiring is laid in parallel via via holes. And This first wiring and the The wirings constituting each of the second wirings are provided adjacent to and in parallel in the same wiring layer corresponding to each other. FIG. 33 (a) shows an example of this mode.

According to this integrated circuit, the wiring resistance can be reduced as compared with the case where the first and second wirings are single lines. Further, since the first and second wirings are formed adjacent to each other in each wiring layer, the capacitance between the two wirings is also smaller than that when the wirings are formed as a single wiring layer. And can be increased.

Further, it is preferable that no other signal transmission wiring is laid between the wirings constituting the first and second wirings. As a result, it is possible to preferably avoid and suppress the first and second wirings from electrically interfering with other signal transmission wirings.

Also, the wiring layers on which the wirings constituting the first and second wirings are respectively laid may be adjacent to each other. By arranging the wiring layers adjacent to each other, it is possible to avoid and suppress electric interference between the wiring and the other wiring which occurs when the wiring is laid in the intermediate layer.

(9) An integrated circuit according to one embodiment is an integrated circuit having a multilayer wiring structure formed on a substrate, and an aspect in which projections on the substrate overlap with a plurality of wiring layers. The first wiring, which is formed by electrically connecting the wiring laid in step 1 via a via hole, and the same wiring layer as a plurality of wiring layers on which the wiring configuring the first wiring is laid And a second wiring configured by electrically connecting wiring laid in a manner that the projection onto the substrate overlaps via a via hole. The wirings constituting each of the first wiring and the second wiring may be provided adjacently in parallel in the same wiring layer corresponding to each other. FIG. 33 (b) shows an example of this mode.

According to this integrated circuit, the resistance of the first and second wirings can be increased without increasing the wiring laying area. Furthermore, since the first and second wirings are formed adjacent to each other in each wiring layer, the capacitance between the two wirings is also smaller than when both wirings are formed as wiring of a single wiring layer. And can be increased.

The wirings constituting the first and second wirings may be laid on adjacent wiring layers. Les ,. By arranging the wiring layers adjacent to each other, it is possible to avoid and suppress electric interference between the wiring and the other wiring which occurs when the wiring is laid in the intermediate layer.

The integrated circuit according to the embodiment (10) is an integrated circuit having a multi-layer wiring structure formed on a substrate, and includes a plurality of terminals fixed at different potentials from signal transmission wiring. Fixed wiring. One of the signal transmission wiring and the potential fixing wiring is laid so that a part of the wiring is released to another wiring layer. At this time, the signal transmission wiring and the plurality of potential fixing wirings are laid to allow the projections on the substrate to be adjacent to each other. FIG. 2932 shows an example of this embodiment.

[0037] The signal transmission wiring and the plurality of potential fixing wirings can be laid in a manner adjacent to one wiring layer in terms of space. The wiring for signal propagation and the plurality of potential fixed wirings are adjacent in one wiring layer while allowing the projections on the substrate to be adjacent to each other. Compared with the case of laying, the lengths of adjacent wires in the same wiring layer are different.

According to this integrated circuit, the capacitance between the signal transmission wiring and the potential fixing wiring can be adjusted by changing the length of the adjacent wiring in the same wiring layer. It is possible to adjust the signal propagation speed in the transmission wiring. In addition, the ratio of the lengths of adjacent signal transmission lines to the potential fixing lines that are fixed at different potentials is determined by the ratio of the adjacent lengths.

In addition, it is possible to change the waveform of the signal propagating through the signal transmission wiring.

(11) An integrated circuit according to one embodiment is an integrated circuit having a multilayer wiring structure formed on a substrate, wherein wirings are arranged in substantially the same direction and at a predetermined unit interval. And a region having a plurality of wiring layers laid at integer multiples of. In this integrated circuit, at least one of the integrated circuits described in (3) and (10) is formed in the region.

According to this integrated circuit, by providing a region where the wiring laying directions and the wiring laying intervals of the adjacent wiring layers are unified, it is possible to easily form the semiconductor integrated circuits of the above-described embodiments. Further, since the wiring laying interval is an integral multiple of the unit interval in the above area, it can be easily designed by an automatic wiring tool. (12) In this integrated circuit, wiring laying directions in at least one wiring layer may be different between adjacent regions. As a result, an appropriate wiring structure can be applied to each of the plurality of regions. FIG. 17 shows an example of this embodiment.

(13) Further, as for the wirings of the wiring layers in which the wiring laying directions are different from each other in the P-contact region, the wirings laid on the other wiring layers in such a manner that the projection on the substrate is on a straight line are used And may be connected. That is, in the same wiring layer, the wiring is laid in a different direction in the vicinity of the boundary of the wiring laying area where wiring laying directions are different from each other. A connection is made between regions in a horizontal plane having wiring laying regions in different directions. FIG. 18 and FIG. 24 show an example of this embodiment.

According to this integrated circuit, in the same wiring layer, in the vicinity of the boundary between the wiring laying areas where the wiring laying directions are different from each other, the wiring is switched to another wiring layer, and the wiring is laid straight through another wiring layer. In addition, it is possible to connect without detouring on the horizontal plane, eliminating the need for complicated re-search processing to determine the connection route involving detouring on the horizontal plane, and appropriately suppressing the path length required for connection can do.

[0042] Another embodiment of the present invention relates to a method for designing an integrated circuit. The outline of the design method of this integrated circuit will be described below.

(14) In an integrated circuit design method according to one embodiment, a wiring layer in an integrated circuit in which a layout is realized is set as a temporary physical wiring layer, and a predetermined temporary physical wiring among the temporary physical wiring layers is used. The arithmetic means for calculating the circuit characteristics of each wiring of the layer to desired circuit characteristics is applied to a wiring formed using at least one of the regions substantially projected onto an actual wiring layer including a plurality of wiring layers. There is a step of converting.

According to the above design method, each wiring of the temporary physical wiring layer is converted into a wiring formed by using at least one of the regions substantially projected onto the actual wiring layer including a plurality of wiring layers. For this reason, it is possible to realize circuit characteristics (characteristics such as wiring characteristics and capacitance between wirings) that cannot be realized by wiring using a conventional wiring method that does not employ a wiring forming method by such conversion. Therefore, adjustment of circuit characteristics can be easily performed. Further, at this time, since the wiring is converted based on the wiring path of each wiring of the temporary physical wiring layer, such adjustment of the circuit characteristics without correcting the electrical connection mode by the wiring of the temporary physical wiring layer is performed. It can be carried out.

Here, the “substantially projected region” is not limited to the region itself projected in the normal direction to the temporary physical wiring layer, but also includes a region in contact with the same region. In addition, the “integrated circuit in which the layout is realized” is an integrated circuit having layout data and mask data in which each part is connected.

The integrated circuit design method according to the embodiment (15) is a method for designing an integrated circuit for determining a wiring path for connection of each element of an integrated circuit, and temporarily includes a wiring layer for connection. Obtained when a physical wiring layer is used, and each wiring of a predetermined temporary physical wiring layer is converted into a wiring formed using at least one of the regions substantially projected onto a real wiring layer including a plurality of wiring layers. While estimating the circuit characteristics, the wiring path on the temporary physical wiring layer is optimized based on the result of the estimation.

According to this design method, when laying temporary wiring by automatic wiring or the like, the temporary wiring is laid in a wiring laying mode that cannot be realized unless it is assumed that the temporary wiring is spread on more wiring layers. Power S can. As a result, the degree of freedom in selecting the wiring route can be improved, and the calculation load for determining the route of the temporary wiring by the automatic wiring can be reduced. In addition, by performing development on the actual wiring layer based on the temporary wiring determined in this way, wiring having desired circuit characteristics can be easily designed, and characteristics of the entire circuit can be easily adjusted. Can be. Further, since the wirings converted in this way have projections on the substrate overlapping or approaching each other, it is possible to form wirings having a high density of the projections.

(16) An integrated circuit design method according to one embodiment is a method of designing an integrated circuit in which each element of the integrated circuit is automatically arranged, wherein connections are made for each part of the integrated circuit. The wiring layer is a temporary physical wiring layer, and each wiring of a predetermined temporary physical wiring layer of the integrated circuit to be connected is formed by using at least one area of a region substantially projected onto a real wiring layer including a plurality of wiring layers. Based on the results of the prediction, the layout of each element is optimized based on the prediction result of the circuit characteristics obtained when the wiring is formed. According to this design method, it is possible to realize a circuit characteristic that cannot be realized by assuming the element arrangement by the conventional method, that is, the wiring of only the wiring of the temporary physical wiring layer. For this reason, when laying out circuit elements by automatic placement, it is not necessary to presuppose the development from the temporary physical wiring layer to the actual wiring layer, and circuit characteristics that cannot be realized by wiring (characteristics such as wiring characteristics and capacitance between wiring, etc.) ), It is possible to improve the degree of freedom of arrangement. In particular, according to the above-described design method, the arrangement of each element of the integrated circuit should be made denser since the wiring developed on the actual wiring layer is more easily allowed to have a higher density than before the development. Can be. At this time, for laying the temporary wiring of the temporary physical wiring layer, for example, a Steiner wiring or the like may be allowed as an estimate for the placement.

The integrated circuit designing method according to the embodiment (17) is a method for designing an integrated circuit for determining a circuit configuration of an integrated circuit, in which a wiring layer for performing connection required for the circuit configuration is temporarily provided. A circuit obtained when a physical wiring layer is used and each wiring of a predetermined temporary physical wiring layer is converted into a wiring formed using at least one of the regions substantially projected onto an actual wiring layer including a plurality of wiring layers. The circuit configuration is optimized based on the prediction results while predicting the characteristics.

The circuit configuration may be optimized by temporary wiring based on the temporary physical wiring layer. In this case, by laying wiring with various degrees of freedom in terms of circuit characteristics, the degree of freedom in circuit configuration is improved, and a circuit with excellent performance can be realized effectively and easily. The optimization of the circuit configuration here includes optimization of the characteristics of the elements that make up the circuit, and optimization of the circuit architecture by replacing it with a functionally equivalent circuit.

[0050] The integrated circuit design method according to the embodiment (18) is a method of connecting a laid-out circuit element to form a circuit block, by temporarily arranging tentative wiring used virtually at the time of design. Lay it on the wiring layer. Arithmetic means determines whether the characteristics of the circuit block formed according to the laying mode of the temporary wiring satisfy desired characteristics, and replaces the temporary wiring laid in the temporary physical wiring layer with the actual wiring in which the actual wiring is laid. Deployed as actual wiring on the wiring layer. An example of this mode can be understood from the flowchart shown in FIG.

The deployment of temporary wiring on the actual wiring layer corresponds to temporary wiring laid on one temporary physical wiring layer. The actual wiring in the area where the circuit block determined to not satisfy the desired characteristics by the above determination is transferred to a plurality of actual wiring layers so that the circuit block satisfies the desired characteristics. The wiring may be laid again using the wiring of the wiring layer.

“Expanding” the wiring means transferring the temporary wiring of the temporary physical wiring layer to the real wiring layer corresponding to each temporary physical wiring layer, and using the transferred temporary wiring by a plurality of real wiring layers. Means to lay it. Further, “transfer” means to project the temporary wiring of the temporary physical wiring layer onto the actual wiring layer without changing the laying mode, but all the transferred wiring is the original temporary wiring. It is not necessary to have the same laying mode as the temporary wiring of the layer. In other words, when the integrated circuit is divided into several blocks for each function or for each section, it is only necessary that the wiring laying mode corresponding to each block is the same.

When it is necessary to relay the actual wiring realized by the transfer from the temporary wiring, the transfer using the actual wiring layer on which the actual wiring layer is laid and the actual wiring layer adjacent thereto is performed again. However, the wiring may be laid in substantially the same manner as the temporary wiring in the temporary physical wiring layer. In this case, almost the same wiring is laid between adjacent actual wiring layers, so that the wiring of the adjacent wiring layers can be easily connected in various forms such as parallel U and series by a via hole. S Speak.

According to this design method, circuit characteristics (characteristics such as wiring characteristics and capacitance between wires) that cannot be realized by using the wiring by the conventional wiring method, that is, using only the temporary wiring of the temporary physical wiring layer. Can be realized, and adjustment of circuit characteristics can be easily performed. In other words, the actual wiring on the actual wiring layer to which the data is transferred can be realized as a form using a plurality of actual wirings. can do.

Further, at this time, since the wiring is re-laid based on the wiring path of the temporary wiring in the temporary physical wiring layer, such circuit characteristics are adjusted without correcting the electrical connection mode by the wiring in the temporary physical wiring layer. be able to.

(19) According to this integrated circuit design method, the correspondence between the temporary physical wiring layer and the real wiring layer is determined for each of the plurality of divided sections by dividing the integrated circuit into a plurality of sections. You can make a difference. An example of this embodiment is shown in FIGS. According to this design method, wiring is developed from the temporary physical wiring layer to the real wiring layer for each section, so that desired circuit characteristics can be efficiently realized. That is, in the layout design, the wiring is not always laid almost uniformly over all the regions of each wiring layer, and a region where the wiring is not laid is often formed. Therefore, in this design method, by performing the above-described development for each section, the number of actual wiring layers to be developed is increased in a section including more temporary physical wiring layers in which no wiring is laid, thereby increasing the number of integrated circuits. The final increase in the number of wiring layers can also be suitably suppressed.

(20) In addition, this design method is used in the case where the direction of laying out the wiring after the development from the temporary wiring to the actual wiring is different in the adjacent sections due to the division of the sections. Wiring for connecting across sections may be laid near the division boundary while maintaining the connection mode at the time of temporary wiring by using arithmetic means based on development from a temporary physical wiring layer. An example of the design method of this integrated circuit can be understood from FIG. 6, FIG. 17, and FIG.

In other words, as a result of dividing the section and making the correspondence between the temporary physical wiring layer and the actual wiring layer different for each section, and developing the wiring of the temporary physical wiring layer to the actual wiring of the real wiring layer, the wiring When the laying directions are different between adjacent sections, wiring for connecting the adjacent sections is maintained by using arithmetic means while maintaining the connection mode at the time of wiring in the temporary physical wiring layer. On the other hand, it may be laid as actual wiring formed by expanding from the temporary physical wiring layer to a plurality of actual wiring layers.

When the above-described development is performed for each section in the above-described manner, the manner in which a plurality of actual wiring layers are developed to the actual wiring is not necessarily the same between adjacent sections. For example, the wiring direction may be different between adjacent sections. At these locations, it may be difficult to connect the wiring between these compartments directly to one another. Therefore, it is necessary to maintain the connection form of the same temporary physical wiring layer with the temporary wiring even after it has been deployed to the actual wiring. By laying in such a manner, the connection between the two sections can be suitably performed.

An integrated circuit according to one embodiment relates to an integrated circuit having a multilayer wiring structure formed on a substrate, and has a feature in a wiring configuration laid in a multilayer wiring layer. The features are as follows. [0058] A unit interval is defined in advance for each wiring layer. The wiring is laid on the wiring layer in such a manner that the spacing between the wirings is an integral multiple of a predetermined unit spacing. Therefore, the wirings of one wiring layer are laid in parallel with each other and in the same laying direction. In addition, adjacent wiring layers are provided with regions in which wiring directions are the same. The first wiring is laid on one of the adjacent wiring layers in which such conditions are set, and the second wiring is laid on the other wiring. In this integrated circuit, the electrical characteristics of the wiring are adjusted by laying these wiring elements in various modes.

The following is an example of an embodiment of an integrated circuit configured using such wirings and a design method thereof.

[0059] The integrated circuit according to the embodiment (21) is an integrated circuit having a multilayer wiring structure formed on a substrate, and the interval between adjacent wirings is a unit defined in advance for each wiring layer. There is a region in which a plurality of wirings are laid in parallel with each other in a manner of being an integral multiple of the interval. In this integrated circuit, the region may include at least a pair of adjacent wiring layers in which wiring directions are the same. FIG. 45 shows an example of this embodiment.

Since this integrated circuit has adjacent wiring layers in which the wiring laying directions are the same, the unit spacing between adjacent wiring layers can be easily approximated. Therefore, electrical connection between these adjacent wiring layers can be easily performed.

In addition, by providing the wiring layers adjacent to each other, it is possible to avoid or suppress electrical interference with other wirings generated when wiring is laid in an intermediate layer. For this reason, various problems associated with miniaturization can be easily dealt with, and as a result, more efficient design can be performed.

Further, in the above-mentioned area, since the wiring laying interval is set to an integral multiple of a predetermined unit interval, the wiring at the time of designing the integrated circuit can be easily performed according to a regular pattern. . Therefore, particularly in the case where the connection in the above-mentioned area is performed by the automatic wiring tool, the programming of the tool can be simplified, and the processing at the time of connection by the tool can be simplified.

It is desirable that a logic circuit of an integrated circuit be formed in this region. to this On the other hand, memory, analog circuits, I / O (input / output)

) A circuit or the like may be formed.

(22) In this integrated circuit, the unit interval predetermined for each wiring layer may be set to be substantially the same in the pair of adjacent wiring layers. FIG. 45 shows an example of this embodiment.

According to this integrated circuit, electrical connection of wiring between these wiring layers can be easily performed in order to make the unit intervals substantially the same in adjacent wiring layers.

[0061] (23) In this integrated circuit, a plurality of wirings may be laid on the pair of adjacent wiring layers on the pair of adjacent wiring layers. The plurality of wirings to be provided may be laid with offset so that the projections on the substrate do not overlap each other. FIG. 46 shows an example of this embodiment.

[0062] This means, for example, a case in which the wiring of two adjacent wiring layers, which are laid at twice the unit spacing, are offset by the unit spacing. . According to this integrated circuit, the distance between adjacent wirings can be increased in the same wiring layer, so that the capacitance between adjacent wirings can be reduced, and crosstalk noise can be suppressed. In addition, when attention is paid to the wiring on one wiring layer, since there is no wiring in the wiring layer above or below, the wiring can be directly connected to the wiring further above or below via a via hole. As a result, the time and load required to calculate the connection path in the automatic wiring tool can be reduced.

(24) In this integrated circuit, two adjacent wirings are laid on one of the pair of adjacent wiring layers. One of the two adjacent wirings may be laid so that the distance between the two adjacent wirings is substantially longer by switching to the other wiring layer via the via hole. . FIG. 47 shows an example of this embodiment.

According to this integrated circuit, it is possible to minimize the portion where a pair of wirings are adjacent to each other in the same wiring layer, and furthermore, it is possible to reduce the capacitance between the pair of wirings appropriately. Become like Also, by placing the wiring layers adjacent to each other, wiring It is possible to avoid and suppress electrical interference with other wiring that occurs when the cable is laid.

(25) In this integrated circuit, a signal transmission wiring and a potential fixing first wiring are laid adjacent to each other on one of the pair of adjacent wiring layers. The other wiring layer is laid so as to include a second wiring force S for fixing potential and a region formed by projecting the signal transmission wiring onto the other wiring layer. Alternatively, the first and second wirings may be electrically connected to form a shield wiring of the signal transmission wiring. FIG. 48 shows an example of this embodiment.

According to this integrated circuit, since the signal transmission wiring and the shield wiring are adjacent to each other and no other wiring is laid in the intermediate wiring layer, it is possible to configure a shield wiring that does not significantly impair wiring resources. This makes it easy and effective to take measures against crosstalk and electromagnetic interference (EMI).

The integrated circuit according to the embodiment (26) is an integrated circuit having a multilayer wiring structure formed on a substrate, and one of a pair of adjacent wiring layers has a signal Propagation wiring and first potential fixing wiring are laid in parallel and adjacent to each other. On the other wiring layer, a second wiring for fixing a potential is laid so as to cover a region formed by projecting the wiring for signal propagation to the other wiring layer, and And the second wiring is electrically connected to form a shield wiring of the signal transmission wiring. FIG. 48 shows an example of this embodiment.

According to this integrated circuit, since the signal transmission wiring and the shield wiring are adjacent to each other and no other wiring is laid in the intermediate wiring layer, it is possible to configure the shield wiring without significantly impairing the wiring resources. This makes it easier to take countermeasures against crosstalk and electromagnetic interference (EMI).

(27) An integrated circuit designing method according to one embodiment is a method for designing an integrated circuit having a multilayer wiring structure formed on a substrate, and connects circuit elements laid out. For this purpose, wiring is laid on a plurality of wiring layers using an automatic wiring tool. This automatic wiring rule sets an area in which the wiring direction is the same between adjacent wiring layers, and sets the wiring of the adjacent wiring layer in the area to an interval of an integral multiple of a unit interval defined in advance. Laying I'm sorry. FIG. 49 and FIG. 50 show an example of this embodiment.

[0070] According to this design method, in order to perform connection while setting adjacent wiring layers having the same wiring laying direction, the laying interval of the wiring laid in parallel with each other is set to the unit interval. When it is set to an integral multiple of, it is easy to approximate this for the unit spacing of wiring layers that are in P contact. For this reason, electrical connection between the wiring layers in P contact can be easily performed.

. In addition, since there is no intermediate wiring layer between adjacent wiring layers, it is possible to prevent the electrical connection between adjacent wiring layers from interfering with other wiring. For this reason, various problems associated with miniaturization can be easily dealt with, and more efficient design can be achieved.

(28) In this integrated circuit design method, the automatic wiring tool sets the wiring laid on one wiring layer of the adjacent wiring layers in the area to the wiring laid on the other wiring layer. Thus, the wiring may be laid in such a manner that it is offset in a direction perpendicular to the laying direction in a range smaller than the wiring laying interval. FIG. 46 shows an example of this embodiment.

According to this design method, the distance between adjacent wirings can be increased in the same wiring layer, so that the capacitance between adjacent wirings can be reduced and crosstalk noise can be suppressed. In addition, when attention is paid to the wiring on one wiring layer, there is no wiring in the wiring layer above or below the wiring layer, so that the wiring can be directly connected to the wiring in the further upper or lower layer via the via hole. As a result, the time and load required to calculate the connection path in the automatic wiring tool can be reduced.

(29) In this integrated circuit design method, the automatic wiring tool sets a wiring layer in which wiring is to be laid in parallel with each other in a range in which wiring for which electric characteristics need to be adjusted is laid. You can use it as an area.

According to this design method, by providing a region where the wiring laying direction is the same between the adjacent wiring layers, the unit spacing between the adjacent wiring layers can be approximated and the distance between adjacent wiring layers can be quickly reduced by an electrical distance between the wiring layers. Connection can be made easily. In addition, by making the wiring layers adjacent to each other, it is possible to avoid or suppress electrical interference with other wirings that occurs when wiring is laid in an intermediate layer. This makes it possible to easily adjust the electrical characteristics of the wiring for which the adjustment of the electrical characteristics is desired, and thus to achieve a more efficient design. Will be able to do.

[0073] (30) In this integrated circuit design method, when laying wiring for signal propagation for which low noise is required as an electrical characteristic in the area, the automatic wiring tool may include one wiring in the area. A signal propagation wiring is laid on the layer, and functions as a shield wiring in a mode that includes the projection of the signal propagation wiring on a wiring layer adjacent to one wiring layer and having the same wiring laying direction. A wiring for fixing the potential may be laid. FIG. 48 shows an example of this embodiment.

According to this design method, since the shield wiring is provided in the wiring layer adjacent to the signal transmission wiring, interference with the wiring in other wiring layers can be reduced. As a result, it is possible to configure a shield wiring that does not significantly damage the wiring resources, and it is possible to easily perform measures against crosstalk and electromagnetic interference (EMI).

[0074] Note that any combination of the above-described components and any conversion of the expression of the present invention between a method, an apparatus, a system, and the like are also effective as embodiments of the present invention. These integrated circuits are more specifically realized by the embodiments described below.

(First Embodiment)

Hereinafter, a first embodiment in which an integrated circuit and a method for designing the same according to the present invention are applied to a semiconductor integrated circuit and a method for designing the same will be described with reference to the drawings.

FIG. 1 shows a configuration of a semiconductor integrated circuit according to the present embodiment. The semiconductor integrated circuit 1 shown in FIG. 1A includes a logic circuit unit 2 and an analog circuit unit 3. In the present embodiment, the logic circuit unit 2 is a part designed using an automatic placement and routing tool.

First, the configuration of the wiring layer of the semiconductor integrated circuit according to the present invention will be described. Since the automatic wiring tool lays out wiring on a predetermined grid, the following wiring laying intervals are considered to correspond to grid intervals. FIG. 1 (b) shows the wiring of the (n + 1) th wiring layer of the logic circuit section 2, and FIG. 1 (c) shows the wiring of the nth wiring layer of the logic circuit section 2. Shown respectively. As shown in Fig. 1 (b), each wiring of the (n + 1) th wiring layer is provided in parallel with each other, and the wiring laying interval is set to an integral multiple of a predetermined unit interval Pa. Has been done. Also, as shown in FIG. 1 (c), the wiring of the n-th wiring layer is provided in parallel with each other. The wiring interval is set to an integral multiple of a predetermined unit interval Pb.

That is, for example, in the (n + 1) th wiring layer, between the wiring Lai and the wiring La2 and between the wiring La2 and the wiring La3, the wiring laying interval is “1” times the unit interval Pa. ing. Also, between the wiring La3 and the wiring La4, the wiring laying interval is "2" times the unit interval Pa.

In the (n + 1) -th and n-th wiring layers that are adjacent wiring layers, the wiring laying direction (the signal propagation direction in the case of the signal line) is changed. They are the same as each other. In the (n + 1) -th and n-th wiring layers adjacent to each other, the unit spacing Pa and the unit spacing Pb are the same. Further, in the (n + 1) -th and n-th wiring layers, which are adjacent wiring layers, a wiring of any one wiring layer projected on the other wiring layer is the same as the other wiring layer. It is the same as the wiring in the wiring layer. That is, for example, the wiring La4 of the (n + 1) th wiring layer vertically projected onto the nth wiring layer is the same as the wiring Lb4.

In the semiconductor integrated circuit according to the present embodiment, the (n)

+1) The electrical characteristics of the wiring are adjusted by configuring any of the wirings shown in FIGS. 2 to 4 described below using the wiring layers of the nth and nth layers.

FIG. 2 will be described. FIGS. 2A and 2B show, for example, the wiring La4 and the wiring Lb4 shown in FIG. Here, the surface of each wiring layer is a plane extending in the X direction and the y direction, and the wiring laying direction is the X direction. FIG. 2 (c) shows that each of the wiring La4 and the wiring Lb4 has the same shape as the vertical projection of each other as described above. Then, as shown in FIG. 2D, the wiring La4 and the wiring Lb4 are electrically connected to each other by plugs pgl and pg2 formed in the via holes at a plurality of locations (B1 and B2).

[0081] Accordingly, the wirings electrically connected in parallel to each other from one of the predetermined two places Pl and P2 defined in the (n-1) -th wiring layer A single signal propagates through each of La4 and wiring Lb4. For details, PI which is the connection point of the wiring Lcl and the wiring Lb4 of the (n-1) th wiring layer by the plug pg3, the wiring Lc2 and the wiring Lb4 of the (n-1) th wiring layer Wiring La4 and the connection between P2 which is the connection point by pg4 A signal propagates through each of the lines Lb4.

[0082] For this reason, the resistance of the wiring can be reduced without increasing the effective wiring width, that is, the wiring width of the wiring perpendicularly projected to the substrate surface of the integrated circuit. In particular, since the surface area of the wiring itself is increased as a whole by paralleling a plurality of wirings, the increase in resistance due to the skin effect can be reduced. By reducing such resistance, the speed of the integrated circuit can be increased and the power consumption can be reduced. By applying such wiring to power wiring, it is possible to take measures against electrification port migration and IR drop.

Next, FIG. 3 will be described. FIGS. 3A and 3B show, for example, the wiring La3 and the wiring Lb3 shown in FIG. Here, the surface of each wiring layer is a plane extending in the X direction and the y direction, and the wiring laying direction is the X direction. FIG. 3C shows that each of the wiring La3 and the wiring Lb3 has the same shape as the vertical projection of each other as described above.

As shown in FIG. 3 (d), the wiring La3 and the wiring Lb3 are connected in series by the plug pg5 in the via hole in such a manner that the signal propagation direction is reversed. In order for the signal to propagate through the wires connected in series in such a manner that the signal propagation direction is reversed, the effective wire length (the vertical projection of the wire on the substrate surface of the integrated circuit) is used. The wiring resistance can be increased without increasing the wiring length).

Next, FIG. 4 will be described. FIGS. 4A and 4B show, for example, the wirings La2 and Lai and the wirings Lb2 and Lbl shown in FIG. Here, the surface of each wiring layer is a plane extending in the x direction and the y direction, and the wiring laying direction is the X direction. FIG. 4C shows that each of the wiring La2 and the wiring Lb2 and each of the wiring Lai and the wiring Lbl have the same shape as the vertical projection of each other as described above.

Then, as shown in FIG. 4D, the wiring La2 provided in the (n + 1) th wiring layer, the wiring Lb2 provided in the nth wiring layer, and the power via hole are provided. Are electrically connected to each other by the plug pg6. Further, as shown in FIG. 4 (e), the wiring Lai provided in the (n + 1) th wiring layer and the wiring Lbl provided in the nth wiring layer are provided in the via hole. Connected to each other by plug pg7. Here, one of the wiring La2 and the wiring Lb2 and one of the wiring Lai and the wiring Lbl function as a dummy wiring in which one side is open. That is, these dummy wirings are connected at one end to other wirings by the plugs Pg6 and Pg7, but are open at the other ends. Therefore, even if the other wiring is a signal transmission wiring, the dummy wiring does not become a signal propagation path. Also, even if the other wiring is a power supply wiring, the dummy wiring does not become a power supply path.

With such a configuration, the capacitance between the wiring Lb2 and the wiring Lbl provided in a region where the wiring La2 and the wiring Lai are projected is added to the capacitance between the adjacent wiring La2 and the wiring Lai in the (n + 1) th wiring layer. In addition, the capacitance between adjacent wirings can be increased. In this case, the capacity can be increased without reducing the wiring interval or increasing the wiring length, so that the design rule is restricted and the resistance is increased. Absent.

[0089] If the wiring La2 and the wiring Lai are a wiring fixed to the power supply voltage and a wiring grounded, respectively, it is effective in stabilizing the power supply. That is, according to the above-described configuration, it is possible to appropriately suppress the noise from being mixed into the wiring, so that it is possible to preferably suppress the electromagnetic interference.

As described above, in the present embodiment, by providing the wiring having the configuration shown in FIGS. 2 to 4, it is possible to adjust the resistance value of the wiring and the capacitance between the wirings. For this reason, various problems associated with miniaturization can be easily dealt with without developing new materials used for integrated circuits.

The wiring having the configuration shown in FIGS. 2 to 4 can be easily realized by using the wiring laid using the automatic wiring tool. That is, the wiring of a predetermined wiring layer (temporary physical wiring layer) laid using the automatic wiring tool is replaced with a plurality of wirings of a plurality of wiring layers (real wiring layers) having the same shape as each other. It can be easily realized by conversion. In particular, when applying such a design method, the wiring structure with the above features can reverse the wiring of multiple real wiring layers to the wiring of the temporary physical wiring layer consisting of one original layer. Structure. In other words, the above-mentioned wiring structure is reversible in which the conversion of the wiring path into the wiring of a plurality of real wiring layers and the conversion of the wiring of the plurality of real wiring layers to a lesser extent and the inverse conversion to the wiring of the wiring layer are possible. It has a simple structure. Therefore, the wiring structure In the trial and error of the above-mentioned conversion and the inverse conversion, it is always necessary to use the history information of the interrelationship before and after the conversion without constantly using the original laying state of the temporary physical wiring layer. .

Hereinafter, a procedure for designing an integrated circuit having such a wiring configuration will be described in detail.

FIG. 5 is a block diagram showing a configuration of an integrated circuit design support apparatus according to the present embodiment. This support device is configured as a device that supports the design of the standard cell system.

First, the function of each unit constituting the support apparatus will be described.

[0093] The library 10 is a part in which performance information of the function cells, such as cell information of various function cells to be included in the integrated circuit, delay information of the function cells, and constraint information on setup and hold time, is stored. . Here, various functional cells include logical operation elements (logical product, logical sum, exclusive logical sum, exclusive logical product, negation, etc.), flip-flops, memories such as RAM, analog devices such as A / D, and the like. This is a circuit formed by using. Further, the library 10 is also a part in which information on the layout of the functional cells, such as the area information of each functional cell, is stored.

[0094] The design specification storage section 12 is a section for storing information on the function and structure of the integrated circuit described in, for example, a hardware description language (HDL). For details, circuit information expressed by RTL (resistance transfer level), gate level, etc., and timing such as operating frequency

This is a part in which information such as power and power conditions are stored. Here, for example, the circuit information at the gate level is a netlist composed of the types and numbers of cells used and the logical connection information from the cells defined in the library 10.

[0095] Further, the process parameters 14 include element characteristics according to designated design rules (rules regarding the minimum processing accuracy in the manufacturing process, rules specifying the element size and the minimum wiring interval, etc.), and the wiring characteristics for each material. This is a part in which information relating to etc. is stored.

[0096] The temporary physical wiring layer rule 16 is a part in which rules for converting wiring of the temporary physical wiring layer, which is a wiring layer to be connected by the automatic wiring tool, into wiring of the actual wiring layer are stored. That is, a route for converting a predetermined wiring into a wiring having the structure shown in FIGS. 2 and 3 above. A rule for converting a pair of adjacent wires into a wire having the structure shown in FIG. 4 is stored.

The library 10, the design specification storage unit 12, the process parameters 14, and the provisional physical wiring layer rules 16 are provided with storage devices such as a hard disk device.

[0097] On the other hand, the circuit variable calculation unit 20 is a part that calculates circuit variables of wiring converted by the rules stored in the tentative physical wiring layer rule 16 based on externally input data.

[0098] The automatic placement unit 22 and the automatic routing unit 24 as automatic placement and routing tools are parts for performing layout design. That is, the automatic arranging unit 22 is a unit for automatically arranging the functional cells, and the automatic wiring unit 24 is a unit for connecting the arranged functional cells. The automatic arrangement of the functional cells and the connection between the arranged functional cells are performed using the layout data of the library 10 corresponding to the functional cells.

[0099] The netlist of the circuit for which the wiring route is generated by the automatic wiring unit 24 is supplied to the timing analysis unit 30. This netlist has a hierarchical structure, and is composed of a netlist in a functional block composed of each functional cell and a netlist between functional blocks.

[0100] The timing analysis unit 30 is a part that performs timing analysis based on the netlist, the process parameters 14, and the provisional physical wiring layer rules 16. The circuit variable determination unit 32 is a part that determines the circuit variable of the wiring on the temporary physical wiring layer based on the above timing analysis. The wiring layer developing unit 34 is a part that develops a temporary physical wiring layer into an actual wiring layer that is an actual wiring layer of the integrated circuit based on the determined circuit variables.

[0101] Further, the mask calculation unit 40 is a unit that creates data (mask data) serving as a mask pattern used in manufacturing an integrated circuit based on data (layout data) serving as a final layout pattern.

[0102] The automatic placement unit 22, the automatic wiring unit 24, the timing analysis unit 30, the circuit variable determination unit 32, the wiring layer development unit 34, and the mask calculation unit 40 include a semiconductor device that stores a program related to the processing to be performed. It is configured to include a storage device such as a memory and a hard disk device and a computer. [0103] In addition, the input unit 50 is a unit that includes various input devices such as a touch pen, a keyboard, and a mouse, and that inputs various information and commands for layout design. The image display section 52 is a section for visually displaying the input information, the layout diagram, and the like. On the other hand, the control unit 54 includes the image display unit 52, the above-described automatic placement unit 22, automatic wiring unit 24, timing analysis unit 30, circuit variable determination unit 32, wiring layer development unit 34, mask calculation unit 40, and the like. This is the part that controls the operation.

Next, a procedure for designing an integrated circuit according to the present embodiment, which is performed using the design support apparatus having such a configuration, will be described. FIG. 6 shows a procedure for designing an integrated circuit that is useful in this embodiment.

In this series of processing, first, in step S100, a temporary physical wiring layer is defined as a wiring layer to be used when automatic wiring is used after automatic cell placement and wiring is performed. That is, the number of wiring layers that can be used as temporary physical wiring layers is set through the input unit 50 due to restrictions at the time of manufacturing the integrated circuit. The number of wiring layers is set to be equal to or less than the maximum number of actual wiring layers determined by the above-mentioned restrictions at the time of manufacturing.

In the following step S110, layout design is performed using the temporary physical wiring layer defined in step S100. Here, first, the layout information on the functional cells stored in the library 10 and the gate-level circuit information stored in the design specification storage unit 12 are input to the automatic arrangement unit 22. Then, the automatic placement unit 22 performs automatic placement of functional cells based on the gate-level circuit information. Next, in the automatic wiring unit 24, connection between the function cells is performed using the connection information of the function cells for which arrangement has been completed stored in the design specification storage unit 12.

Next, in step S 120, the circuit variables of the integrated circuits for which the above-mentioned connections have been completed are determined by the circuit-variable determining unit 32. Here, each wiring of a predetermined temporary physical wiring layer that satisfies design constraints such as timing is converted into a plurality of wirings that are wirings of a plurality of wiring layers (real wiring layers) and have the same shape as each other. The circuit variables that minimize the number of actual wiring layers among those realized in this way are determined.

[0107] Specifically, for example, first, the timing analysis is performed by the timing analysis unit 30 using a circuit variable when the temporary physical wiring layer is not expanded to the actual wiring layer, and the presence or absence of a timing violation is analyzed. Analyze.

When a timing violation part occurs depending on the circuit variable, the timing analysis is performed again by using a circuit variable obtained when a predetermined temporary physical wiring layer is expanded to an actual wiring layer. That is, first, when the electrical connection by the wiring provided in the temporary physical wiring layer is converted into the wiring of the actual wiring layer including a plurality of wiring layers in which the projection of each wiring layer is the same as the wiring of its own wiring layer. Set the circuit variables of That is, the characteristics obtained when the electrical connection by the predetermined wiring of the temporary physical wiring layer can be realized by, for example, the wiring over two layers shown in FIGS. 2 to 4 are set as the above circuit variables. Is done.

For example, the layout in the temporary physical wiring layer corresponding to the circuit information shown in FIG. 7A is as shown in FIG. 7B and FIG. Suppose it is set to R. At this time, when converted to the wiring of the structure shown in Fig. 2, the resistance value becomes R / 2, and when converted to the wiring of the structure shown in Fig. 3, the resistance value becomes 2R. Become. Therefore, when the wiring of the temporary physical wiring layer is converted into the wiring of the real wiring layer having the two wiring layers having the structure shown in FIGS. 2 and 3, the resistance values as circuit variables are R / 2 and 2R. Become. It should be noted that a part of these wirings, which do not correspond to the entire length of the wiring in the provisional physical wiring layer shown in FIGS. It is also possible to convert In this case, the resistance value as a circuit variable can be set between R / 2-R and R-2R.

[0110] Further, for example, a plan view of a layout in the provisional physical wiring layer corresponding to the circuit information shown in Fig. 8 (a) is shown in Fig. 8 (b), and its cross-sectional views are shown in Figs. It is assumed to be as shown in Fig. 8 (d). At this time, when the wiring is converted into the wiring having the structure shown in FIG. 4, the capacitance between the pair of wirings is approximately doubled.

[0111] The number of such deployable real wiring layers is determined based on the maximum number of real wiring layers and the number of temporary physical wiring layers, which are determined by the restrictions at the time of manufacturing and the like. In other words, if the maximum number of actual wiring layers is six and the number of temporary physical wiring layers is five, then any one of the temporary physical wiring layers will have two real layers. It can be developed in the wiring layer.

The circuit variables are calculated by the circuit variable calculating section 20 based on the maximum number of wiring layers and the number of provisional physical wiring layers input from the input section 50. And this The circuit variables of the temporary physical wiring layer are stored in the temporary physical wiring layer rule 16 described above. In order to expand the range of the above-mentioned circuit variables, it is desirable to set the number of temporary physical wiring layers small.

[0113] When deploying such actual wiring layers, it is desirable to gradually increase the number of actual wiring layers to be developed, such as two or three layers. Then, the actual wiring layer that realizes the circuit variables at the time when the timing violation is eliminated is determined as the actual wiring layer to be used finally.

[0114] As described above, the number of actual wiring layers is increased stepwise, and instead, all timing analysis is performed by circuit variables corresponding to all possible actual wiring layers. The circuit variable may be determined based on the result.

[0115] In the following step S130, the wiring of the temporary physical wiring layer is developed to the wiring of the actual wiring layer that realizes the circuit variables determined in step S120. That is, for example, the wiring shown in FIG. 7B and FIG. 7C is converted into the two-layer wiring shown in FIG. 2 or FIG. Further, for example, the pair of wires shown in FIGS. 8B to 8D is converted to the pair of wires shown in FIG.

[0116] Next, in step S140, the validity of the layout of the integrated circuit in which the connection using the temporary physical wiring layer is made in step S110 and the portion is modified to the real wiring layer in step S130 is checked. . Here, for example, in addition to the above-described timing constraints, it is desirable to consider constraints and the like at the time of manufacturing a few. Such a restriction is, for example, an antenna rule that prevents a gate insulating film from being destroyed by a charge accumulated in a gate connected to a transistor in a manufacturing process of the integrated circuit. This is a restriction, for example, in the manufacturing process, when the wiring connected to the gate does not exceed a predetermined wiring length.

[0117] Note that this antenna rule may be considered in step S110 or step S120. In this case, the conversion from the wiring in the temporary physical wiring layer to the wiring in the actual wiring layer is performed according to the antenna rule. For example, when the wiring shown in FIG. 7 is converted to the wiring having the wiring structure shown in FIG. 2, when the wiring Lb4 of the n-th wiring layer is formed, the gate insulation of the transistor connected to the wiring LC2 when the wiring Lb4 is formed. When dielectric breakdown of the film occurs To do. In this case, in the manufacturing process of the wiring of the n-th wiring layer, the connection between the wiring LC2 and the wiring Lb4 is avoided by shortening the length of the wiring Lb4. Then, in the manufacturing process of the (n + 1) th wiring layer, the wiring Lb4 and the wiring La4 are connected, and the wiring La4 and the wiring LC2 are connected. Accordingly, in the case where the wiring Lb4 is connected to the drain and the source of the transistor by manufacturing the wiring of the (n + 1) th wiring layer, insulation breakdown can be avoided.

Then, if it is determined in step S140 that the integrated circuit is appropriate, the mask calculation section 40 performs mask pattern data (mask data) based on data (layout data) serving as a layout pattern. ).

That is, the mask of the wiring La4 of the (n + 1) th wiring layer and the wiring Lb4 of the nth wiring layer shown in FIG. 2 are the same as those shown in FIG. 9 (a). Is the mask data. Then, the mask of the via hole for connecting the wiring La4 of the (n + 1) th wiring layer and the wiring Lb4 of the nth wiring layer shown in FIG. 2 is shown in FIG. 9 (b). It will be shown.

Also, the mask of the wiring La3 of the (n + 1) th wiring layer and the wiring Lb3 of the nth wiring layer shown in FIG. 3 is a single mask shown in FIG. 9 (c). It becomes mask data. The via hole mask for connecting the wiring La3 of the (n + 1) th wiring layer and the wiring Lb3 of the nth wiring layer shown in FIG. 3 is shown in FIG. 9 (d). It becomes what is shown in.

Further, the mask of the pair of wirings La2 and Lai of the (n + 1) th wiring layer and the pair of wirings Lb2 and Lbl of the nth wiring layer shown in FIG. This is the single mask data shown in (e). Then, a via hole mask for connecting the pair of wirings La2 and Lai of the (n + 1) th wiring layer and the pair of wirings Lb2 and Lbl of the nth wiring layer shown in FIG. Is as shown in FIG. 9 (f).

Note that these mask data are subject to restrictions from the manufacturing process of the integrated circuit. That is, for example, when manufacturing a wiring having a predetermined wiring width and a wiring interval in the integrated circuit, a mask in which the wiring width and the wiring interval are converted to a predetermined value according to the manufacturing process is used. For this reason, in the mask shown in FIG. 9, the wiring width, the wiring interval, and the like may be different from those of the layout data designed by step S140. As described above, according to the present embodiment, the mask of the (n + 1) th wiring layer and the mask of the nth wiring layer can be made common.

Further, in the present embodiment, after the placement and routing using the temporary physical wiring layer is performed, the electrical connection by the wiring of the temporary physical wiring layer is realized by the wiring of the plurality of real wiring layers. Therefore, it is possible to adjust the circuit variables so as to satisfy the design constraints while avoiding changes in the wiring layout. Therefore, it is possible to reduce the trial and error due to the automatic wiring unit 24, and it is possible to reduce the calculation load of the automatic wiring tool.

According to the embodiment described above, the following effects can be obtained.

(1) Wirings La 4, which are used for signal propagation and are provided in a plurality of wiring layers in parallel with each other and electrically connected to each other via via holes at a plurality of locations. Added Lb4. As a result, it is possible to reduce the wiring resistance without increasing the effective wiring width, that is, the wiring width of the wiring occupying the substrate surface of the integrated circuit.

(2) By providing the wirings La3 and Lb3 connected in series in such a manner that the signal propagation directions are reversed, the integrated circuit can adjust the signal delay amount and generate the reference potential. , The resistance can be adjusted in the direction of increasing the resistance.

[0127] (3) A pair of adjacent wirings La2 and Lai provided in a predetermined wiring layer and a pair of wirings La2 and Lai are provided in a region where the pair of wirings La2 and Lai are projected on a common wiring layer different from the predetermined wiring layer. The interconnects Lb2 and Lbl were connected to each other via via holes. Thus, the capacitance between adjacent wirings can be increased.

(4) Wiring directions of wirings of two adjacent wiring layers exemplified as the (n + 1) th layer and the nth layer are the same, and the wiring of any one wiring layer with respect to the other wiring layer is The projection was the same as the wiring provided on the other wiring layer. Therefore, a common mask can be used for the two layers in contact with each other.

[0129] (5) After the placement and routing is performed using the temporary physical wiring layer, it is considered that the electrical connection by the wiring of this temporary physical wiring layer is realized by the wiring of a plurality of real wiring layers. As a result, it is possible to realize circuit characteristics that cannot be realized by wiring using a conventional wiring method that does not use such a wiring conversion method. Therefore, adjustment of circuit characteristics can be easily performed. (Second Embodiment)

Hereinafter, a second embodiment in which the integrated circuit and its design method according to the present invention are applied to a semiconductor integrated circuit and its design method will be described with reference to the drawings, focusing on the differences from the first embodiment. explain.

Also in the present embodiment, in the (n + 1) th wiring layer and the nth wiring layer of the logic circuit section 2, the wiring laying interval is set to an integral multiple of the common unit interval Pa. ing. Also, in the present embodiment, as for the predetermined wiring of the (n + 1) th wiring layer and the predetermined wiring of the nth wiring layer, these are projected onto the other wiring layer. Things match. However, in the present embodiment, the wiring is not necessarily formed in a region where the wiring of the (n + 1) th wiring layer or the wiring of the nth wiring layer is projected on the other wiring layer. Not necessarily. This is because the (n + 1) th wiring layer and the nth wiring layer are further provided with a pair of wirings having the configuration shown in FIG. 10 or FIG.

[0132] Here, Fig. 10 will be described. The (n + 1) th wiring layer shown in FIG. 10 (a) and the nth wiring layer shown in FIG. 10 (b) have a plane extending in the X and y directions, and The laying direction is the X direction. The wiring Lcl provided in the (n + 1) th wiring layer shown in FIG. 10A and the wiring Lc2 provided in the nth wiring layer shown in FIG. And the horizontal interval is the unit interval Pa. FIG. 10C shows a cross-sectional configuration of the wiring Lcl and the wiring Lc2 in the yz plane when the normal direction of the wiring layer is the z direction.

According to such a configuration, the wiring Lcl and the wiring Lc2, which are a pair of wirings that are closest to each other when the integrated circuit is projected onto the substrate surface, are provided in different wiring layers. become. As a result, the capacitance between the wiring Lcl and the wiring Lc2 can be suitably reduced without increasing the horizontal distance between the wiring Lcl and the wiring Lc2.

Next, FIG. 11 will be described. The (n + 1) th wiring layer shown in FIG. 11 (a) and the nth wiring layer shown in FIG. 11 (b) have a plane extending in the X direction and the y direction. The laying direction is the X direction. The wiring Ldl and the wiring Ld2 provided over the (n + 1) th and nth wiring layers shown in FIGS. 11A and 11B are flat with each other. It is provided in a row, and the laying interval is the unit interval Pa.

FIG. 11 (c) shows a cross-sectional configuration on the xz plane of the wiring Ldl when the normal direction of each wiring layer is the z direction. That is, the wiring Ldl is formed over the (n + 1) th wiring layer and the nth wiring layer, and both wirings are formed by the plug pg8 provided in the via hole between these wiring layers. The portions formed in the layers are electrically connected in series.

FIG. 11D shows a cross-sectional configuration on the xz plane of the wiring Ld2 when the normal direction of each wiring layer is the z direction. That is, the wiring Ld2 is formed over the (n + 1) th wiring layer and the nth wiring layer, and both wirings are formed by the plug pg9 provided in the via hole between these wiring layers. The portions formed in the layers are electrically connected in series.

The wiring Ldl and the wiring Ld2 are provided so that the (n + 1) th wiring layer and the nth wiring layer are alternately switched via via holes. Therefore, the portion where the wiring Ldl and the wiring Ld2 are horizontally adjacent in the same wiring layer can be reduced as much as possible, so that the capacity between the wiring Ldl and the wiring Ld2 can be appropriately reduced. Become. Further, since the wiring Ldl and the wiring Ld2 are provided so as to change wiring layers, the influence of the electrical coupling to the outside of the wiring Ldl and the wiring Ld2 is reduced.

In the present embodiment including the wirings of FIG. 10 and FIG. 11, in the processing of step S150 shown in FIG. 6, the mask data of the (n + 1) th wiring layer and the n-th Create mask data for each wiring layer separately.

That is, the mask for the wiring Lcl shown in FIG. 10 is as shown in FIG. 12 (a), and the mask for the wiring Lc2 in FIG. 10 is as shown in FIG. 12 (b). An example of a mask of a via hole between the (n + 1) th wiring layer and the nth wiring layer connecting these wirings Lcl and Lc2 to another wiring is shown in FIG. It will be as shown in c). On the other hand, the mask of the (n + 1) -th wiring layer of the wirings Ldl and Ld2 shown in FIG. 11 is as shown in FIG. 12D, and the n-th wiring of the wirings Ldl and Ld2 is shown in FIG. The layer mask is as shown in Fig. 12 (e). The wirings Ldl and Ld2 in the (n + 1) th wiring layer and the n-th layer FIG. 12F shows a mask of a via hole connecting the wirings Ldl and Ld2 in the second wiring layer.

As described above, in the present embodiment, in addition to the configuration shown in FIGS. 2 to 4, the wiring having the configuration shown in FIG. 10 and FIG. It can be reduced. In particular, since the capacitance between the wirings can be reduced, the speed of the integrated circuit can be reduced, the power consumption can be reduced, and the crosstalk noise can be suitably reduced.

[0141] In addition, in Figs. 14, 10, and 11, the case where the temporary physical wiring layer is developed into two real wiring layers is illustrated, but the present invention is not limited to this. That is, for example, as shown in FIG. 13 (a), it may be expanded to four actual wiring layers. In FIG. 13A, the wiring Lei and the wiring Le5 are formed in the first real wiring layer, the wiring Le3 is formed in the second wiring layer, and the wiring Le2 and the wiring Le6 are formed in the third wiring layer. The wiring Le4 is formed in the fourth wiring layer. The wiring Lei and the wiring Le2 have substantially the same projection as themselves, and are connected to each other via a via hole. Further, the wiring Le3 and the wiring Le4 have substantially the same projection as themselves, and are connected to each other via via holes. Further, the wiring Le5 and the wiring Le6 have substantially the same projection as themselves, and are connected to each other via via holes.

[0142] The wiring having the closest distance in the line width direction to the wiring Le4 except for immediately below the wiring Le4 is the wiring Le2 and the wiring Le6 provided in the wiring layer one layer below. . Except for the wiring Le3, the wiring having the closest distance in the line width direction except for the wiring Le3 is the wiring Lei and the wiring Le5 provided in the wiring layer one layer below. Therefore, the wirings Le4 and Le3 are set to reduce the capacitance between the wirings Le2 and Lei, which are the wirings having the closest distance in the line width direction, and the wirings Le6 and Le5.

Further, in FIG. 13B, the wiring Lf 1 and the wiring Lf 2 are connected in series, and the wiring Lf 2 and the wiring Lf 3 are connected in series in such a manner that the signal propagation directions are inverted. An example is shown.

According to the present embodiment described above, (1)-(3) and (5) of the first embodiment described above. In addition to the effect of), the following effect can be further obtained.

[0145] (6) The wiring Lcl and the wiring Lc2, which are a pair of wirings composed of wirings that are closest to each other and projected onto the substrate surface of the integrated circuit, are configured to have different wiring layers. Thus, the capacitance between the wiring Lc1 and the wiring Lc2 can be suitably reduced without increasing the horizontal distance between the wiring Lcl and the wiring Lc2.

(7) The wiring Ldl and the wiring Ld2 alternately switch between the (n + 1) th wiring layer and the nth wiring layer via the via hole. For this reason, the portion where the wiring Ldl and the wiring Ld2 are horizontally adjacent to each other can be reduced as much as possible, and the capacitance between the wiring Ldl and the wiring Ld2 can be reduced appropriately. It can be reduced.

(Third Embodiment)

Hereinafter, a third embodiment in which the integrated circuit and its design method according to the present invention are applied to a semiconductor integrated circuit and its design method will be described with reference to the drawings, focusing on the differences from the second embodiment. explain.

[0148] In the second embodiment, after the placement and routing is performed by the automatic placement and routing tool using the temporary physical wiring layer, the electrical connection by the wiring of the temporary physical wiring layer is performed by the real wiring including a plurality of wiring layers. The layout was designed in consideration of the realization with the layer wiring.

On the other hand, in the present embodiment, the layout is changed in order to improve the performance of the integrated circuit in which the layout has been realized (the integrated circuit in which layout data, mask data, and the like have already been designed). This is the case, for example, when (a) an already manufactured integrated circuit is found to have large characteristic variations and a low yield. (Mouth) When a change in performance, such as the operating frequency of an integrated circuit whose design has been completed or an existing integrated circuit that has already been manufactured, is requested. (C) For example, when designing an integrated circuit with a design rail of “0.18 zm” based on an existing integrated circuit with a design rule of “0.35 xm”, design an integrated circuit with a modified design rail. When adjusting the timing of a downsized integrated circuit that is similar to an existing off-the-shelf integrated circuit. And so on.

FIG. 14 shows a processing procedure for changing the layout of an integrated circuit according to the present embodiment. The process shown in FIG. 14 is performed using the design support device shown in FIG. It is. However, in this case, not all the configurations of the support device shown in FIG. 5 are used, and the usage of each functional block is slightly different. This will be pointed out when describing the processing procedure in FIG.

[0151] In this series of processing, first, in step S200, a rule for converting a wiring of a single wiring layer (temporary physical wiring layer) into a wiring of a plurality of real wiring layers is set as a temporary physical wiring layer rule. Define.

Here, first, the maximum number of wiring layers that can be used due to restrictions at the time of manufacturing the integrated circuit and the number of wiring layers of the integrated circuit for which the layout design has been completed are first determined by the input unit 5 shown in FIG. Entered through 0. Then, based on these differences, the circuit variable calculation unit 20 shown in FIG. 5 determines the number of wiring layers that can be expanded to actual wiring layers. For example, if the maximum number of wiring layers is “6” and the number of wiring layers of the integrated circuit for which the layout design has been completed is 5 ”, this is expanded to two actual wiring layers for one wiring layer. be able to. For example, if the maximum number of wiring layers is “6” and the number of wiring layers of the integrated circuit for which the layout design has been completed is “4”, each of the two wiring layers is changed to two actual wiring layers. Or one wiring layer can be expanded to three real wiring layers. When the actual wiring layer to be expanded is determined in this manner, a predetermined wiring is expanded in accordance with this, for example, to wiring having a configuration as exemplified in FIGS. 2 to 4, 10, 10, and 13. Constraints are defined.

Then, the circuit variable calculation unit 20 calculates a circuit variable based on the number of expandable actual wiring layers.

[0153] In the following step S210, among the wiring layers of the integrated circuit for which the layout design has been completed, a wiring layer that allows a change in the wiring laying mode is selected, and this is set as a temporary physical wiring layer. The instruction to make this specific wiring layer a temporary physical wiring layer is issued through the input unit 50 in FIG.

[0154] In the following step S220, the circuit variable of the wiring of the temporary physical wiring layer is determined by the circuit variable determination unit 32 shown in FIG. Here, a circuit variable that satisfies design constraints such as timing and minimizes the number of expansions from the temporary physical wiring layer to the actual wiring layer is determined. [0155] Specifically, for example, the timing analysis is performed while the number of actual wiring layers to be developed is gradually increased to two or three layers. Then, the actual wiring layer that realizes the circuit variables at the time when the timing violation has disappeared is determined as the finally used actual wiring layer.

[0156] As described above, the number of actual wiring layers is increased in a stepwise manner. Instead, timing analysis using each circuit variable corresponding to all possible actual wiring layers is performed. The circuit variable may be determined based on the result.

[0157] In the following step S230, the wiring of the temporary physical wiring layer is changed to the wiring of the actual wiring layer that realizes the circuit variable determined in step S220 by the wiring layer developing unit 34 shown in FIG. expand.

Next, in step S240, the validity of the layout of the integrated circuit having the portion modified in step S230 is confirmed. Here, it is desirable to consider, for example, some restrictions at the time of manufacturing in addition to the above timing restrictions.

[0159] Note that such design constraints may be considered in step S210 or step S220.

Then, if it is determined in step S240 that the integrated circuit is appropriate, in step S250, the mask calculation section 40 creates mask data based on the layout data.

When the layout data obtained by converting the wiring of the temporary physical wiring layer into the wiring of a plurality of real wiring layers is further changed, the converted wiring is It can also be dealt with by inversely converting to the wiring of FIG. Therefore, for such layout data, not only can the number of actual wiring layers be increased, but also the timing can be adjusted by reducing the number of actual wiring layers.

According to the present embodiment described above, in addition to the above (1)-(3), (6), and (7) in the second embodiment, the following effects can be obtained. Become.

[0163] (8) A wiring layer that allows a change in the wiring layout of an integrated circuit whose layout has been completed is a temporary physical wiring layer, and the electrical connection by the wiring of the temporary physical wiring layer is performed by a plurality of real wiring layers. I thought about realizing it with the wiring of. Therefore, it is possible to easily adjust the circuit characteristics of the integrated circuit for which the layout design has been completed. (Fourth Embodiment)

Hereinafter, a fourth embodiment in which the integrated circuit according to the present invention and its design method are applied to a semiconductor integrated circuit and its design method will be described with reference to the drawings, focusing on differences from the first and second embodiments. It will be described with reference to FIG.

In the first and second embodiments, after a layout design using a temporary physical wiring layer, a predetermined temporary physical wiring layer is expanded to an actual wiring layer, and this expansion is performed by a logical This was common in all areas of the circuit section 2. On the other hand, in the present embodiment, after the layout is designed by the automatic placement and routing tool using the temporary physical wiring layer, the area where the layout is designed by the automatic placement and routing tool (the logic circuit section 2 in FIG. 1 above) Is divided into a plurality of sections, and each of the divided sections can be separately developed into an actual wiring layer.

That is, when the above-described development is performed uniformly over the entire area of the logic circuit unit 2, the wiring is not necessarily laid almost uniformly over the entire area of each temporary physical wiring layer. Therefore, there is a possibility that an area where wiring is not laid will be formed. On the other hand, in the present embodiment, when considering realizing the electrical connection by the wiring of the temporary physical wiring layer by the wiring of a plurality of real wiring layers for each section, the expansion to the same real wiring layer is considered. The use of an area where no wiring is laid can also be considered. Therefore, it is possible to improve the circuit characteristics of the layout using the temporary physical wiring layer while reducing the redundancy due to the layout design.

FIG. 15 shows the overall configuration of the design support apparatus used in the present embodiment. In FIG. 15, members having the same functions as those of the design support apparatus shown in FIG. 5 are given the same reference numerals for convenience.

In FIG. 15, a section setting section 42 is provided. The section setting unit 42 sets not only the above-described sections but also sets a connection area between adjacent sections having different development modes on the actual wiring layer, and performs an electrical connection between both sections. The partition setting unit 42 also includes a computer and a storage device such as a semiconductor memory or a hard disk device that stores programs related to the above-described processes, and a computer.

[0169] Here, the processing procedure of the layout design that is performed by using the design support apparatus and is focused on the present embodiment will be described in detail with reference to FIG. In this series of processing, first, in step S300, similarly to step S100 shown in FIG. 6, a wiring layer used when wiring is performed using an automatic wiring tool after automatic cell placement. Is defined as a temporary physical wiring layer. However, in the present embodiment, the number of deployable real wiring layers is determined based on the maximum number of wiring layers determined by the above-described restrictions at the time of manufacturing and the like, but this number is the same as the maximum number of wiring layers and the provisional physical layer. The difference from the number of wiring layers is not necessarily dealt with, and it is desirable that the number be larger than this.

In subsequent step S310, a layout design is performed using the temporary physical wiring layer defined in step S300.

When the layout design is completed in this way, in step S320, the area for which layout has been designed by the automatic placement and routing tool is divided into small sections by the section setting section 42 shown in FIG. 15 in the integrated circuit. To divide. That is, as exemplified in FIG. 17A, the logic circuit section 2 is divided into a plurality of rectangular sections (at in the figure).

In the following step S330, for the integrated circuit on which the connection has been completed, the circuit variable determination unit 32 determines circuit variables of the wirings related to the respective connections for each of the sections. Here, a circuit variable that satisfies design constraints such as timing and minimizes the number of developments from the temporary physical wiring layer to the actual wiring layer is determined.

At this time, in the present embodiment, the circuit variable determination unit 32 detects the number of wiring layers where no wiring is laid in each section. Then, a section having a large number of wiring layers where no wiring is laid is preferentially set as a section to be developed to an actual wiring layer. That is, for example, the number of temporary physical wiring layers is “5”, of which, in section a shown in FIG. 17 above, the number of wiring layers to be laid is three, and in section c, the number of wiring layers is three. Assuming that the number of wiring layers to be laid is "5", development to the actual wiring layer is performed preferentially in section a over section c. In particular, in the case of this example, since no wiring is laid in the “2” wiring layers in the section a, the two wiring layers in the section a are redundant at the end of the layout setting in step S310. Therefore, the circuit characteristics of the integrated circuit as a whole are adjusted by effectively utilizing the redundant space. By doing so, the increase in the number of wiring layers of the integrated circuit can be suppressed as much as possible.

[0175] Specifically, for example, first, a circuit change when the temporary physical wiring layer is not expanded to the actual wiring layer is performed. The timing analysis is performed by the timing analysis unit 30 using the number, and the presence or absence of a timing violation is analyzed. When a timing violation part occurs depending on the circuit variables described above, timing analysis is performed again using the circuit variables obtained when the wiring of the predetermined temporary physical wiring layer in the predetermined section is converted to the wiring of the actual wiring layer. I do. At this time, it is desirable to gradually increase the number of sections to be converted. In addition, it is desirable to increase the number of actual wiring layers to be expanded step by step, such as two or three layers.

Then, the actual wiring layer that realizes the circuit variable at the time when the timing violation is eliminated is finally determined as the actual wiring layer to be used.

[0177] In the following step S340, the wiring of the temporary physical wiring layer is converted into the wiring of the actual wiring layer for each subsection by the wiring layer developing unit 34 based on the determined circuit variables.

[0178] Next, in step S350, the section setting unit 42 sets a connection area between adjacent sections having different development modes on the actual wiring layer. That is, when the development to the actual wiring layer is performed, the connection state at the time of the layout design in step S310 cannot be maintained between adjacent sections having different development modes to the actual wiring layer. . Therefore, a connection area is set between these adjacent sections.

More specifically, first, as shown in FIG. 17 (b), boundaries between sections having different development modes on the actual wiring layer are extracted. As a result, a new section is defined in units of areas having the same development pattern on the actual wiring layer. In FIG. 17 (b), sections a, b, f, and g shown in FIG. 17 (a) are new sections D and sections d, e, h, i, j, m, n, o. Is defined as a new section C, sections k, 1, p, and g are defined as a new section A, and sections r, s, and t are defined as a new section B, respectively.

In such a new section, as shown in FIG. 18 (a) and FIG. 18 (b), the development to the actual wiring layer in step S340 is the same. Specifically, in FIG. 18 (b), in the new section A, the temporary physical wiring layer K is expanded to the actual wiring layers K (l) and Κ (2), and the temporary physical wiring layer K + 1 is actually realized. The wiring layers K + 1 (1) and K + 1 (2) are expanded, and the temporary physical wiring layer Κ + 2 is expanded to the real wiring layers Κ + 2 (1) and Κ + 2 (2). In the new section Β, the provisional physical wiring layer Κ + 2 is expanded to the actual wiring layers Κ + 2 (1) and Κ + 2 (2). Incidentally, in FIGS. 18 (a) to 18 (d), the horizontal direction is the X direction and the vertical direction is the Z direction. In the figure, the force and the X and Y And Y direction. In the figure, the hatching of the actual wiring layer matches the hatching of the temporary physical wiring layer before development.

[0181] Then, in step S350, as shown in Fig. 18 (c), the vicinity of the boundary between adjacent new sections is defined as a connection area. In this connection area, wiring is formed so as to maintain the connection state in the layout design in step S310. In FIG. 18 (c), the hatching of each wiring layer in the coupling region matches the hatching of the temporary physical wiring layer in which the connection state is maintained by the wiring layer.

[0182] In the temporary physical wiring layer K and the temporary physical wiring layer (K + 2) in Fig. 18 (a), the partition A is set so as to straddle the boundary between the new partition A and the new partition B. And wiring to connect Section B is laid. On the other hand, in the temporary physical wiring layer K + 1, the wiring laying direction is the Y direction, which is parallel to the boundary between the new section A and the new section B. Therefore, in the connection area, wiring is laid on the temporary physical wiring layer K and the temporary physical wiring layer (K + 2) so as to maintain the connection state between the new section A and the new section B. In other words, the wiring of the real wiring layer K (l) and the wiring of the real wiring layer K (2) in the new section A and the wiring of the real wiring layer Β in the new section Β form a new section Α and a new section. Connect to B. The wiring of the real wiring layer K + 2 (1) and the real wiring layer K + 2 (2) in the new section A and the real wiring layer K + 2 (1) and the real wiring layer K + 2 in the new section B The new section A and the new section B are connected by the wiring of (1).

[0183] As described above, in the present embodiment, as the structure of the connection region that maintains the wiring connection state in the temporary physical wiring layer, in the present embodiment, the actual wiring layer developed from the same temporary physical wiring layer between adjacent sections is Adopt a structure that connects continuously. In other words, as shown in FIG. 18 (c), the connection area that connects the real wiring layers K (l) and Κ (2) of the new section A and the real wiring layer Β of the new section 連続 continuously A wiring layer in the X direction (first layer in the figure) is provided. In addition, the wiring in the Y direction is connected to the connection area where the real wiring layer Κ + 1 (1) and Κ + 1 (2) of the new section と and the real wiring layer Κ + 1 of the new section 連続 are continuously connected. Layers (second and third layers in the figure) are provided. Furthermore, the real wiring layers K + 2 (1) and K + 2 (2) of the new section A and the real wiring layers K + 2 (1) and K + 2 (2) of the new section B are continuously connected. Wiring layers in the X direction (fourth and fifth layers in the figure) are provided in the connection area to be connected. [0184] In Fig. 18 (c), an area where connection between the connection area and a section adjacent to the connection area is not permitted is marked with an X. This is set by the section setting unit 42 as an area where connection is not permitted when setting the connection area.

[0185] Further, as a setting mode of the connection area, for example, only a temporary physical wiring layer having a wiring that straddles the partitioned area may be connected to the actual physical wiring layer, and may be continuously connected. That is, for example, in FIG. 18 described above, a connection region that continuously connects the real wiring layers K + 1 (1) and K + 1 (2) of the new section A and the real wiring layer K + 1 of the new section B is continuously connected. In setting, it is not necessary to provide an X-direction wiring laying across the sections in the provisional physical wiring layer K + 1. By determining the wiring structure of the coupling region in consideration of the presence or absence of the wiring straddling between adjacent sections in this manner, the degree of freedom of the wiring structure allowed in the coupling region can be increased. For this reason, among the restrictions on the laying of the wiring, the restriction from the structure of the coupling region can be reduced, and the required circuit characteristics of the wiring can be easily realized.

[0186] In the following step S360, the new sections are electrically connected so as to maintain the electrical connection obtained by the layout design in step S310. The electrical connection between the new sections using this coupling region is as illustrated in FIG. 18 (d). As shown in Fig. 18 (d), the real wiring layers K (l) and Κ (2) expanded into two layers in the new section A are connected to the real wiring layer in the new section して via the coupling region. Connected to the wiring. In addition, the real wiring layer K + 2 (l) and the wiring of Κ + 2 (2) expanded to two layers in the new section Α are expanded to two layers in the new section 介 through the coupling region. Connected to the wiring of layers Κ + 2 (1) and Κ + 2 (2).

[0187] In Fig. 18, the force of one expansion structure of the wiring in the coupling region is used. In such a structure, the connection state of the wiring of the temporary physical wiring layer between adjacent sections cannot be satisfied. From the viewpoint of circuit characteristics, a plurality of the same expanded structures may be provided. That is, for example, when the wiring of the provisional physical wiring layer shown in FIG. 19A is converted to the wiring of the actual wiring layer shown in FIG. 19B, a connection region as shown in FIG. 19C is set. You may. As a result, as shown in FIG. 19 (d), the wiring of the real wiring layer K (l), Κ (2), Κ (3) of the new section and the wiring of the real wiring layer Κ of the new section β And are connected. In addition, a new real wiring layer 区画 +2 The real wiring layers Κ + 2 (1) and Κ + 2 (2) in the section β are connected.

[0188] In any case, by using such a coupling region, when connecting the adjacent sections, the wiring provided so that the projection of the integrated circuit onto the substrate surface is on a straight line and the wiring layer is switched is provided. Can be used. Therefore, connection between these adjacent sections can be suitably performed.

[0189] After the connection between the sections using the connection areas in this way, in step S370 shown in Fig. 16 above, the validity of the integrated circuit is checked in the same manner as in step S140 in Fig. 6 above. Further, in step S380, similar to step S150 shown in FIG. 16, mask data is created, and this series of processing ends.

According to the present embodiment described above, the following effects are obtained in addition to the effects (1)-(3) and (5)-(7) in the first and second embodiments. You will be able to obtain.

(9) After the placement and routing using the temporary physical wiring layer is performed, the redundant space in which the wiring is not laid in each partition unit is deleted, so that the redundant space can be reduced. Then, by taking into account that the electrical connection by the wiring of the temporary physical wiring layer is realized by the wiring of a plurality of real wiring layers for each section, the development state over the entire area of the logic circuit unit 2 is considered. As a result, it is possible to realize appropriate wiring with reduced redundancy as compared with the case where the same is used.

[0192] (10) The coupling region having the wiring provided such that the integrated circuit is projected on the substrate surface in a straight line and provided so as to change wiring layers is set near the boundary between adjacent sections. As a result, the connection between the adjacent sections can be preferably performed.

( ^Fifth Embodiment)

Hereinafter, a fifth embodiment in which the integrated circuit and the design method thereof according to the present invention are applied to a semiconductor integrated circuit and a design method thereof will be described with reference to the drawings, focusing on the differences from the fourth embodiment. explain.

In the present embodiment, when the wiring of the temporary physical wiring layer is developed into the wiring of the actual wiring layer, the wiring is not limited to those shown in FIG. 2, FIG. 4, FIG. 10, and FIG. A wiring having a structure as illustrated in FIG. 20 is further used.

[0195] FIG. 20 (a) shows the same physical wiring when one temporary physical wiring layer is expanded into three real wiring layers. In this example, wiring Lgl and wiring Lg2 are provided on the first and third layers, respectively, and no wiring is provided on the intermediate second layer. Further, FIG. 20 (a) shows a via hole which takes a contact between the actual wiring layers and a plug Lg2 and a plug connecting between the wiring Lg2, which show that the shape of the plug formed in the via hole may be arbitrary. pgl0 and a plug pgl l are illustrated.

In FIG. 20 (b), wirings Lhl Lh3 of real wiring layers adjacent to each other are provided in parallel with each other and electrically connected to each other by plugs pgl 2 -pgl 6 in via holes at a plurality of locations. The layout of the via holes is illustrated for the connected wiring. In FIG. 20 (b), when the signal is propagated from the end L to the end R of the wiring Lhl, the wiring Lhl and the wiring with the plug pgl2 are connected from the connection point of the wiring Lhl and the wiring Lh2 with the plug pgl4. The signal propagates to the connection point of Lh2 via each of the wiring Lhl and the wiring Lh2. Further, from the connection point of the wiring Lh2 and the wiring Lh3 by the plug pgl6 to the connection point of the wiring Lh2 and the wiring Lh3 by the plug pgl5, the signal further propagates through the wiring Lh3. Therefore, the resistance of the propagation path when a signal propagates from the end L to the end R can be adjusted by the connection point of the wirings Lhl-Lh3 by these plugs.

[0197] FIG. 20 (c) shows that the wiring Lil-Li3 provided in the real wiring layers adjacent to each other propagates a signal from the end L of the wiring Lil to the end R of the wiring Li3. They are electrically connected to each other so as to form a system IJ. Here, it is assumed that the wiring length laid in the layout using the temporary physical wiring layer is the wiring length of the wiring Li3, and the wiring Lil and the wiring Li2 when the wiring is expanded to the actual wiring layer. The length is different from the wiring length of the wiring of the temporary physical wiring layer. The resistance of the signal propagation path when the signal propagates from the end L to the end R can be adjusted by the wiring length.

Further, FIG. 20 (d) shows, in the case shown in FIG. 4 above, the wiring length of the wiring Lj1 fixed to the potential and the wiring Lj2 connected via the contact hole. The case where the wiring length is different is shown. By arranging the wirings having such a configuration adjacent to each other as illustrated in FIG. 4, the capacitance between these adjacent wirings can be adjusted.

[0199] As shown in FIG. 20 (e), the wirings Lkl, Lk of the actual wiring layers expanded to a plurality of wiring layers are shown. 2 shows a case where each has a different wiring width. Note that these wirings Lkl and Lk2 may be, for example, the (n + 1) th layer wiring and the nth layer wiring shown in FIGS. 2 to 4 and FIGS. 10, 11, and 13 described above. .

[0200] Further, in the present embodiment, based on the temporary physical wiring layer, temporary connection, which is a connection process with a smaller computational load than detailed wiring for completing all connections, is performed. We will try to optimize the layout based on the layout and the wiring route. After that, the development from the temporary physical wiring layer to the actual wiring layer is performed. In this embodiment, at least one area of the area where the wiring of the predetermined temporary physical wiring layer is substantially projected onto the actual wiring layer including a plurality of wiring layers is used for the temporary connection. This is performed based on the circuit characteristics on the assumption that the wiring is converted into a wiring formed.

Hereinafter, with reference to FIG. 21, the procedure for designing an integrated circuit that is effective in this embodiment will be described in detail.

In this series of processing, first, in step S400, a temporary physical wiring layer is defined as in step S300 shown in FIG.

Subsequently, in step S410, based on the provisional physical wiring layer, the automatic placement unit 22 performs the automatic placement of the function cells and the automatic wiring unit 24 performs the temporary connection. The temporary connection may be a Steiner wiring connecting a desired two points with a straight line, or a global connection that requires less computational load than the detailed wiring described above, for example, by performing a trial and error within a predetermined time limit. There are wiring etc. In these cases, for example, a short-circuit of wiring may be allowed. In addition, estimation of circuit variables in these processes is performed by

This is performed in consideration of what is realized when each wiring of the wiring layer is converted to a wiring formed using at least one region of a region substantially projected onto an actual wiring layer including a plurality of wiring layers.

[0203] In the following step S420, similarly to step S320 in Fig. 16 described above, the area for which layout has been designed by the automatic placement and routing tool in the integrated circuit is defined by the partition setting unit shown in Fig. 15 above. Divide into small sections by 42.

[0204] In the following step S430, for the integrated circuit on which the connection has been completed, the circuit variable determination is performed. The setting unit 32 determines the upper limit value and the lower limit value of the circuit variable of the wiring that works on each connection for each section. That is, in the present embodiment, even if the number of actual wiring layers is determined, the circuit variables are not uniquely determined to enable the wiring structure as exemplified in FIG. The lower limit is determined. Here, a circuit variable that satisfies design constraints such as timing and minimizes the number of developments from the temporary physical wiring layer to the actual wiring layer is determined.

When verifying whether or not the above timing design constraint is satisfied, note the following when performing the timing analysis by the timing analysis unit 30 based on the layout data on which the temporary connection has been performed. .

That is, in the global wiring, for example, a short circuit of the wiring is allowed as described above. For this reason, for example, when performing timing analysis while taking into account the coupling capacitance between adjacent wirings, for example, the minimum distance (unit spacing) allowed as the spacing force between these short-circuited wirings And perform timing analysis.

[0207] In the case of the Steiner wiring, since a desired two places are connected by a straight line, it does not directly correspond to the actual wiring layout. For this reason, for example, from the connection mode after the end of the Steiner wiring, the timing analysis is performed by, for example, setting a larger coupling capacitance between adjacent wirings as the wiring congestion degree becomes higher.

[0208] After the circuit variables are determined in step S430, the process proceeds to step S440. In step S440, when the wiring of the temporary physical wiring layer is expanded to the actual wiring layer for each of the sections by the above-described section setting section 42, boundaries between the sections having different development modes are extracted, and these sections are connected. Set the connection area.

[0209] In the following step S450, the automatic placement unit 22 performs fine adjustment of the placement based on the information obtained from the estimation by the processing shown in steps S430 and S440. That is, in step S430, the number of temporary physical wiring layers that can be used for wiring in each subsection is determined. Further, in step S440, a connection mode between adjacent sections having different developments on the actual wiring layer is set. Therefore, based on these information, the arrangement obtained in step S410 is further finely adjusted. In this case, Step S430: Make fine adjustments to obtain an optimal arrangement within the range of the upper and lower limits of the circuit variables determined in S430.

[0210] In the following step S460, detailed wiring for connecting all parts of the integrated circuit is performed based on the provisional physical wiring layer, and the wiring obtained by the detailed wiring is expanded to wiring in the actual wiring layer. Here, the detailed wiring refers to converting each wiring of a predetermined temporary physical wiring layer into a wiring formed by using at least one region of a region substantially projected onto a real wiring layer including a plurality of wiring layers. This is performed based on the assumed circuit characteristics. It is desirable to use this detailed wiring if the temporary connection made in step S410 is a global wiring. Instead of this, adjustment of circuit variables is performed while estimating by temporary connection again.

You can do it. However, in this case, it is preferable that the adjustment of the circuit variable be within the range of the upper limit value and the lower limit value of the circuit variable determined in step S430. After the detailed wiring, the timing analysis is performed by the timing analysis unit 30 to determine a final circuit variable.

[0211] When the final circuit variables are determined, the wiring layer developing unit 34 expands the wiring of the temporary physical wiring layer into the wiring of the actual wiring layer based on the final circuit variable. In other words, the wiring of the temporary physical wiring layer is converted into a wiring formed using at least one of the regions substantially projected onto the real wiring layer including a plurality of wiring layers. However, at this time, in order to allow the wiring structure illustrated in FIG. 20, the wiring on the actual wiring layer does not necessarily match the region where the wiring of the temporary physical wiring layer is simply projected onto the real wiring layer.

[0212] Then, in step S470, the sections are electrically connected to each other using the coupling region so as to maintain the electrical connection of the temporary physical wiring layer by the detailed wiring in step S460.

[0213] Specifically, the setting of the connection area in step S440 and the processing in step S470 based on the setting are desirably performed as shown in FIG.

[0214] Fig. 22 (a) shows the layout of wiring in the temporary physical wiring layers when the number of temporary physical wiring layers in which wiring is laid differs between the adjacent sections A and B. b) shows a mode of development to an actual wiring layer. Then, the joint between the sections shown in Fig. 18 In addition to the method shown in Fig. 22 (c), in the case where the wiring laying directions in the same real wiring layer of the adjacent sections A and B are The provisional physical wiring layers that can be combined in the section are newly defined. Further, in the processing in the above step S470, the connection is made across the adjacent sections in the above step S460, the wiring layer is formed, and the actual wiring layer is expanded. Maintain the connection relationship. Thus, by the processing in step S470, as shown in FIG. 22 (d), the connection between the adjacent sections A and B is performed using the connection area.

[0215] As described above, when the wiring directions in the same actual wiring layer are the same, the connection can be newly established in the coupling region, thereby reducing the connection via different actual wiring layers. it can. That is, for example, in FIG. 22 (a), the temporary physical wiring layer in which wiring is laid in the section A is only the temporary physical wiring layer K-K + 2, which is the wiring in the section B where the wiring is laid. This is different from the temporary physical wiring layer K-K + 4, which is a temporary physical wiring layer. For this reason, for example, if the provisional physical wiring layer K + 2 of the section A and the provisional physical wiring layer K + 4 of the section B have wiring that is to be electrically connected, In a layout using a temporary physical wiring layer, connections are made via another wiring layer or an interlayer insulating film. However, in the real wiring layer, as shown in FIG. 22 (d), the real wiring layer K + 2 (2) corresponding to the provisional physical wiring layer K + 2 of these sections A and the temporary physical wiring of the section B The actual wiring layer K + 4 corresponding to the layer K + 4 is connected to the same layer.

[0216] However, in the connection between the section A and the section B using such a connection area, the wiring of the temporary physical wiring layer that is connected across the adjacent sections is the same as that of the expanded real wiring layer. The condition for maintaining the connection relation in the wiring may be removed. Hereinafter, this is illustrated in FIG.

That is, FIGS. 23 (a) and 23 (b) show the same situation as FIGS. 22 (a) and 22 (b). Then, in FIG. 23 (c), the wiring layer is the same real wiring layer of the adjacent sections A and B, and the wiring laying direction is the same, and the wiring layer is orthogonal to the boundary between the sections A and B. Only allow connections between Block A and Block B at. Then, by the processing in the above step S470, as shown in FIG. 23 (d), the connection between the adjacent sections A and B is performed using the connection area. However, in this case, The connection between the provisional physical wiring layer K + 2 of the section A and the provisional physical wiring layer K + 2 of the section B is not maintained.

[0218] When the connection between the adjacent sections is performed in this way, in steps S480 and S490, the same processing as in steps S370 and S380 in Fig. 16 is performed, and this series of processing ends.

According to the present embodiment described above, the following effects can be obtained in addition to the above-described effects of the fourth embodiment.

[0220] (11) The wirings Lhl-Lh3 of each real wiring layer are provided in parallel with each other and are electrically connected to each other at a plurality of locations by plugs pgl2-pgl6 in via holes. The arrangement of via holes can be set arbitrarily. This makes it possible to adjust the resistance value of the propagation path when the signal propagates from the end to the end R.

[0221] (12) The wiring length of the wiring of the temporary physical wiring layer and the wiring length of the wiring expanded to the actual wiring layer are allowed to be different. As a result, it is possible to adjust the resistance value and the capacitance between the wirings according to the wiring length.

[0222] (13) The wiring width is allowed to differ between real wiring layers developed from one temporary physical wiring layer. Thereby, the resistance value and the capacitance between wirings can be adjusted.

[0223] (14) While assuming that each wiring of the temporary physical wiring layer is converted into a wiring formed using at least one region of a region substantially projected onto a real wiring layer including a plurality of wiring layers, By performing the placement and routing based on the temporary physical wiring layer, it is possible to perform a layout design that makes the placement and the wiring route more appropriate.

[0224] (Sixth embodiment)

Hereinafter, a sixth embodiment in which the integrated circuit and its design method according to the present invention are applied to a semiconductor integrated circuit and its design method will be described with reference to the drawings, focusing on the differences from the fourth embodiment. explain.

In the fourth embodiment, after the arrangement and the connection are performed using the temporary physical wiring layer, the projection of the integrated circuit onto the substrate surface is performed from the temporary physical wiring layer for each of the plurality of divided sections. Development to the wiring layer was performed. That is, the integrated circuit was divided into two-dimensional sections, which were developed into actual wiring layers as a unit. On the other hand, in the present embodiment, not only is the integrated circuit divided into planar partitions, but also division in the vertical direction is performed using several temporary physical wiring layers as a unit. FIG. 24 exemplifies how the integrated circuit is divided into sections according to the present embodiment. FIG. 24 illustrates a division state of the logic circuit unit 2 having the temporary physical wiring layer K and the temporary physical wiring layer K + 7.

Here, FIG. 24 (a) shows a division mode of the provisional physical wiring layer K−K + 4 in the logic circuit unit 2. The remaining temporary physical wiring layer K + 5K + 7 in the logic circuit section 2 is divided into a section u shown in FIG. 24 (b), a section V shown in FIG. 24 (c), and a section V shown in FIG. 24 (d). And is divided into the indicated sections w. As described above, in the present embodiment, the temporary physical wiring layer K + 5, the temporary physical wiring layer K + 6, the temporary physical wiring layer K + 7, and the force are respectively divided into one section.

In such a configuration, for the provisional physical wiring layer K-K + 4, in the series of processes shown in FIG. 14, each process is performed in the mode shown in FIGS. 17 and 18. That would be.

[0229] On the other hand, for the provisional physical wiring layer K + 5—K + 7, based on the circuit variables determined by the processing of step S220 in FIG. 14 above, in the processing of step S230, FIG. 24 (e) and FIG. As shown in f), development from the temporary physical wiring layer to the actual wiring layer is performed. The wiring generated by expanding from the temporary physical wiring layer to the real wiring layer has the same wiring formation mask on each of the developed real wiring layers as illustrated in FIGS. It is desirable that

[0230] As described above, according to the present embodiment, a partition is configured in units of several temporary physical wiring layers, and circuit characteristics are adjusted for each partition. You will be able to make adjustments. That is, for example, the wiring in the uppermost layer of the integrated circuit tends to have a longer wiring length, so that the wiring resistance increases remarkably. However, the wiring of this temporary physical wiring layer is replaced with, for example, the wiring shown in FIG. By performing the conversion, the resistance value can be suitably suppressed.

According to the present embodiment described above, the following effects can be further obtained in addition to the effects of the fourth embodiment.

(15) A section which is a unit of development from a temporary physical wiring layer to an actual wiring layer is defined as an integrated circuit board. Not only was it configured as a two-dimensional division in a plane parallel to the plane, but also as a division in units of several temporary physical wiring layers. Thereby, the circuit characteristics of the integrated circuit can be adjusted more suitably.

(Seventh Embodiment)

Hereinafter, a seventh embodiment in which the integrated circuit and its design method according to the present invention are applied to a semiconductor integrated circuit and its design method will be described with reference to the drawings, focusing on differences from the first embodiment. I do.

In the first embodiment, the connection is once performed using the temporary physical wiring layer, and then the connection is developed to the actual wiring layer. On the other hand, in the present embodiment, a temporary physical wiring layer and an actual wiring layer obtained by expanding the temporary physical wiring layer are determined in advance, and connection is performed by an automatic wiring tool. In other words, the connection is performed by providing a prohibited area for which connection by the automatic wiring tool is prohibited corresponding to the upper layer or the lower layer of the wiring laying area where the adjustment of the electrical characteristics is desired. After that, the predetermined wiring is converted into a wiring having the same structure as the wiring illustrated in FIGS. 2-4, 10, 10, 11, and 20 by using the prohibited area. The wiring prohibition area has features such as permission / prohibition of via formation, so that it is possible to control a wiring path and a degree of freedom in forming a wiring structure.

Hereinafter, this will be described with reference to FIGS.

FIG. 25 is a flowchart showing a procedure for designing an integrated circuit according to the present embodiment.

This design procedure is performed using the design support device shown in FIG.

[0236] In this series of processing, first, in step S500, the automatic placement unit 22 performs automatic placement of a functional cell for which circuit design has been completed.

[0237] In the following step S510, connection using an automatic wiring tool is prohibited in an upper layer or a lower layer of a predetermined wiring laying area where adjustment of electric characteristics of the wiring, such as wiring resistance and capacitance between the wirings, is desired. A prohibited area is provided. Here, it is desirable that the predetermined wiring is, for example, a bus wiring or a clock wiring. Further, it is preferable that the upper or lower wiring layer of the predetermined wiring laying area is a wiring layer adjacent to the wiring layer on which the predetermined wiring is laid.

[0238] Specifically, this prohibited area stores, for example, circuit information and the like in the design specification storage unit 12 described above. The predetermined wiring such as a bus wiring or a clock wiring may be used to specify the predetermined wiring and, based on the specified wiring, notify the automatic wiring unit 24 of the prohibited area through the input unit 50.

[0239] In the following step S520, in the automatic wiring unit 24, connection between the functional cells is performed in such a manner as to avoid the prohibited area.

[0240] After the connection between the functional cells is thus performed, the circuit variables are determined by the circuit variable determining unit 32 in step S530. This can be done, for example, as follows. That is, first, the values that can be taken by the circuit variables when the above-mentioned predetermined wiring is converted into the wiring extending over the two wiring layers having the structure illustrated in FIGS. 2-4, 10, 10, and 20, etc. Is calculated by the circuit variable calculator 20. Then, based on the circuit variables calculated by the circuit variable calculator 20, the timing analyzer 30 performs timing analysis. Then, a circuit variable that satisfies the design constraint is determined based on the analysis result of the timing analysis unit 30.

[0241] In the following step S540, based on the determined circuit variables, the wiring layer developing unit 34 expands the wiring to the prohibited area. Then, in steps S550 and S560, the same processing as the processing in steps S140 and S150 shown in FIG. 6 is performed.

For example, FIGS. 26 (a) to 26 (c) show a plurality of actual wiring layers K (3)-(1) in which the provisional physical wiring layer K is developed.

[0243] In these real wiring layers K (3)-K (l), a prohibited area is set as an area where the temporary physical wiring layer is developed before wiring by the automatic wiring tool. That is, the wiring prohibited area DAI is set in the real wiring layer K (3) shown in FIG. 26A, and the prohibited areas DA2, DA3, and DA4 are set in the real wiring layer K (2) shown in FIG. 26A. Is set, and the prohibited area DA5 is set in the actual wiring layer Κ (1) shown in FIG. 26 (a). The prohibited area DA4 shown in FIG. 26B prohibits the formation (automatic placement) of wiring and through vias (via holes that penetrate the wiring layer and connect the upper and lower wirings of the wiring layer). The other prohibited areas DAI, DA2, DA3, and DA5 are areas where wiring is prohibited but formation of through vias is permitted. Also, as shown in FIG. 26 (a), predetermined wirings Ll l and L12 are provided in the actual wiring layer K (3), and as shown in FIG. 26 (c), predetermined wirings Ll l and L12 are provided in the actual wiring layer K (l). Wiring L13 and L14 are laid.

[0244] Figs. 27 (a) -1 (c) and 28 (a)-(c) show the actual distribution in which the temporary physical wiring layer K is expanded after connection. Line layer K (3) —shows K (l). Here, the wiring L11 of the provisional physical wiring layer Κ is changed to the wiring LI la, LI lb and the plug Pl la, PI lb of the real wiring layer Κ (2) and the real wiring layer Κ (3) based on the determined circuit variables. Has been expanded to. In addition, the wiring L14 of the provisional physical wiring layer K is expanded to the wirings L14a, L14b, L14c and the plugs P12a, P12b of the actual wiring layer K (l) and the actual wiring layer K (2) based on the determined circuit variables. ing.

According to the present embodiment described above, the effects (1) and (3) of the first embodiment, the effects (6) and (7) of the second embodiment, The same effects as the effects (11) and (13) of the fifth embodiment can be obtained.

(Eighth Embodiment)

Hereinafter, an eighth embodiment in which the integrated circuit and the design method thereof according to the present invention are applied to a semiconductor integrated circuit and a design method thereof will be described with reference to the drawings, focusing on differences from the second embodiment. I do.

[0247] In the semiconductor integrated circuit according to the present embodiment, the logic circuit section 2 further includes the wiring shown in FIG. FIG. 29 (a) shows a circuit diagram of the wiring included in the logic circuit unit 2. In FIG. 29 (a), a wiring Lml for signal propagation is shielded by wirings Lm2 and Lm3 whose potentials are fixed at a power supply potential and a ground potential.

The wiring structure corresponding to the circuit diagram of FIG. 29 (a) is shown in FIG. 29 (b) —FIG. 29 (e). Fig. 29

(b) and FIG. 29 (c) are plan views of the wirings Lml-Lm3 in the (n + 1) th wiring layer and the nth wiring layer, respectively. Here, the surface of each wiring layer is a plane defined by the x direction and the y direction, and the wiring laying direction is the X direction. FIGS. 29D and 29E are cross-sectional views of the wiring Lm2 and the wiring Lm3, respectively. Here, the normal direction of the xy plane is the z direction. As shown in FIGS. 29 (d) and 29 (e), the wiring Lm2 switches the wiring layer via the plug pgl7, and the wiring Lm3 switches the wiring layer via the plug pgl8. Is going.

As described above, in the present embodiment, the wirings Lm2 and Lm3 for shielding the signal transmission wiring Lml in the n-th wiring layer are switched to the (n + 1) -th wiring layer, and the signal The capacitance between the transmission wiring Lm1 and the wiring Lm2 and the capacitance between the signal transmission wiring Lml and the wiring Lm3 are adjusted. That is, as shown in FIG. 29 (c), the wirings Lm2 and Lm3 are All of them are laid in the n-th layer adjacent to the signal propagation wiring Lml, and are switched to the (n + 1) -th wiring layer in the middle as shown in FIG. 29 (b). . For this reason, the capacitance between these lines Lm2 and Lm3 and the line Lml is reduced. Therefore, as compared with the case where the wiring Lm2 and Lm3 are adjacent to each other in the entire area where the wiring Lml for signal propagation is laid on the nth layer, it is necessary to increase the signal propagation speed in a range where a sufficient shielding effect can be obtained. Can be.

[0250] Furthermore, since the switching manners of these wirings Lm2 and Lm3 are different from each other, in the n-th wiring layer, the signal transmission wiring Lml and the wiring Lm2 and Lm3 having a fixed potential are adjacent to each other. Is different between the wiring Lm2 and the wiring Lm3. Then, in the example shown in FIG. 29, the length of the wiring Lm3 fixed to the ground potential is shorter than the length of the wiring Lml for signal propagation adjacent to the wiring Lm2 fixed to the power supply potential. Therefore, the signal propagating through the signal transmission wiring Lml has a relatively high rise time compared to the fall time of the signal.

As described above, by adjusting the region where the signal propagation wiring Lml and the fixed potential wirings Lm2 and Lm3 are adjacent to each other, the signal propagation speed and signal waveform of the signal propagation wiring Lml are reduced. Be able to adjust.

[0252] The integrated circuit according to the present embodiment having such a wiring structure can also be designed by the design procedure shown in FIG. That is, by performing the layout design using the temporary physical wiring layer in step S110, the layout data of the wiring shown in FIG. 30A is realized from the circuit shown in FIG. 29A. Further, by converting the wiring of the temporary physical wiring layer into the wiring of the actual wiring layer in the above steps S120 and S130, the layout data of the wiring shown in FIGS. 29B to 29E is realized. Then, in the above step S150, the mask data shown in FIG. 30 (b) and FIG. 30 (d) is generated. The mask data shown in FIG. 30 (b) is for the (n + 1) th wiring layer, and the mask data shown in FIG. 30 (c) is for the (n + 1) th and nth layers. The mask data shown in FIG. 30 (d) is for the nth wiring layer.

According to the present embodiment described above, the effects (1)-(1) (3) and (5) of the first embodiment and the (6) and (7) of the second embodiment described above are obtained. In addition to the effects of Ability to gain fruit

(16) The wiring Lm2 and Lm3 for shielding the signal transmission wiring Lml in the n-th wiring layer are switched to the (n + 1) -th wiring layer to connect with the signal transmission wiring Lml. The capacitance between Lm2 and the capacitance between the signal propagation wiring Lml and the wiring Lm3 can be adjusted.

(Ninth Embodiment)

Hereinafter, a ninth embodiment in which the integrated circuit according to the present invention and its design method are applied to a semiconductor integrated circuit and its design method will be described with reference to the drawings, focusing on differences from the above-described eighth embodiment. I do.

In the semiconductor integrated circuit according to the present embodiment, the logic circuit unit 2 further includes the wiring shown in FIG. FIG. 31 (a) shows a circuit diagram of the wiring included in the logic circuit unit 2. In FIG. 31 (a), the wiring Lml for signal propagation is shielded by wirings Ln2 and Ln3 whose potentials are fixed at the power supply potential and wirings Ln4 and Ln5 whose potentials are fixed at the ground potential. I have.

FIG. 31 (b) and FIG. 31 (e) show a wiring structure corresponding to the circuit of FIG. 31 (a). FIGS. 31B and 31C are plan views of the wirings Lnl to Ln5 in the (n + 1) th wiring layer and the nth wiring layer, respectively. Here, the surface of each wiring layer is a plane defined by the x direction and the y direction, and the wiring laying direction is the X direction. FIGS. 31D and 31E are cross-sectional views of the wiring Lnl, the wiring Ln2, and the wiring Ln5, respectively. Here, the normal direction of the xy plane is the z direction. As shown in FIG. 31 (d), the wiring Lnl switches wiring layers via the plug pgl9. As shown in FIG. 31 (e), the wiring Ln2 is formed over two adjacent wiring layers via the plug pg20, and the wiring Ln5 is formed on the two adjacent wiring layers via the plug pg21. It is formed over.

[0257] Here, in the n-th wiring layer, each of the wirings Ln2 to Ln5 has the same length, and in the wiring laying area between the wirings Ln2 and Ln5 and the wirings Ln3 and Ln4, A wiring Lnl for signal propagation is laid. On the other hand, in the (n + 1) th wiring layer, the lengths of the wirings Ln2 and Ln3 whose potentials are fixed at the power supply potential and the wirings whose potentials are fixed at the ground potential The lengths of Ln4 and Ln5 are different from each other. Therefore, in the (n + 1) -th wiring layer, the length of the signal transmission wiring Lnl adjacent to these wirings Ln2 and Ln3 and the wirings Ln4 and Ln5 is different from each other.

In particular, in the example shown in FIG. 31, the lengths of the lines Ln4 and Ln5 fixed to the ground potential are closer to the wiring Ln1 for signal propagation than the lines Ln2 and Ln3 fixed to the power supply potential. It is getting shorter. Therefore, the signal propagating through the signal transmission line Lnl has a relatively high rise time compared to the fall time of the signal. As described above, the signal waveform of the signal transmission line Lnl can be adjusted by adjusting the region where the signal transmission line Lnl and the fixed potential lines Ln2 to Ln5 are adjacent to each other. You.

[0259] The integrated circuit according to the present embodiment having such a wiring structure can also be designed by the design procedure shown in FIG. That is, by performing the layout design using the temporary physical wiring layer in step S110, the layout data of the wiring shown in FIG. 32 (a) is realized from the circuit shown in FIG. 31 (a). Further, by converting the wiring of the temporary physical wiring layer into the wiring of the real wiring layer in the above steps S120 and S130, the layout data of the wiring shown in FIGS. 31 (b) to 31 (e) is realized. Then, in step S150, the mask data shown in FIGS. 32 (b) to 32 (d) is generated. The mask data shown in FIG. 32 (b) is for the (n + 1) th wiring layer, and the mask data shown in FIG. 32 (c) is for the (n + 1) th and nth layers. The mask data shown in FIG. 32 (d) is for the nth wiring layer.

[0260] According to the present embodiment described above, the effects (1), (1), (3), and (5) of the first embodiment and the effects (6) and (5) of the second embodiment described above are also obtained. The effect of 7) and the effect of (16) of the eighth embodiment can be obtained.

(Tenth embodiment)

The above embodiments may be modified and implemented as follows.

[0261] In addition, the above steps S140, S240, S370, S480, etc. (when it is determined that there is enough room, etc. Conversely, even if processing is performed to reduce the number of wiring layers in the expanded real wiring layers, Good. That is, for example, the wires in the actual wiring layer shown in FIG. 2 may be compressed and converted into the wires shown in FIG.

[0262] The structure for increasing the capacitance of a pair of adjacent wires is not limited to the structure illustrated in FIG. For example, it may be as shown in FIG.

[0263] FIG. 33 (a) shows that a pair of adjacent wirings (wiring Lol and wiring Lo2 and wiring Lo3 and wiring Lo4) are respectively formed by parallel connection of wirings of a plurality of wiring layers. Is common to a pair of wirings. Incidentally, the wiring Lol and the wiring Lo2 are connected in parallel to each other by plugs pg22 and pg23. Also wiring.

3 and wiring Lo4 are connected in parallel with each other by plugs pg24 and pg25. The wiring Lol and the wiring Lo3, the wiring Lo2 and the wiring Lo4 are formed on the same wiring layer.

[0264] FIG. 33 (b) shows that a pair of adjacent wirings (wiring Lpl and wiring Lp2 and wiring Lp3 and wiring Lp4) are laid in parallel with each other and the collection of paths from one end to the other end. The wiring power of a plurality of wiring layers connected in series with each other so that the projection of the integrated circuit onto the substrate surface is configured. Incidentally, the wiring Lpl and the wiring Lp2 are connected in series with each other by a plug Pg26. The wiring Lp3 and the wiring Lp4 are connected in series to each other by a plug Pg27. The wiring Lpl and the wiring Lp3, the wiring Lp2 and the wiring Lp4 are formed in the same wiring layer.

Further, for example, in FIG. 4, one of the wiring Lbl and the wiring Lb2 may not be connected to the wiring La1 or the wiring La2. In this case, of the wiring Lbl or the wiring Lb2, the wiring connected to the wirings Lbl and Lb2 of the (n + 1) th wiring layer is a dummy wiring having one open side. be able to. Then, a capacitance between the dummy wiring and the adjacent wiring is given to the wiring connected to the dummy wiring. Therefore, the capacitance between the wiring connected to the dummy wiring and the wiring connected to the P wiring can be increased.

Note that the pair of wirings in FIG.

a. As shown in FIG. 34 (a), a wiring Ll connecting between specific terminals ta and tb of any two elements Ea and Eb of the integrated circuit. b. As shown in FIG. 34 (b), a wiring L2 for fixing the potential of a specific terminal tc of any one element Ec of the integrated circuit.

Desirably, at least one of the following.

As shown in FIG. 34 (a), the wiring shown in FIG. 2 also has a specific wiring such as between specific terminals ta and tb of any two elements Ea and Eb of the integrated circuit. It is desirable that the wiring be used to connect two terminals.

[0267] Further, the wiring structures illustrated in FIGS. 2, 3, 4, 10, 10, 11, 13, 20, 29, 31, and 33, etc., are also described in these figures. Re, limited to those illustrated. The point is that it is composed of wirings of a plurality of wiring layers connected to each other by via holes in such a manner that they have the same route direction as each other and that the projection of the integrated circuit onto the substrate surface overlaps each other. It may be changed appropriately within the range.

In addition, the wiring having such a wiring structure,

a. As shown in FIG. 34 (a), a wiring Ll connecting between specific terminals ta and tb of any two elements Ea and Eb of the integrated circuit.

b. As shown in FIG. 34 (b), a wiring L2 for fixing the potential of a specific terminal tc of any one element Ec of the integrated circuit.

c. As shown in FIG. 34 (c), the wiring L3 whose potential is fixed and whose one side is open. d. As shown in FIG. 34 (d), a wiring L4 connected to the terminal of the specific element Ed and having one side open.

It is desirable to use at least one wiring.

In the above embodiments, after the layout design is completed based on the layout data, the mask data is created from now on. However, the present invention is not limited to this. For example, the placement and connection by an automatic placement and routing tool, the development to an actual wiring layer, and the like may be performed using mask data.

• The division of the section exemplified in the sixth embodiment may be used in the fifth embodiment. • In the second to fourth and sixth embodiments, the wiring structure shown in FIG. 20 may be adopted.

[0269] The mode of setting the sections by the section setting unit 42 is not limited to the examples illustrated in Figs. What? This section is not limited to a rectangular shape.

• The area designed using the automatic placement and routing tool is not limited to the logic circuit section.

In the seventh embodiment, the prohibition region is not limited to the one provided on a single wiring layer, but may be at least one of an upper layer and a lower layer of a wiring laying region where electric characteristics are desired to be adjusted. A connection prohibited area where connection by the automatic wiring tool is prohibited is provided in the layer of.

[0271] The procedures for designing an integrated circuit are not limited to those exemplified in the above embodiments. For example, the following may be used.

[0272] Step 1: (a) After performing automatic placement using the temporary physical wiring layer by the conventional method, perform temporary connection on the temporary physical wiring layer with less computational load than the final connection, and Estimate the wiring route on the temporary physical wiring layer. Here, the circuit characteristics based on the assumption that the wiring of a predetermined temporary physical wiring layer is converted into a wiring formed using at least one region of a region substantially projected onto a real wiring layer including a plurality of wiring layers are described. Provisional connection is performed based on this. (B) Final connection is performed based on the estimation of the wiring route. (Iii) Perform the conversion based on the above premise based on the circuit characteristics that help estimate the wiring route.

[0273] Step 2: (a) Convert the wiring of the predetermined temporary physical wiring layer into a wiring formed using at least one of the regions substantially projected onto the real wiring layer including a plurality of wiring layers. Arrange them based on the assumed circuit characteristics. (A) Connect each part of the integrated circuit by the conventional wiring method using the temporary physical wiring layer. (Iii) Converting a wiring of a predetermined wiring layer of the temporary physical wiring layer into a wiring formed by using at least one region of a region substantially projected onto a real wiring layer including a plurality of wiring layers.

'In the layout design of step S310 shown in FIG. 16 above, after the placement is completed, the integrated circuit is divided into a plurality of regions, and the cost for laying wiring is defined for each region. Under the specified conditions, the connection of each part of the integrated circuit may be performed so as to reduce the cost.

[0275] Thus, for example, a region where high-speed performance is required, such as a region in which it is particularly desired to adjust circuit variables by expanding to an actual wiring layer, is defined so as to increase the cost. By reducing the number of temporary physical wiring layers used for laying wiring in the same area Can do. For this reason, in this area, the development to the actual wiring layer can be preferentially performed. In other words, by providing a constrained area that reduces the number of temporary physical wiring layers used for laying wiring, priority can be increased in areas where specific circuit characteristics such as high speed are desired. This can be applied to actual wiring layers, and the circuit characteristics can be greatly improved.

The integrated circuits having the wiring structures illustrated in FIGS. 2, 3, 4, 10, 10, 11, 13, 20, 29, 31, 33, etc. The present invention is not limited to the one performed by the design illustrated in the embodiment and its modification. Further, for example, assuming the layout by the conventional automatic wiring tool in which the wiring laying direction is orthogonal between the adjacent wiring layers, the previous FIGS. 2, 3, 4, 4, 10, 11, 13, and 20 are used. An integrated circuit having the wiring structure illustrated in FIG. 29, FIG. 31, and FIG. 33 may be designed. That is, for example, by using two wiring layers that separate one wiring layer, such as a third layer and a fifth layer, wiring that requires a low resistance, for example, when high-speed operation is required, as shown in FIG. The wiring may be configured as exemplified in a). At this time, between the wiring Lgl and the wiring Lg2, a wiring in a direction orthogonal to the laying direction of the wiring Lgl and the wiring Lg2 may be formed so as to intersect with the wiring Lg1 and the wiring Lg.

The present invention is not limited to the standard cell method, and may be applied to the wiring design of an integrated circuit using a multilayer wiring, in addition to applying the design method of the present invention to a gate array.

[0278] At least one region of a region where each of the wirings in the predetermined temporary physical wiring layer is substantially projected onto a real wiring layer made up of a plurality of wiring layers in order to achieve the desired circuit characteristics with the desired circuit characteristics The arithmetic means for converting into wiring formed by using is not limited to those exemplified in the above embodiments. For example, instead of using software and a program, a dedicated hardware unit may be used.

[0279] The arithmetic means for setting a wiring layer used for coupling between adjacent sections having different development modes on the actual wiring layer is not limited to the above section setting section 42. For example, instead of using software and a program, a dedicated hardware unit may be used.

In the first to sixth embodiments and their modifications, the design method of expanding the temporary physical wiring layer into the actual wiring layer is used for the area designed using the automatic placement and routing tool. ,to this Not exclusively. For example, even in the case of designing without using an automatic wiring tool, once the wiring is completed, the wiring of a predetermined wiring layer is drawn in the area where each wiring is roughly projected onto the actual wiring layer consisting of multiple wiring layers. By converting to wiring formed using at least one region, it is possible to adjust circuit characteristics without changing the design. The target of the design using such an automatic wiring tool is, for example, an analog macro including analog elements, such as a DZA converter and an AZD converter.

In the actual wiring layer obtained by expanding the temporary physical wiring layer of the above embodiment, the position of the plug may be changed as appropriate. For example, the wiring structure in the temporary physical wiring layer shown in FIG. 35 (a) is developed into a wiring structure including a plurality of physical wiring layers as shown in FIG. 35 (b). FIG. 35 (c) is a cross-sectional view of the wiring having the structure developed on the actual wiring layer as viewed from the X direction. At this time, the adjacent plugs (vias) P21 and P22 indicated by the arrows are formed so as to be displaced in the X direction so that they are not overlapped. Depending on the direction in which the wiring extends, the position may be shifted so that the plug does not overlap in the Y direction.

When the temporary physical wiring layer is expanded to the actual wiring layer, a plug can be formed at an arbitrary position on the actual via layer between the actual wiring layers. Therefore, as shown in FIG. 13A, by forming the plugs so as to overlap in the X direction or the Y direction, it is possible to increase the capacity S between the plugs. Conversely, as shown in Fig. 35 (b), by forming the plugs so that they do not overlap, it is possible to reduce the capacitance between the plugs by increasing the distance between the plugs, and to reduce the crosstalk noise. . By appropriately changing the position of the plug (via) as described above, the capacitance between wirings can be increased or decreased without changing the wiring path, and a circuit having desired electrical characteristics can be obtained. Can be.

In each of the above embodiments, when the wiring determined by the provisional physical wiring layer is expanded to the wiring of the actual wiring layer, the wiring separation layer (horizontal and vertical insulating layers) in the expanded wiring region In order to generate the desired electrical characteristics at the time of development, adjust the height or width of the wiring separation layer, or develop a configuration using a high-permittivity material or a low-permittivity material. May be.

For example, as shown in FIGS. 36 (a)-(c), wiring L21 laid in parallel with the temporary physical wiring layer

(Between terminals A1 and A2) and wiring L22 (between terminals B1 and B2) as shown in Fig. 37 (a) and (b). Expand to multiple layers (six layers in the figure) of actual wiring layers, and connect the wiring in the vertical direction (Z direction) with a plug whose width is adjusted in the X direction. As a result, two wirings L21a and L22a having a predetermined area facing each other on the XZ plane and separated by a wiring interval in the Y direction are configured. The resistance of the two wirings L21a and L22a can be made smaller than the resistance of the wiring laid on one wiring layer by multiplexing the wirings, and the capacitance between the two wirings L21a and L22a can be increased. .

Further, as shown in FIG. 37 (c), by forming the insulating film Ml between the wirings L21a and L22a adjacent to each other in the Y direction and the plug with a high dielectric constant (high-k) material, Can be increased, and the capacitance value can be easily controlled depending on the material used.

[0286] In the above embodiments, when the wiring defined by the temporary physical wiring layer is expanded to the wiring of the actual wiring layer, the position where the plug (via) is formed is appropriately set, so that the actual A structure in which a coil is formed in the wiring layer and the inductance component is adjusted by the coil may be employed. Various structures are conceivable for the coin.

For example, the wiring L31 defined in the provisional physical wiring layer shown in FIGS. 38 (a) and (b) is developed in the actual wiring layer to form the coil 61 shown in FIGS. 38 (c) and (d). The coil 61 is a planar spiral coil formed along the X-Z plane.

[0288] Further, the frame-shaped wiring L41 defined in the temporary physical wiring layer shown in Fig. 39 (a)-(c) is developed in the actual wiring layer, and the coil 62 shown in Figs. Form. The coil 62 is a spiral coil extending along the Z direction. In addition, Fig. 40 (a) shows the wiring and plug developed from the wiring L41a (between terminals B1 and B2) in Fig. 39 (c), and Fig. 40 (b) shows the wiring L41b (between terminals A1 and A2 in Fig. 39 (c)). The wires and plugs with () are shown. Further, FIG. 40 (c) shows the wiring and plug obtained by expanding the wiring L41c (between terminals A2 and B2) of FIG. 39 (c), and FIG. 40 (d) shows the wiring L41d (terminals A1-B1) of FIG. 39 (c). The wiring and the plug are shown in the expanded state.

The wiring L51 defined in the temporary physical wiring layer shown in FIGS. 41 (a) and 41 (b) is developed in the actual wiring layer to form the coil 63 shown in FIGS. 41 (c) and 41 (d). The coil 63 is a zigzag (meander) coil formed along the XZ plane.

[0290] Also, the frame-shaped wirings L61 and L62 defined in the temporary physical wiring layer shown in Figs. 42 (a) and 1 (c) are developed in the actual wiring layer, and are shown in Figs. 43 (a) to (d). The coil 64 is formed. This coil 64 is Is a spiral-shaped coil extending along. FIG. 43 (a) shows a wiring and a plug obtained by expanding the wiring L62 of FIG. 42 (a), and FIG. 43 (b) shows a wiring and a plug obtained by developing the wiring L61 of FIG. 42 (b). FIG. 43 (c) shows the wirings of the actual wiring layer K (l), the actual wiring layer K (3) and the actual wiring layer Κ (6), respectively.

In the first embodiment, in order to comply with the antenna rule, for example, as shown in FIG. 44, the wiring is changed to a bridge structure in the actual wiring layer to shorten the wiring length. For example, the wiring L71 defined in the temporary physical wiring layer shown in FIGS. 44 (a) and (b) is extended to the actual wiring layer to form the wiring L71 shown in FIG. 44 (c). This wiring L71 is connected to the gate terminal of the transistor at the terminal A2. Then, the length of the wiring L71a formed on the actual wiring layer K (l) connected to the terminal A2 violates the antenna rule. By dividing this wiring L71a into two wirings L71b and L71c as shown in Fig. 44 (d), the length of the wiring connected to the gate terminal of the transistor is shortened, and the wiring stored in the wiring during manufacturing is shortened. Reduce the amount of electric charge. In this way, by deploying the wiring that violates the antenna rule into a bridge structure, the violation of the rule can be easily eliminated.

[0292] In each embodiment, the development as the wiring of a plurality of actual wiring layers means that the thickness of the actual wiring layer is, in principle, a method of realizing the case of manufacturing in which the thickness is fixedly determined. Shows. Here, when the thickness of the actual wiring layer is set arbitrarily (multi-step) in manufacturing, a structure that is developed as a wiring of a plurality of actual wiring layers is used as an actual wiring having a plurality of wiring thicknesses. This is realized by treating it as a layer structure.

[0293] In addition to the integrated circuit designed by the method of expanding the temporary physical wiring layer to the real wiring layer, other than the integrated circuit designed in FIG. 2, FIG. 3, FIG. 4, FIG. 10, FIG. 11, FIG. , FIG. 29, FIG. 31, FIG. 33, FIG. 35—FIG.

(Eleventh Embodiment)

Hereinafter, an eleventh embodiment in which the integrated circuit and the design method thereof according to the present invention are applied to a semiconductor integrated circuit and a design method thereof will be described with reference to the drawings.

FIG. 45 shows a configuration of a semiconductor integrated circuit having a multilayer wiring structure according to the present embodiment. The semiconductor integrated circuit 1 shown in FIG. 45A includes a logic circuit unit 2 and an analog circuit unit 3. In the present embodiment, the logic circuit unit 2 is designed using an automatic placement and routing tool. Part.

[0296] Fig. 45 (b)-Fig. 45 (e) show the laying rules for each wiring from the (n + 3) th wiring layer to the nth wiring layer of the same logic circuit unit 2. As shown in FIG. 45 (b), in the (n + 3) th wiring layer, wirings are provided substantially in parallel with each other. The laying interval of each of these wirings is an integral multiple of the unit interval Pd. That is, the wiring intervals of P-connected wiring are Pd, 2Pd, 3Pd, and so on. The laying direction of the wiring laid on the (n + 3) th layer is the Y direction.

Further, as shown in FIG. 45 (c), the wiring is provided substantially parallel to the (n + 2) -th wiring layer. The laying interval of each of these wirings is an integral multiple of the unit interval Pc. The laying direction of the wiring laid on the (n + 2) th layer is the X direction.

As shown in FIG. 45 (d), the (n + 1) th wiring layer is provided with wirings substantially parallel to each other. The laying interval of each of these wirings is an integral multiple of the unit spacing Pc equal to the unit spacing in the (n + 2) th wiring layer. The wiring direction of the wiring laid on the (n + 1) th layer is the X direction.

As shown in FIG. 45 (e), in the n-th wiring layer, wirings are provided substantially in parallel with each other. The laying interval of each of these wirings is an integral multiple of the unit interval Pa. The wiring direction of the wiring laid on the nth layer is in the Y direction.

As described above, in the present embodiment, basically, the inverse scaling rule is applied, in which an upper wiring layer has a larger wiring laying interval. According to the inverse scaling rule, the wiring width and the wiring interval can be increased in the upper wiring layer, so that the wiring resistance can be reduced and the capacitance between adjacent wirings can be reduced. For this reason, the upper wiring layer has a configuration in which a wiring having a longer wiring length can be easily laid. Note that such an inverse scaling rule is applied intentionally for the purpose of making it easier to lay wiring having a longer wiring length in an upper wiring layer, and is also applied as a request from a semiconductor integrated circuit manufacturing process. Sometimes. That is, for example, when the flatness of the upper wiring layer is lower, it is desirable to increase the interval between the wiring layers in the upper wiring layer. [0301] In the present embodiment, the wiring direction is the same in the (n + 2) th wiring layer and the (n + 1) th wiring layer that are adjacent wiring layers. . By the way, in the general placement and wiring, the wiring laying directions in adjacent wiring layers have different directions, and especially in the middle wiring layer, the wiring laying in P contact always has a different laying direction. . On the other hand, as in the present embodiment, when the rules for arranging the wiring directions of the respective wiring layers are changed so that the wiring laying directions are the same between the wiring layers adjacent to each other, the laying of these wirings is considered. The unit intervals can be easily made equal. In other words, if the inverse scaling rule is intentionally applied for the purpose of making it easier to lay wiring with a longer wiring length in the upper wiring layer, the above-mentioned unit intervals should be equal without substantially impairing the purpose. Can be. Further, even when the inverse scaling rule is applied due to restrictions from the manufacturing process, the difference in the unit spacing is smaller between the wiring layers adjacent to each other than in the wiring layers separated from each other. I'm sorry.

By setting the same wiring laying direction between adjacent wiring layers in this manner, the adjustment of the electrical characteristics of the wiring is smooth as shown in FIGS. 46 to 48. Is

[0303] FIG. 46 (a) shows the wirings Lel, Le3, Le5 laid in the (n + 1) th wiring layer and the (n)

+2) A diagram in which the wirings Le2 and Le4 laid in the second wiring layer are projected on the substrate surface (XY plane) of the integrated circuit. Further, FIG. 46B shows a YZ sectional view of the wiring Lei-Le5. As shown in these figures, the wirings Lel, Le3, and Le5 of the (n + 1) th wiring layer are laid such that the laying interval Pe is twice the unit spacing Pc, and the (n) + 2) Similarly, wiring Le2 and Le4 of the wiring layer are laid so that the laying interval between them is twice the unit interval Pc. Then, the center lines of the wirings of the respective layers are alternately laid so as to be offset by the unit interval Pc so that the wirings of the respective layers do not overlap on the XY plane.

[0304] Thus, the distance between adjacent wirings in the same wiring layer can be made larger than the unit spacing, so that the capacitance between adjacent wirings can be suitably reduced. Also, for example, when the wiring Le3 and the wiring of the (n + 3) th layer in which the wiring laying direction is different from each other via connection, the wiring of the (n + 2) th layer located in the middle may be an obstacle. Direct contact Since the connection is possible, the via connection can be easily performed.

[0305] In this example, the distance Pe between the center lines of the wirings in the same wiring layer is set to twice the unit interval Pc. However, the present invention is not limited to this. If it ’s twice, In addition, in the wiring of the (n + 1) th wiring layer and the wiring of the (n + 2) th wiring layer, it is assumed that the center lines of the respective wirings are laid with a unit interval Pc offset. , Not limited to this. The point is that the wiring of each layer does not overlap on the XY plane.

Next, FIG. 47 (a) shows the wiring Lai and the wiring La2 laid on the (n + 1) th wiring layer and the (n + 2) th wiring layer, FIG. 47 (b) shows an XZ cross-sectional view of the wiring Lai, and FIG. 47 (c) shows an XZ cross-sectional view of the wiring La2. As shown in these figures, in the (n + 1) th wiring layer, the wirings Lai and La2 are provided adjacent to each other, and the wiring La2 is connected to the (n + 2) th through the plug pg in the via hole. It is provided so that it can be switched to the wiring layer of the layer.

As a result, adjacent portions of the wiring Lai and the wiring La2 in the same wiring layer can be reduced as much as possible. Therefore, the capacitance between the wiring Lai and the wiring La2 can be suitably reduced.

On the other hand, FIG. 48 (a) and FIG. 48 (c) show how to lay the shield wiring for shielding the signal transmission wiring Lcl for which protection against the influence of noise or the like is desired in the present embodiment. Here, in the (n + 1) -th wiring layer, wirings Lc2 and Lc3 having fixed potentials are provided on both sides of the wiring Lcl for signal propagation. The (n + 2) th wiring layer has a potential formed so as to include the projection area of the signal transmission wiring Lcl to the (n + 2) th wiring layer. The fixed wiring Lc4 is formed.

As shown in FIGS. 48 (b) and 48 (c), these (n + 1) th layer wiring Lc2, wiring Lc3 and (n + 2) th layer wiring Lc4 Are electrically connected to each other by a plug pg provided in the via hole. Accordingly, the wirings Lc2 and Lc3 of the (n + 1) th wiring layer and the wiring Lc4 of the (n + 2) th wiring layer shield the signal transmission wiring Lcl from surrounding electromagnetic waves. To form a shielded wiring. [0310] As a result, it is possible to appropriately take measures against crosstalk and electromagnetic interference (EMI) with respect to the signal transmission wiring Lcl. By the way, it is desirable that the shielded wiring to be shielded by the shield wiring is a bus wiring or a clock wiring.

[0311] On the other hand, Figs. 46 (c), 47 (d) and 48 (d) show the same laying direction between adjacent wiring layers according to the setting of the laying direction of wiring in a normal automatic wiring tool. When they are orthogonal, they are shown and shown.

That is, in FIG. 46C, wirings Lel, Le3, and Le5 are laid on the (n + 1) th wiring layer, and wirings Le2 and Le4 are laid on the (n + 3) th wiring layer. Is laid.

In FIG. 47 (d), the wirings Lbl and Lb2 are provided adjacent to each other in the (n + 1) th wiring layer, and the wiring Lb2 is connected through the plug in the via hole. It is provided so as to be switched to the (n + 3) th wiring layer.

Further, in FIG. 48 (d), the wiring Lcl for signal propagation is formed by the wirings Lc2 and Lc3 of the (n + 1) th wiring layer and the wiring Lc4 of the (n + 3) th wiring layer. The shield wiring for is configured.

In FIG. 46 (c), FIG. 47 (d) and FIG. 48 (d), the unit spacing between the wirings of the (n + 1) th wiring layer is the (n + 3) The figure shows a case in which the unit spacing Pd of the wiring layer of the layer is combined. In other words, usually, the bow of the wiring tends to be shorter than that of the wiring in the (n + 3) th wiring layer. 3) The unit spacing for the wiring of the (n + 1) th wiring layer smaller than the wiring of the wiring layer of the (n + 1) th layer is set to the unit spacing side of the wiring layer of the (n + 1) th layer. For this reason, the reduction in wiring resources is larger than in the case of FIGS. 46 (a) and (b) and FIG. 47 (a) —FIG. 47 (c) and FIG. 48 (a) —FIG. Has become.

[0316] However, if the inverse scaling rule is not a request from the manufacturing process, the unit spacing of the wiring of the (n + 3) th wiring layer is changed to the unit spacing of the wiring of the (n + 1) th wiring layer. It may be possible to combine with However, in this case, the wiring of the (n + 3) th layer violates the inverse scaling rule set in consideration of the tendency of the wiring length to become longer, and the wiring resistance, the capacitance between the wirings, etc. In addition, a problem easily occurs in electrical characteristics.

[0317] Furthermore, in the configuration shown in Fig. 46 (c), Fig. 47 (d), and Fig. 48 (d), the arrangement of the (n + 3) th layer When making electrical contact between the wiring in the wiring layer and the wiring in the (n + 1) th wiring layer, the wiring between the wiring in the (n + 2) th wiring layer, which is an intermediate wiring layer between them, It is also necessary to avoid interference. For this reason, when the wiring is performed by the automatic wiring tool, an increase in calculation load and a reduction in wiring resources in avoiding the above-described interference are inevitable.

On the other hand, in the present embodiment, the wiring directions of the (n + 1) th wiring layer and the (n + 2) th wiring layer are made the same, whereby The problem that occurs when the unit intervals described above are the same for the wiring of the wiring layer can be suitably suppressed. In addition, since there is no intermediate wiring layer, it is possible to avoid the problem of interference at the time of the electrical connection.

Hereinafter, a design procedure of a semiconductor integrated circuit having such a configuration and working on this embodiment will be described.

FIG. 49 is a block diagram showing a configuration of a semiconductor integrated circuit design support apparatus according to the present embodiment. This support device is configured as a device that supports the design of the standard cell system or the gate array system.

[0320] The library 1010 stores the performance information of the functional cells, such as the cell information of various functional cells constituting the semiconductor integrated circuit, the delay information of the functional cells, and the constraint information on the setup and hold time. It is the part that is done. Here, the various functional cells are logical operation elements (logical product, logical sum, exclusive logical sum, exclusive logical product, negation, etc.) ゃ flip-flops, memories such as RAM, analog devices such as A / D, or the like. It is a circuit formed using them. Further, the library 1010 is a part in which information on the layout of the functional cells, such as the area information of each functional cell, is stored.

[0321] The design specification storage section 1012 is a section for storing information on functions and structures of the semiconductor integrated circuit described in, for example, a hardware description language (HDL). More specifically, the design specification storage unit 1012 stores circuit information expressed by RTL (resistor transfer level), gate level, and the like, timing such as operating frequency, power conditions, and the like. Here, for example, the circuit information at the gate level is obtained from the cells defined in the library 1010, the type and number of cells used, and the logical connection information thereof. Netlist.

[0322] Further, the process parameter 1014 includes element characteristics according to designated design rules (rules regarding minimum processing accuracy in the manufacturing process, rules specifying element size and minimum wiring interval, etc.), wiring characteristics for each material, and the like. This is the part where the information about is stored.

The library 1010, the design specification storage unit 1012, and the process parameter 1014 are provided with a storage device such as a hard disk device.

[0324] On the other hand, the automatic placement unit 1020 and the automatic routing unit 1022 as automatic placement and routing tools are parts for performing layout design. That is, the automatic arrangement unit 1020 is a unit for automatically arranging the function cells, and the automatic wiring unit 1022 is a unit for connecting the arranged function cells. The automatic arrangement of the functional cells and the connection between the arranged functional cells are performed using the layout data of the library 1010 corresponding to the functional cells.

[0325] The netlist of the circuit generated by the automatic wiring unit 1022 is supplied to the timing analysis unit 1030. This netlist has a hierarchical structure, and is composed of a netlist in a functional block composed of functional cells and a netlist between functional blocks.

[0326] The timing analysis unit 1030 is a unit that performs timing analysis based on the netlist and the process parameters 1014.

[0327] Note that the automatic placement unit 1020, the automatic wiring unit 1022, and the timing analysis unit 1030 each include a powerful storage device such as a semiconductor memory or a hard disk device that stores a program related to the processing to be performed, and a computer. It is configured.

[0328] In addition, the input unit 1040 is a unit that includes input devices such as a touch pen, a keyboard, and a mouse, and that inputs various information and commands for layout design. The image display unit 1042 is a part that visually displays the input information, the layout diagram, and the like. On the other hand, the control unit 1050 controls the operations of the image display unit 1042, the automatic placement unit 1020, the automatic wiring unit 1022, the timing analysis unit 1030, and the like.

Next, a procedure for designing a semiconductor integrated circuit according to the present embodiment, which is performed using the design support apparatus having such a configuration, will be described.

FIG. 50 shows a procedure for designing a semiconductor integrated circuit according to the present embodiment. [0330] In this series of processing, first, in step S1100, the layout information relating to the functional cells stored in the library 1010 and the gate-level circuit information stored in the design specification storage unit 1012 are automatically placed by the automatic placement unit 1020. Is input to Then, the automatic placement unit 1020 performs automatic placement of functional cells based on the gate-level circuit information.

[0331] When the automatic placement of the function cells is performed in this way, in step S1110, the laying area of the shielded wiring, which is the wiring shielded by the shield wiring, is specified through the input unit 1040. Further, in adjacent wiring layers in which the wiring laying direction is the same, the wiring of each layer is laid at intervals larger than the unit interval, and when viewed from the substrate surface of the semiconductor integrated circuit, the wiring of each layer is The area laid so as not to overlap is also specified through the input unit 1040.

[0332] Subsequently, in step S1120 and step S1130, in the automatic wiring unit 1022, the connection information of the functional cell stored in the design specification storage unit 1012 and the laying of the shielded wiring specified in step S1110 are performed. Using the information on the area where wiring is to be laid so that the wiring of each layer does not overlap when viewed from the substrate surface in the area or the adjacent wiring layer, the connection between the functional cells where the above arrangement is completed is performed .

[0333] Here, first, in step S1120, wiring with fixed potentials such as power supply wiring and the connection between these laid wirings are performed. At this time, the shield wiring laying area is set, for example, through the input unit 1040 so as to correspond to the shielded wiring laying area. Note that the laying area of the shielded wiring designated in step S1110 is an area where the laying of the wiring with the fixed potential is prohibited.

In the following step S1130, wiring is laid to help signal propagation between the functional cells.

Further, in step S1140, the timing analysis unit 1030 performs timing analysis based on the layout data in which the connection between the functional cells has been completed and the information stored in the process parameter 1014. It is desirable that this timing analysis includes a crosstalk noise analysis based on the extraction of the capacitance between P-connected wires.

[0335] Then, in step S1150, the timing analysis unit 1030 checks this timing analysis. It is determined whether or not the result is within an allowable range. If not within the allowable range, the process returns to step S1130, and the connection of each functional cell is performed again. At this time, in the embodiment shown in FIG. 47, the (n + 1) th wiring layer and the (n + 2) th wiring layer are adjacent to each other in one of the wiring layers. By replacing one of the provided pair of wirings with the other wiring layer, timing violation due to crosstalk noise is avoided. In addition, in step S1130 as a process immediately after the processing of steps S1110 and S1120, any one of the (n + 1) th wiring layer and the (n + 2) th wiring layer In addition, the wiring may be laid such that the wiring of a pair of wirings provided adjacent to each other is shifted to the other wiring layer. This can be realized, for example, by providing the automatic wiring unit 1022 with a function of performing transfer when the wiring length of an adjacent wiring exceeds a predetermined length.

In the adjacent wiring layer, the wiring of each layer is laid at an interval larger than the unit interval, and the wiring of each layer does not overlap when viewed from above the substrate surface of the semiconductor integrated circuit. The designation of the area to be laid may be performed through the input unit 1040 based on the result of the timing analysis in step S1150, and the process may return to step S1130 and connect the functional cells again.

Further, as shown by the broken line in FIG. 50, when it is determined in step 1140 that the timing violation cannot be eliminated in the layout, the process returns to step S1100 to relocate the functional cells. Yore,

If it is determined in step S1150 that the result of the timing analysis is within the allowable range, the series of processes is temporarily terminated.

[17] (17) In the area where wiring is performed by the automatic wiring tool, two adjacent wiring layers

And the wiring laying directions were the same. Therefore, various problems associated with miniaturization can be easily dealt with, and more efficient design can be achieved.

(18) The higher the wiring layer, the larger the unit interval for defining the wiring laying interval is set. As a result, it is possible to provide a wiring having a longer wiring length for connecting portions separated from each other in an upper wiring layer. (19) In adjacent wiring layers having the same wiring laying direction, the unit intervals defining the wiring laying intervals are set to be substantially the same. As a result, electrical connection of wiring between these wiring layers can be easily performed.

(20) The distance between the wirings of the (n + 1) th and (n + 2) th wiring layers is set to be larger than the unit spacing, and when viewed from above the substrate surface, the (n + 1) th By preventing the wiring of the () -th wiring layer from overlapping with the wiring of the (n + 2) -th wiring layer, the capacitance between the wirings in the same wiring layer can be suppressed, and crosstalk noise can be reduced. The accompanying timing violation can be avoided.

(21) One of a pair of wirings provided adjacent to each other in one of the (n + 1) th wiring layer and the (n + 2) th wiring layer The timing violation due to crosstalk noise can be avoided by changing the wiring to the other wiring layer.

(22) Shield wiring was configured using adjacent wiring layers having the same wiring laying direction. This makes it possible to avoid electrical connection between the shield wirings and interference with the another wiring layer as in the case where another wiring layer is provided between the wiring layers in which the wirings constituting the shield wiring are provided. As a result, it is possible to configure a shielded wiring that does not significantly damage wiring resources, and it is possible to easily perform measures against crosstalk and electromagnetic interference (EMI).

The above-described embodiment may be modified and implemented as follows.

The first wiring, which is a wiring constituting the shield wiring and runs in parallel with the shielded wiring, is not necessarily provided on both sides of the signal propagation wiring as exemplified in FIG. The configuration is not limited.

• The positional relationship between the signal transmission wiring and the second wiring, which is a wiring constituting the shield wiring and is provided in a wiring layer different from the wiring layer in which the signal transmission wiring is provided, is shown in FIG. Re, limited to those exemplified in the above. That is, for example, the second wiring may be provided in the lower layer where the signal transmission wiring is provided, or the second wiring may be provided in both the upper layer and the lower layer.

[0346] The (n + 2) -th wiring layer and the (n + 1) -th wiring layer are not necessarily related to the wiring pitch. The unit intervals are not limited to those having the same unit interval. For example, even when the unit spacing of the (n + 2) th wiring layer is larger than the unit spacing of the (n + 1) th wiring layer, the wiring laying directions of the adjacent wiring layers are the same. This makes it possible to avoid interference as in the case where an intermediate wiring layer is provided between them. Further, even when the inverse scaling law is used, the difference in the wiring pitch between wiring layers having the same wiring laying direction can be reduced by making the wiring laying directions of the wiring layers in contact with each other the same.

• The area designed by the automatic wiring tool is not limited to the logic circuit section.

[0347] In a region designed by the automatic wiring tool, the wiring direction of two adjacent wiring layers is not limited to be set to the same direction in advance. For example, regarding wiring for which electrical characteristics are desired to be adjusted, the wiring laying direction may be the same between adjacent wiring layers only at a portion where the wiring is laid.

In the above embodiment, an example in which the integrated circuit according to the present invention and the method for designing the same are applied to a semiconductor integrated circuit has been described. However, the present invention is not limited to this. The present invention may be applied to an integrated circuit provided, for example, an integrated circuit in which elements on a silicon, glass, or printed circuit board are circuit-connected.

[0349] The present invention can also be grasped as follows.

1. An invention relates to an integrated circuit having a multilayer wiring structure, comprising: a. A wiring connecting between specific terminals of any two elements included in the integrated circuit; and b. An arbitrary one of the integrated circuits. Wiring that fixes the potential of a specific terminal of the element; c. Wiring that has a fixed potential and is substantially open on one side; and d. Is connected to the terminal of the specific element and the other end is substantially At least one of the interconnects that are to be opened at the same time has substantially the same path direction as each other, and the projection of the path onto the substrate surface of the integrated circuit overlaps with the via hole in a manner overlapping each other. The gist of the present invention is that it is composed of wirings of a plurality of wiring layers connected to each other.

In the above configuration, the wiring force of the ad, which is usually configured by one wiring, has substantially the same path direction, and the projection of the path onto the substrate surface of the integrated circuit overlaps with each other. It is composed of a plurality of wiring layers connected to each other by via holes. For this reason, compared to the case of forming on a single wiring layer, In comparison, the degree of freedom of the circuit variables that can be taken by the wiring can be improved. For this reason, it becomes possible to easily deal with various problems associated with miniaturization.

Here, the “path” is a long side in the longitudinal direction of the wiring separated by the via hole, and does not include the via hole. In addition, the overlapping of the projections of the routes on the wiring layers includes the case where the projections of the routes on the wiring layers and the wirings are in contact with each other.

[0350] 2. One invention provides a wiring force for connecting between specific two terminals of an element included in the integrated circuit, the wiring force being provided in a plurality of wiring layers in parallel with each other and being electrically connected in parallel with each other. The gist is to have a part that has

In the above configuration, for a portion provided in parallel with a plurality of wiring layers and electrically connected in parallel with each other, for example, through each of these wirings, a predetermined two places (in the wiring layer) A single signal can be propagated from one of the two (parallel connected ends) to the other. As a result, it is possible to reduce the wiring resistance compared to the case where this wiring is a single line.

At this time, it is desirable that the wirings electrically connected in parallel with each other be formed so that the projection of the integrated circuit onto the substrate surface overlaps each other. This makes it possible to adjust the effective wiring width and wiring length, that is, the wiring resistance without increasing the wiring width and wiring length of a vertical projection of the wiring on the substrate surface of the integrated circuit. This reduces the inductance that does not increase the effective wiring length, that is, the wiring length in the vertical projection of the wiring with respect to the substrate surface of the integrated circuit.

[0351] 3. One aspect of the invention is an integrated circuit having a multilayer wiring structure, in which a region provided in parallel with a plurality of wiring layers and where the projection of the integrated circuit onto a substrate surface overlaps each other. The gist is that the plurality of wirings are connected in series in such a manner that the signal propagation directions are inverted with respect to each other.

In the above configuration, the effective wiring length, that is, the wiring length in the vertical projection of the wiring is enlarged because the signal propagates through the wiring connected in series in a manner in which the signal propagation directions are inverted with respect to each other. It is possible to increase the resistance of the wiring to be performed. For this reason In addition, the present invention can be applied to the adjustment in the direction of increasing the resistance value in the adjustment of a signal delay amount, the generation of a reference potential, and the like in the integrated circuit.

In the above configuration, the inductance is increased without increasing the effective wiring length, that is, the wiring length in the vertical projection of the wiring with respect to the substrate surface of the integrated circuit. In the invention of the above item 2 or 3, the plurality of wiring layers may include wiring layers adjacent to each other.

This avoids electrical interference between the wiring routed in the wiring layer between them, which is likely to occur when the plurality of wiring layers are not adjacent to each other, and the wiring of the plurality of wiring layers having the above configuration, or Can be suppressed.

[0352] 4. One invention is directed to a method in which the laying direction and the laying interval of wirings provided in parallel to each other are set to be substantially the same between adjacent wiring layers. The gist is that projections are provided so as to form a pair of wiring layers having wirings that are closest to each other and different wiring layers.

In the above configuration, the pair of wirings are provided in different wiring layers of adjacent wiring layers. Therefore, the capacitance between the pair of wirings can be suitably reduced without increasing the horizontal interval between the pair of wirings.

[0353] 5. The one invention is that the projection of the integrated circuit onto the substrate surface is provided such that adjacent wirings are alternately switched between at least two wiring layers via via holes. Make a summary.

In the above configuration, the wirings provided so that the projection of the integrated circuit onto the substrate surface are adjacent to each other are placed in the same wiring layer, and the portion adjacent to the horizontal direction is reduced as much as possible. As a result, the capacitance between these horizontally adjacent wirings can be suitably reduced.

In the present invention, the at least two wiring layers may include wiring layers adjacent to each other.

This avoids electrical interference between the wiring routed in the wiring layer between them, which is likely to occur when the plurality of wiring layers are not adjacent to each other, and the wiring of the plurality of wiring layers having the above configuration, or Can be suppressed. [0354] 6. One invention provides an integrated circuit having a multilayer wiring structure, wherein at least one of a pair of wirings provided adjacent to and parallel to a predetermined wiring layer includes the predetermined wiring layer. And a corresponding wiring of a pair of wirings provided adjacent to each other and in parallel with the pair of wirings in the same direction as the pair of wirings. The gist is that at least one of the pair of wirings provided in the above is formed as a dummy wiring whose one side is substantially open.

In the above configuration, at least one of the pair of wirings in the predetermined wiring layer is placed in another wiring layer as described above, and a wiring adjacent to the dummy wiring to be connected thereto (a pair of another wiring layer). (The other of the wirings). Therefore, the capacitance between the wiring connected to the dummy wiring and the wiring connected to the P-contact can be increased. For this reason, it is possible to adjust the delay amount of the signal propagating through the wiring and to perform impedance matching.

[0355] Moreover, even if the effective wiring pitch is not reduced or the wiring length is increased, in other words, the wiring pitch of the vertical projection of the wiring on the substrate surface of the integrated circuit is reduced or the wiring length is increased. Since the capacitance can be increased even without the above, there is no restriction on design rules and no increase in resistance.

In particular, when a pair of wirings of a predetermined wiring layer and a pair of wirings of another wiring layer are connected to each other, both of the pair of wirings of the another wiring layer become dummy wirings. Since the capacitance between the dummy wirings is added to the capacitance between the pair of wirings in the wiring layer, the capacitance between the pair of wirings in the predetermined wiring layer can be increased.

[0356] In the present invention, the pair of wirings in the another wiring layer may be substantially equal to a pair of wirings in the predetermined wiring layer projected on the same wiring layer. Thus, the mask pattern of the predetermined wiring layer and another wiring layer can be the same for at least the pair of wirings.

[0357] Further, according to the present invention, the predetermined wiring layer and the another wiring layer may be wiring layers adjacent to each other. This avoids electrical interference between the wiring routed in the wiring layer between them and the wiring of the wiring layers of the above configuration, which is likely to occur when a plurality of wiring layers are not adjacent to each other. Or can be suppressed. [0358] 7. One invention is an integrated circuit having a multi-layered wiring structure, wherein a wiring connecting between specific terminals of any two elements provided in the integrated circuit, and an arbitrary one of the integrated circuits is provided. A pair of wirings each composed of at least one of wirings for fixing the potential of a specific terminal of one element is formed by parallel connection of wirings of a plurality of wiring layers, respectively, and the plurality of wiring layers are formed of the pair of wirings. The gist is that the pair of wirings common to each other and in each of these wiring layers are formed adjacent to each other.

In the above configuration, the pair of wirings is configured by connecting the wirings of a plurality of wiring layers in parallel, so that the wiring resistance is reduced as compared with the case where the pair of wirings are formed as a single line. Power S can. Further, since the pair of wirings are formed adjacent to each other in each wiring layer, the capacitance between the pair of wirings is also reduced to at least one of the pair of wirings by a wiring of a single wiring layer. It can be increased as compared with the case of forming as. It is desirable that the wirings of the plurality of wiring layers include wiring layers adjacent to each other. This avoids electrical interference between the wiring routed in the wiring layer between the wiring layers, which tends to occur when the wiring layers are not adjacent to each other, and the wiring of the wiring layers having the above configuration, or Can be suppressed.

[0359] 8. One invention is an integrated circuit having a multi-layered wiring structure, wherein a wiring connecting between specific terminals of any two elements provided in the integrated circuit, and an arbitrary one of the integrated circuit is provided. A pair of wirings, each of which consists of at least one of the wirings for fixing the potential of a specific terminal of one element, are laid in parallel with each other, and the path from one end to the other end is over projected on the substrate surface of the integrated circuit. The plurality of wiring layers are connected in series so as to overlap with each other, and the plurality of wiring layers are common to the pair of wiring layers, and the pair of wirings in each of the wiring layers is The gist is that they are formed adjacent to each other.

In the above configuration, the pair of wires are connected in series so as to overlap each other, so that the resistance of the pair of wires is reduced by the effective wire length, that is, the wire in the vertical projection of the wire. It can be increased without increasing the length. Since the pair of wirings are formed adjacent to each other in each wiring layer, the capacitance between the pair of wirings is also set such that at least one of the pair of wirings is a wiring of a single wiring layer. It can be increased as compared with the case of forming by forming.

It is desirable that the wirings of the plurality of wiring layers include wiring layers adjacent to each other. This avoids electrical interference between the wiring routed in the wiring layer between the wiring layers, which tends to occur when the wiring layers are not adjacent to each other, and the wiring of the wiring layers having the above configuration, or Can be suppressed.

[0360] 9. One aspect of the present invention relates to an integrated circuit having a multilayer wiring structure, in which a plurality of potential fixed wirings, which are a plurality of wirings fixed at mutually different potentials, and a signal propagation wiring are provided. At a portion where the projections of the integrated circuit onto the substrate surface are formed adjacent to and parallel to each other, at least one of the wirings changes wiring layers so that the signal transmission wirings have the plurality of potentials. The length adjacent to the fixed wiring and any wiring layer is different for each potential fixed wiring.

The gist is to be made different.

The length of the adjacent signal transmission wiring and potential fixing wiring corresponds to the magnitude of the capacitance between these wirings. Then, the propagation speed of the signal on the signal transmission wiring changes depending on the magnitude of the capacitance between the signal transmission wiring and the adjacent potential fixing wiring.

In addition, the waveform of the signal propagating through the signal transmission wiring changes depending on the ratio of the length of the signal transmission wiring adjacent to the potential fixing wiring fixed at a different potential.

In this regard, in the above configuration, the signal propagation speed and signal waveform on the signal propagation wiring can be adjusted by adjusting the length of the signal propagation wiring adjacent to each potential fixing wiring.

[0361] 10. One aspect of the present invention is an integrated circuit having a multilayer wiring structure, wherein the wiring directions of wirings provided substantially in parallel with each other are set to be substantially the same between wiring layers, and And a region formed by a plurality of wiring layers in which the distance between the center lines with respect to the line width of the wiring provided in the wiring layers is set to an integral multiple of a unit interval that is substantially the same between the wiring layers. A. A wiring for connecting between specific two terminals of an element included in the integrated circuit, the wiring being provided in a plurality of wiring layers in parallel with each other and having portions electrically connected in parallel with each other; And b. A plurality of wirings which are provided in parallel with each other on a plurality of wiring layers and have an area where projections on the wiring layers overlap with each other. C. a pair of wirings connected in series in such a manner that the signal propagation directions are inverted with respect to each other; and C. a pair of wirings provided adjacent to each other in parallel on a predetermined wiring layer and the predetermined wirings. One side is substantially open by being provided adjacent to and in parallel with another wiring layer and at least one of the layers is connected to a corresponding wiring of the pair of wirings via a via hole. D. A pair of wirings formed as dummy wirings, and d. A pair of wirings composed of the wirings that are closest to each other when projected onto the substrate surface of the integrated circuit, and formed in different wiring layers. And e. Projecting the integrated circuit onto the substrate surface is a wiring adjacent to each other, and at least two wiring layers of the plurality of wiring layers are alternately switched via via holes. Yo F. A plurality of potential fixed wirings, which are a plurality of wirings fixed at mutually different potentials, and signal transmission wirings, which are projected onto the substrate surface of the integrated circuit. Are formed adjacent to each other and parallel to each other. At least one of the wirings changes wiring layers, so that the signal transmission wiring is fixed to the plurality of potentials. The gist of the present invention is that at least one of the wirings in which the length adjacent to the wiring in an arbitrary wiring layer is different for each potential fixing wiring is provided.

In the above configuration, the laying directions of the wirings provided substantially in parallel with each other are set to be substantially the same between the wiring layers, and the interval between the center lines with respect to the line width of the wirings provided in parallel with each other is set. The wiring layer has a region composed of a plurality of wiring layers set to an integral multiple of substantially the same unit interval. By setting the laying mode of the wiring between the wiring layers in this manner, each of the wirings af can be easily formed.

In other words, when the wiring described in a above is provided, when a single signal is transmitted to one of the two places in the wiring layer and the other to the other, the signal is transmitted to the substrate surface of the integrated circuit. A plurality of wirings provided in parallel on a plurality of wiring layers so that the projections of the propagation paths overlap each other are used. For this reason, the wiring resistance can be suitably adjusted according to the laying mode of the plurality of wirings and the relationship between the signal propagation directions in the respective wiring layers corresponding to the overlap region.

In addition, when the wiring b is provided, the capacitance between the dummy wirings is added to the capacitance of the adjacent wiring in one wiring layer, so that the capacitance between the adjacent wirings may be increased. it can. Na

It is desirable that the pair of dummy wirings be provided in a region where the pair of wirings is projected on the another wiring layer.

Further, when the wiring c is provided, at least one of a pair of wirings in a predetermined wiring layer is adjacent to a dummy wiring connected thereto in the another wiring layer. In this case, the capacitance between the wiring and the other wiring (the other of the pair of wirings in another wiring layer) is provided. For this reason, the capacitance between the wiring connected to the dummy wiring and the wiring connected to the P wiring can be increased.

In short, when the wiring d is provided, the capacity between the same pair of wirings can be suitably reduced without increasing the horizontal interval between the pair of wirings.

[0364] Further, when the wiring e described above is provided, horizontally adjacent wirings can minimize a horizontally adjacent part in the same wiring layer, and as a result, these horizontally adjacent wirings can be reduced. It is possible to preferably reduce the capacitance between the wirings to be performed. Further, when the wiring of the above f is provided, the signal transmission speed and the signal waveform on the signal transmission wiring are adjusted by the length of the signal transmission wiring adjacent to each potential fixing wiring. become able to.

It is desirable that the above-mentioned region is provided with at least two of these a-f wirings so as to satisfy a plurality of required elements with respect to increase and decrease of resistance, capacitance between wirings, and the like.

By the way, the above-mentioned area is an area that can be easily designed by an automatic wiring tool because the center line spacing with respect to the line width of the wiring provided in parallel with each other is an integral multiple of the unit spacing. You.

[0365] 11. One invention is the invention according to the tenth aspect, wherein the region provided with at least one of the wirings a to f has a wiring laying direction between adjacent regions in a predetermined wiring layer. The gist of the present invention consists of a plurality of different areas.

According to the above configuration, an appropriate wiring structure is applied to each region of the integrated circuit because a plurality of regions have wiring layers in which wiring laying directions are different between adjacent regions. Can be. 12. The invention according to the eleventh aspect, wherein the projection of the integrated circuit onto the substrate surface is straight on the connection between the adjacent regions among the regions in which the wiring laying directions are different from each other, and the wiring layer May be used. This makes it possible to appropriately suppress the length of the wiring route for connecting the adjacent regions without taking a detour route or the like.

13. One aspect of the present invention is that a wiring layer in an integrated circuit in which a layout is realized is a temporary physical wiring layer, and that circuit characteristics of each wiring of a predetermined temporary physical wiring layer among the temporary physical wiring layers are desired. Converting the respective wirings into wirings formed using at least one of the regions substantially projected onto an actual wiring layer composed of a plurality of wiring layers by means of a circuit property to be calculated and a slip calculating means. This is the gist.

According to the above design method, each wiring of the temporary physical wiring layer is converted into a wiring formed using at least one of the regions substantially projected onto the actual wiring layer including a plurality of wiring layers. For this reason, it is possible to realize circuit characteristics (characteristics such as wiring characteristics and capacitance between wirings) that cannot be realized by wiring using a conventional wiring method that does not employ a wiring forming method by such conversion. Therefore, adjustment of circuit characteristics can be easily performed.

Further, at this time, since the wiring is converted based on the wiring path of each wiring of the temporary physical wiring layer, such adjustment of the circuit characteristics without correcting the electrical connection mode by the wiring of the temporary physical wiring layer is performed. It can be carried out.

[0368] 14. One invention is directed to an integrated circuit design method for determining a wiring route to be applied to each element of an integrated circuit, wherein the wiring layer for performing the connection is a temporary physical wiring layer, Based on the circuit characteristics based on the premise that each wiring of the physical wiring layer is converted into a wiring formed using at least one of the regions substantially projected onto an actual wiring layer including a plurality of wiring layers, The gist is to determine the wiring route on the temporary physical wiring layer by automatic wiring. In the above design method, each wiring of a predetermined temporary physical wiring layer is replaced with an actual wiring composed of a plurality of wiring layers. A wiring path on the temporary physical wiring layer is determined by automatic wiring on the premise of circuit characteristics based on conversion into wiring formed using at least one of the regions substantially projected onto the wiring layer. Therefore, when the wiring route is determined by the automatic wiring, it is possible to use circuit characteristics (characteristics such as wiring characteristics and capacitance between wirings) that cannot be realized by the wiring without assuming the above conversion. The degree of freedom of selection can be improved, and the calculation load for determining the wiring route by automatic wiring can be reduced.

Then, if the conversion to the presupposed wiring is performed based on the wiring path determined in this way, a wiring having desired circuit characteristics can be easily designed. Therefore, adjustment of circuit characteristics can be easily performed. Since the wirings converted in this way overlap with (or approach) the projections of the integrated circuit onto the substrate surface, it is possible to form wirings with a high density of the projections.

Here, the “substantially projected region” is not limited to the region itself projected in the normal direction to the temporary physical wiring layer, but also includes a region in contact with the same region.

15. An invention is directed to an integrated circuit design method for automatically arranging each element of an integrated circuit, wherein a wiring layer to be connected to each part of the integrated circuit is a temporary physical wiring layer, and the connection is made. It is assumed that each wiring of the predetermined temporary physical wiring layer of the integrated circuit is converted into a wiring formed using at least one region of a region substantially projected onto a real wiring layer including a plurality of wiring layers. The gist is to perform the automatic placement based on the circuit characteristics thus determined.

The above design method is based on the premise that each wiring of a predetermined temporary physical wiring layer is converted into a wiring formed using at least one of the regions substantially projected onto an actual wiring layer including a plurality of wiring layers. The automatic arrangement is performed based on the circuit characteristics thus determined. For this reason, when deciding placement by automatic placement, placement based on circuit characteristics (characteristics such as wiring characteristics and capacitance between wirings) that cannot be realized by wiring that does not assume the above conversion can be performed. The degree of freedom can be improved. In particular, the converted wiring allows higher density placement than before conversion.

According to the above-described design method, the arrangement of each element of the integrated circuit can be made denser to be simple. Then, if the conversion to the wiring assumed as described above is performed based on the determined layout, wiring having circuit characteristics suitable for the determined layout can be easily designed.

Here, the “substantially projected region” is not limited to the region itself projected in the normal direction to the temporary physical wiring layer, but also includes a region in contact with the same region. In addition, the “connection” includes, for example, a Steiner wiring or the like that is performed as an estimate for placement.

[0370] 16. An invention according to any one of the aforementioned items 1315, further comprising a step of dividing the integrated circuit into a plurality of regions, wherein the step of dividing the integrated circuit into a plurality of regions is performed. The conversion to the wiring formed by using at least one of the substantially projected areas is performed by at least one of the substantially projected areas onto the actual wiring layer including the number of wiring layers set for each of the above sections. The gist is that the conversion to the wiring formed by using is performed. In the above-described design method, since the conversion into wiring is performed for each section, desired circuit characteristics can be efficiently realized. In particular, in the layout design, wiring is not always laid almost uniformly over all regions of each wiring layer, and a region where wiring is not laid is often formed. In this regard, in the design method described above, by performing the above conversion for each section, the number of actual wiring layers to be expanded is increased in a section including more temporary physical wiring layers in which no wiring is laid, so that the finalized integrated circuit is obtained. It is desirable to appropriately suppress an increase in the number of wiring layers.

In the case where the above-mentioned invention is dependent on the invention described in the above-mentioned item 14, the automatic wiring is performed under the condition that the cost for laying the wiring is defined for each of the above-mentioned sections so as to reduce the cost. You can do it. In this way, for example, for sections where high-speed performance is required, such as sections where adjustment of circuit variables is particularly desired by expanding to the actual wiring layer, a definition that increases the cost is defined. It is possible to reduce the number of temporary physical wiring layers used for laying wiring in the sections. Therefore, in this region, the number of actual wiring layers used for the conversion can be preferentially increased.

[0371] 17. In one aspect of the invention, in the method for designing an integrated circuit according to 16 above, the connection mode by the wiring of substantially the same temporary physical wiring layer over the P-contacted partition is converted. The wiring route of the actual wiring layer straddling each of the sections to be maintained even when The gist of the present invention is to further include a step of setting by arithmetic means using layer switching.

When the above-described conversion is performed for each section in the above-described mode, the mode of conversion into wiring of a plurality of actual wiring layers is not always the same between adjacent sections. Therefore, even in the actual wiring layer which is the same layer between adjacent sections, the wiring laying direction is not necessarily the same. In such places, it may be difficult to connect the wiring between these two sections directly to each other.

In this regard, in the design method described above, the wiring mode of the actual wiring layer that straddles these sections so as to maintain the connection mode by the wiring of the same temporary physical wiring layer even when the conversion is performed is defined by the actual wiring layer. By making use of the transfer, the connection between the two sections can be suitably performed. Note that the “connection” includes, for example, a Steiner wiring or the like that is performed as an estimate for placement.

18. One aspect of the present invention is a semiconductor integrated circuit having a multi-layered wiring structure, wherein wirings are laid in parallel with each other in such a manner that a center line spacing with respect to a line width is an integral multiple of a unit spacing. In addition, the gist is that the region has an adjacent wiring layer in which the laying direction of the wiring is the same.

In the above configuration, since the adjacent wiring layers having the same wiring laying direction are provided, the unit spacing between the adjacent wiring layers can be easily approximated. Therefore, electrical connection between these adjacent wiring layers can be easily performed. In addition, at the time of electrical connection between these adjacent wiring layers, it is possible to preferably avoid occurrence of interference with wiring of the intermediate wiring layer as in the case where an intermediate wiring layer is interposed between the wiring layers. . For this reason, various problems associated with miniaturization can be easily dealt with, and as a result, more efficient design can be performed.

Further, in the above-mentioned area, since the interval of the center line with respect to the line width of the wiring is set to an integral multiple of a predetermined unit interval, the connection at the time of designing the integrated circuit is easily performed according to a regular pattern. You can also. Therefore, especially in the case where the connection of the above-mentioned area is performed by the automatic wiring tool, the programming of the tool can be simplified, and the processing at the time of connection by the tool can be simplified. It is desirable that a logic circuit of an integrated circuit be formed in this region. In contrast, memory, analog circuits, I / O (input / output)

It is desirable that a circuit or the like be formed.

[0373] 19. One invention is the invention according to the above item 18, wherein in the multilayer wiring structure, the unit spacing is set to be larger in an upper wiring layer.

In the above configuration, the so-called reverse scaling rule is applied, in which the unit spacing becomes larger in the upper wiring layer, so that the wiring in the upper wiring layer is more easily reduced in wiring resistance. For this reason, in the upper wiring layer, it is possible to lay a wiring having a long wiring length for connecting portions separated from each other.

In the above configuration, the inverse scaling rule is applied because the wiring layers have adjacent wiring layers in the same wiring direction, but the unit spacing between the adjacent wiring layers is substantially omitted. It can be approximated.

[0374] 20. An aspect of the invention according to the invention described in the above item 18 or 19, wherein the unit spacing is set to be substantially the same in the adjacent wiring layers.

According to the above configuration, since the unit intervals in the adjacent wiring layers are made substantially the same, electrical connection of wiring between the wiring layers can be easily performed.

[0375] 21. The invention according to any one of the aforementioned items 18 to 20, wherein in the adjacent wiring layer, wiring of each layer is laid at an interval larger than the unit interval, and The gist is that the wiring of each layer is laid so as not to overlap when viewed from above the substrate surface of the integrated circuit.

In the above configuration, the distance between adjacent wirings can be increased in the same wiring layer.

The capacitance between adjacent wirings is reduced, and crosstalk noise can be suppressed. When electrically connecting the wiring of the P-wiring layer having the same wiring laying direction to the wiring of another wiring layer having a different wiring laying direction, another layer in the P-wiring layer is required. The wiring can be connected directly without any obstacles, so that the connection can be made easily and the time and load required to calculate the connection route with the automatic wiring tool can be reduced. become [0376] One invention is the invention according to any one of the aforementioned 18-21, wherein a pair of wirings provided adjacent to any one of the adjacent wiring layers is provided. The gist of the present invention is that one of the wires is provided such that one of the wires is transferred to the other wiring layer.

In the above configuration, it is possible to reduce as much as possible a portion adjacent to a pair of wirings in the same wiring layer, and thus to appropriately reduce the capacitance between the pair of wirings. become. In addition, since the transfer is performed between adjacent wiring layers, it is possible to avoid interference with wiring of another wiring layer at the time of transfer, as in the case where another wiring layer is provided between wiring layers to be transferred.

[0377] 23. The invention according to any one of 1822, wherein one of the adjacent wiring layers has a first wiring having a fixed potential and a signal transmission wiring. Wirings are provided adjacent to each other, and the other wiring layer has a fixed potential formed so as to include a projection area of the signal transmission wiring onto the other wiring layer. The gist is that a second wiring is formed, and the first and second wirings are electrically connected to form a shield wiring of the signal transmission wiring.

In the above configuration, the shield wiring is configured using the adjacent wiring layers. This avoids the interference between the electrical connection between the shield wirings and the wiring of the another wiring layer as in the case where another wiring layer is provided between the wiring layers in which the wiring forming the shield wiring is provided. be able to. This makes it possible to configure shielded wiring that does not significantly damage wiring resources, and can easily implement measures against crosstalk and electromagnetic interference (EMI).

[0378] 24. One invention is a semiconductor integrated circuit having a multilayer wiring structure, wherein a wiring for signal propagation and a first wiring having a fixed potential are provided on one of the wiring layers that are in P contact. In addition to being provided in parallel with and adjacent to each other, the other wiring layer has a fixed potential formed so as to include a projection area of the signal transmission wiring onto the other wiring layer. A second wiring is formed, and the first and second wirings are electrically connected to form a shield wiring of the signal transmission wiring. In the above configuration, the shield wiring is configured using the adjacent wiring layers. This avoids the interference between the electrical connection between the shield wirings and the wiring of the another wiring layer as in the case where another wiring layer is provided between the wiring layers in which the wiring forming the shield wiring is provided. be able to. This makes it possible to configure shielded wiring that does not significantly damage wiring resources, and can easily implement measures against crosstalk and electromagnetic interference (EMI).

[0379] 25. One invention provides a method for designing a semiconductor integrated circuit, in which wiring is performed on a semiconductor integrated circuit on which layout has been completed by using an automatic wiring tool, wherein the wiring is laid in a wiring direction between adjacent wiring layers. The gist is that the process is performed while setting the same wiring layer. In the above-mentioned design method, since the wiring is performed while setting the adjacent wiring layers in which the wiring laying direction is the same, the distance between the center line and the line width of the wiring laid in parallel with each other is defined as a unit spacing. When set to an integer multiple, the unit spacing between adjacent wiring layers can be approximated. Therefore, electrical connection between adjacent wiring layers can be easily performed. Further, it is possible to avoid the occurrence of interference between the electrical connection between adjacent wiring layers and the wiring of the intermediate wiring layer, as in the case where an intermediate wiring layer is interposed between adjacent wiring layers. For this reason, various problems associated with miniaturization can be easily dealt with, and more efficient design can be achieved.

[0380] 26. The invention according to the above item 22, wherein in the adjacent wiring layer, wiring of each layer is laid at an interval larger than the unit interval, and a substrate of the semiconductor integrated circuit is provided. The gist of the present invention is to perform the connection while further setting a region where the wiring of each layer is not overlapped when viewed from above.

In the above design method, the distance between adjacent wirings can be increased in the same wiring layer, so that the capacitance between P-connected wirings is reduced, and crosstalk noise can be suppressed. When electrically connecting wiring in an adjacent wiring layer having the same wiring laying direction and wiring in another wiring layer having a different wiring laying direction, wiring in another layer in the adjacent wiring layer is not required. Since direct connection is possible without any obstacles, the connection can be made easily and the time and load required to calculate the connection route with the automatic wiring tool can be reduced.

[0381] One invention uses an automatic wiring tool for a semiconductor integrated circuit whose arrangement has been completed. In the method of designing a semiconductor integrated circuit for performing connection by wiring, it is preferable that, in the connection, under a predetermined condition where adjustment of electrical characteristics of the wiring is desired, a region in which the wiring direction is the same between adjacent wiring layers is provided. This is the gist.

In the above-described design method, by setting a region where the wiring laying direction is the same between adjacent wiring layers, the unit spacing between adjacent wiring layers can be approximated. Therefore, in this region, electrical connection between the wiring layers that are in P-contact can be easily performed. Further, in this region, it is possible to avoid interference between the electrical connection between the adjacent wiring layers and the wiring of the intermediate wiring layer as in the case where an intermediate wiring layer is interposed between the wiring layers adjacent to each other. . Therefore, the adjustment of the electrical characteristics of the wiring for which the adjustment of the electrical characteristics is desired can be easily performed, and the more efficient design can be achieved.

[0382] One invention is the invention according to the above item 23, wherein the shielded wiring is a wiring that is desired to be a countermeasure against noise as a wiring that satisfies a predetermined condition for which adjustment of the electrical characteristics is desired. When the laying area is set, when a potential fixed wiring, which is a wiring having a fixed potential, is laid in a region adjacent to the laying region and a region where the laying region is projected on at least one of the upper layer and the lower layer of the laying region. Under the above conditions, the gist is to lay the fixed potential wiring and the shielded wiring in the same wiring direction by using the automatic wiring tool.

In the above-described design method, a potential fixed wiring as a shield wiring having a fixed potential for shielding the shielded wiring is configured using the adjacent wiring layer. Thus, it is possible to prevent the electrical connection between the shielded wirings from interfering with the wiring of the another wiring layer as in the case where another wiring layer is provided between the wiring layers in which the wiring forming the shielded wiring is provided. Can be done. This makes it possible to configure shielded wiring that does not significantly damage wiring resources, and can easily implement measures against crosstalk and electromagnetic interference (EMI).

[0383] Note that the following technical ideas can be grasped from each of the above embodiments and modifications thereof.

A method for designing an integrated circuit according to any one of the above 13 to 15,

At least one of the regions substantially projected onto the actual wiring layer comprising the plurality of wiring layers The conversion to the wiring formed by using: a. Laying the predetermined wiring of the temporary physical wiring layer in at least two wiring layers in an area where the predetermined wiring is substantially projected onto the real wiring layer. B. Convert the predetermined wiring of the temporary physical wiring layer into at least two wiring layers in a region where the predetermined wiring is substantially projected onto the real wiring layer. A pair of wirings laid in the area and converted in series with each other and connected in parallel with each other in the temporary physical wiring layer are transferred to the actual wiring layer. One that is laid in a plurality of wiring layer areas of the substantially projected area and converted into a wiring connected to each other; d. A pair of wirings composed of wirings that are closest to each other in the temporary physical wiring layer The pair of wirings were approximately projected onto the actual wiring layer. E. A pair of wirings in the region and converted to wirings provided so that the pair of wirings are different wiring layers from each other; e. A pair of wirings composed of wirings closest to each other in the temporary physical wiring layer Converting at least two wiring layers out of a region where the pair of wirings are substantially projected onto the actual wiring layer into wirings provided so as to be alternately switched via via holes; f A plurality of potential fixed wirings, which are a plurality of wirings fixed to different potentials in the temporary physical wiring layer, and a signal transmission wiring are connected to at least one of the plurality of potential fixed wirings and the signal transmission wiring. A method for designing an integrated circuit, characterized in that at least one of the two wirings is converted into wiring formed by changing wiring layers.

Industrial applicability

As described above, the present invention is applicable to an integrated circuit, an integrated circuit design method, and the like.

Claims

The scope of the claims

[1] An integrated circuit having a multilayer wiring structure formed on a substrate,

Wirings laid on a plurality of wiring layers in such a manner that they have substantially the same path directions as each other and that the projection of the integrated circuit onto the substrate overlaps each other.

A wiring laid on the plurality of wiring layers is connected via a via hole, thereby connecting two desired points of the integrated circuit, and is an arbitrary two element. , Wiring that fixes the potential of a specific terminal of an arbitrary element, and wiring in which one end of the wiring is substantially open. An integrated circuit characterized by:

[2] An integrated circuit having a multilayer wiring structure formed on a substrate,

A first wiring connecting desired two points of the integrated circuit;

A second wiring laid on a different wiring layer from the wiring layer on which the first wiring is laid, wherein the first wiring and the second wiring are projected on the substrate so that One wiring connecting the desired two points by being laid in an overlapping manner and being connected via a via hole, and connecting between specific terminals of any two elements; An integrated circuit, comprising: a wiring for fixing the potential of a specific terminal of an arbitrary element; and a wiring in which one end of the wiring is substantially open.

[3] An integrated circuit having a multilayer wiring structure formed on a substrate,

A first wiring connecting desired two points of the integrated circuit;

A second wiring parallel to the first wiring laid on a wiring layer different from the wiring layer laid on the first wiring;

The first wiring and the second wiring constitute one wiring connecting the desired two points by electrically connecting the second wiring to the first wiring in parallel. An integrated circuit characterized by:

[4] An integrated circuit having a multilayer wiring structure formed on a substrate,

A plurality of wirings laid in parallel with a plurality of wiring layers in such a manner that projections on the substrate overlap with each other, The plurality of wirings are electrically connected in series via a via hole in a manner of inverting the signal propagation direction for each wiring layer, thereby connecting two desired points of the integrated circuit. An integrated circuit, comprising:

[5] An integrated circuit having a multilayer wiring structure formed on a substrate,

A region in which the wiring laying direction and the laying interval are substantially the same between adjacent wiring layers, and

In the region, the wiring laid on one of the wiring layers that are in contact with the P is smaller than the wiring laid on the other wiring layer in a direction perpendicular to the laying direction and smaller than the wiring laying interval. An integrated circuit having a portion provided in a manner offset in a range.

[6] An integrated circuit having a multilayer wiring structure formed on a substrate,

At a portion where one of the first wiring and the second wiring is laid on a certain wiring layer, the other wiring is laid so as to escape to another wiring layer, and An integrated circuit, wherein the first wiring and the second wiring are laid in parallel so that projections on the substrate are adjacent to each other.

[7] An integrated circuit having a multilayer wiring structure formed on a substrate,

A first pair of wirings laid adjacently and parallel to each other on a predetermined wiring layer; and a second pair of wirings laid adjacently and parallel to each other on a wiring layer different from the predetermined wiring layer. ,

The second pair of wirings is provided in such a manner that the first pair of wirings and the projection on the substrate overlap with each other, and one end of the first pair of wirings is provided via a via hole. Wherein the second pair of wires is formed as a dummy wire whose other end is substantially open.

[8] An integrated circuit having a multilayer wiring structure formed on a substrate,

A first wiring configured by connecting wiring laid on a plurality of wiring layers in parallel via via holes;

A second wiring formed by connecting wirings laid on the same wiring layer as a plurality of wiring layers on which the wirings constituting the first wiring are laid in parallel via via holes, An integrated circuit, wherein the wirings constituting the first wiring and the second wiring are provided adjacently and in parallel in the same wiring layer corresponding to each other.

[9] An integrated circuit having a multilayer wiring structure formed on a substrate,

A first wiring configured by electrically connecting wirings laid on a plurality of wiring layers in such a manner that projections on the substrate overlap with each other through via holes,

Wirings laid in the same wiring layer as the plurality of wiring layers on which the wirings constituting the first wiring are laid in such a manner that projection onto the substrate overlaps are electrically connected in series via via holes. A second wiring configured by

An integrated circuit, wherein the wirings constituting the first wiring and the second wiring are provided adjacently and in parallel in the same wiring layer corresponding to each other.

[10] An integrated circuit having a multilayer wiring structure formed on a substrate,

Wiring for signal propagation;

A plurality of potential fixing wires fixed to different potentials,

Any one of the signal transmission wiring and the potential fixing wiring is laid so as to allow a part of the wiring to escape to another wiring layer, and at this time, the signal transmission wiring and the wiring An integrated circuit, wherein the plurality of potential fixing wirings are laid so as to allow the projections on the substrate to be adjacent to each other.

[11] An integrated circuit having a multilayer wiring structure formed on a substrate,

11. The integrated circuit according to claim 3, further comprising a region having a plurality of wiring layers in which the wiring is laid in substantially the same direction and at an integer multiple of a unit interval defined in advance, wherein the region is provided within the region. An integrated circuit, wherein at least one of the circuits is formed.

12. The integrated circuit according to claim 11, wherein adjacent regions have different wiring laying directions in at least one wiring layer.

[13] In a wiring of a wiring layer in which wiring laying directions are different from each other in the adjacent region, in the wiring which is a connection between the adjacent regions, another wiring is formed in such a manner that the projection onto the substrate is in a straight line. 13. The integrated circuit according to claim 12, wherein the connection is made using a wiring laid on the layer.

[14] The wiring layer in the integrated circuit in which the layout is realized is set as a temporary physical wiring layer, and In order to make the circuit characteristics of each wiring of a predetermined temporary physical wiring layer of the wiring layers into desired circuit characteristics, at least an area of the region where each of the wirings is substantially projected onto a plurality of real wiring layers having a plurality of wiring layers by arithmetic means. A method for designing an integrated circuit, comprising a step of converting into a wiring formed using one region.

[15] In an integrated circuit design method for determining a wiring route related to connection of each element of an integrated circuit,

The wiring layer for performing the connection is defined as a temporary physical wiring layer, and each wiring of the predetermined temporary physical wiring layer is formed using at least one of regions substantially projected onto an actual wiring layer including a plurality of wiring layers. A circuit route obtained on the temporary physical wiring layer is optimized based on a result of the prediction while predicting a circuit characteristic obtained when the wiring is converted into an integrated circuit.

[16] An integrated circuit design method for arranging each element of the integrated circuit is described below.

A wiring layer in each part of the integrated circuit where a connection is made is defined as a temporary physical wiring layer, and each wiring of the predetermined temporary physical wiring layer in the integrated circuit in which the connection is made is formed by a plurality of wiring layers. It is characterized by optimizing the arrangement of each element based on the prediction result while predicting the circuit characteristics obtained when converted to wiring formed using at least one of the regions substantially projected onto the layer. Integrated circuit design method.

[17] In an integrated circuit design method for determining a circuit configuration of an integrated circuit,

A wiring layer for performing connection required for the circuit configuration is a temporary physical wiring layer, and at least one area of a region where each wiring of a predetermined temporary physical wiring layer is substantially projected onto a real wiring layer including a plurality of wiring layers A method for designing an integrated circuit, comprising: optimizing a circuit configuration based on a result of a prediction while predicting a circuit characteristic obtained when the wiring is converted into a wiring formed using the integrated circuit.

[18] laying temporary wiring, which is used virtually at the time of design, on a temporary physical wiring layer to connect the laid out circuit elements to form a circuit block;

Determining by a computing means whether various characteristics of the circuit block formed by the laying mode of the temporary wiring satisfy desired characteristics;

The temporary wiring laid in the temporary physical wiring layer is actually distributed to the actual wiring layer where the actual wiring is laid. Evolving as lines,

The provision of the temporary wiring on the actual wiring layer is performed by transferring the temporary wiring laid on one temporary physical wiring layer to a plurality of corresponding real wiring layers and satisfying the desired characteristics by the determination. Actual wiring in the area where the circuit block determined to be transferred is transferred using the wiring of the plurality of actual wiring layers so that the circuit block satisfies desired characteristics. Integrated circuit design method.

[19] The method further includes a step of dividing the integrated circuit into a plurality of sections.

19. The integrated circuit design method according to claim 18, wherein the correspondence between the temporary physical wiring layer and the real wiring layer is made different for each of the plurality of divided sections.

[20] The result of dividing the section, making the correspondence between the temporary physical wiring layer and the actual wiring layer different for each section, and developing the wiring from the temporary physical wiring layer to the actual wiring of the real wiring layer In the case where the laying directions of the wirings are different from each other in the adjacent section, the wiring for connecting across the adjacent section is maintained by the arithmetic means in the connection mode at the time of wiring in the temporary physical wiring layer. A method of designing an integrated circuit, wherein the wiring is laid as real wiring formed by expanding from a temporary physical wiring layer to a plurality of real wiring layers.

[21] An integrated circuit having a multilayer wiring structure formed on a substrate,

In a mode in which the laying interval between adjacent wirings is an integral multiple of a unit interval predefined for each wiring layer, the wiring has an area in which a plurality of wirings are laid in parallel with each other,

The integrated circuit according to claim 1, wherein the region includes at least a pair of adjacent wiring layers in which wiring directions are the same.

22. The integrated circuit according to claim 21, wherein a unit interval predetermined for each of the wiring layers is set to be substantially the same in the pair of adjacent wiring layers.

[23] In the pair of adjacent wiring layers, a plurality of wirings are laid at an interval of at least twice the unit interval,

23. The integrated circuit according to claim 21, wherein the plurality of wirings laid on the pair of adjacent wiring layers are laid so as to be offset so that projections on a substrate do not overlap each other. circuit.

[24] One of the pair of adjacent wiring layers may include two adjacent wiring layers. Wiring is laid,

Any one of the two adjacent wirings is laid so that the distance between the two adjacent wirings is substantially increased by switching to the other wiring layer via the via hole. 23. The integrated circuit according to claim 21, wherein:

[25] A signal transmission wiring and a potential fixing first wiring are laid adjacent to each other on one of the pair of adjacent wiring layers,

A second wiring for fixing potential is laid on the other wiring layer so as to include a region formed by projecting the signal transmission wiring onto the other wiring layer,

23. The integrated circuit according to claim 21, wherein the first and second wirings are electrically connected to form a shield wiring of the signal transmission wiring.

[26] An integrated circuit having a multilayer wiring structure formed on a substrate,

In one of the pair of adjacent wiring layers, a signal transmission wiring and a potential fixing first wiring are laid in parallel and adjacent to each other, and

An integrated circuit, wherein the first and second wirings are electrically connected to form a seamless wiring of the signal transmission wiring.

[27] A method for designing an integrated circuit having a multilayer wiring structure formed on a substrate,

A step of laying wiring in a plurality of wiring layers by an automatic wiring tool in order to connect the laid out circuit elements, wherein the automatic wiring tool sets an area in which wiring laying directions are the same between adjacent wiring layers. A method of designing an integrated circuit, wherein wirings of adjacent wiring layers in the region are laid at intervals of an integral multiple of a predetermined unit interval.

[28] The automatic wiring tool converts the wiring laid on one of the adjacent wiring layers in the area in a direction perpendicular to the laying direction with respect to the wiring laid on the other wiring layer. 28. The method for designing an integrated circuit according to claim 27, wherein the wiring is laid in a mode in which the wiring is offset within a range smaller than the wiring laying interval.

29. The method of designing an integrated circuit according to claim 27, wherein the automatic wiring tool sets, as the area, a range in which wiring requiring adjustment of electrical characteristics is laid.

[30] The automatic wiring tool, when laying wiring for signal propagation in which electrical noise is required to be reduced in the area, lays out the wiring for signal propagation in one wiring layer in the area. A wiring for potential fixing functioning as a shield wiring in a mode including the projection of the signal transmission wiring is provided on a wiring layer that is laid and adjacent to the one wiring layer and has the same wiring laying direction. 30. The method for designing an integrated circuit according to claim 29, wherein the integrated circuit is laid.