JPH0997841A - Method for designing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To design the interconnection for clock signal in a semiconductor device such that the delay between interconnections due to limitation of layout in conventional clock synthesis technology is eliminated. SOLUTION: When a clock distribution circuit is laid out a capacity region 13 is provided previously in a semiconductor element region provided as a butter region 12. After the delay of clock signal is calculated between interconnections, a capacity layout pattern having an equivalent delay time is generated automatically and substituted for that in the capacity area 13 of clock distribution circuit thus eliminating the delay between interconnections substantially.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a semiconductor device for automatic placement and routing, and more particularly to a method of adjusting skew between clock signals.

[0002]

2. Description of the Related Art A conventional clock synthesis technique will be described with reference to a plan view of a semiconductor chip shown in FIG.
The semiconductor chip 1 is composed of an internal region 2, a connection pad 4 connected to the outside, and an input / output region 3 between them. In the internal area 2, there are clock distribution circuits 6 and 7A.
.About.7D, flip-flops 8A to 8D, and internal wirings 9, 10A to 10D, 11A to 11D. When receiving a clock signal from the outside, it is received by the external input buffer 5 in the input / output area 3 and connected to the first clock distribution circuit 6 connected by the internal wiring 9 passing through the inside of the internal area 2. Clock distribution circuit 6 to internal wiring 10A
Second clock distribution circuits 7A to 7D which are connected with each other
To the flip-flops 8A to 8D via the internal wirings 11A to 11D.

Next, a clock signal distribution method using the conventional clock synthesis technique will be described. As shown in FIG. 4, flip-flops 8A1-8A4, 8B1-8
It is assumed that B4, 8C1 to 8C3, 8D1 to 8D4 are already arranged by the automatic arrangement design. When the clock signal is distributed here, first the flip-flops 8A1 to 8A1
A4 / 8B1-8B4 / 8C1-8C3 / 8D1-8D
Are divided into areas, and the second clock distribution circuits 7A to 7D are provided for the areas of these flip-flops.
Place. The second clock distribution circuit 7A is arranged in such a position that the clock wirings 11A1 to 11A4 have substantially equal lengths with respect to the flip-flops 8A1 to 8A4 divided for each area.

Similarly, for the second clock distribution circuits 7B to 7D, the clock wirings 11B1 to 11B4 are individually provided.
11C1 to 11C3 and 11D1 to 11D4 are arranged at locations having the same length, and clock wirings 11A1 to 11A
4, 11B1-11B4, 11C1-11C3, 11D
1 to 11D4 are connected.

Next, the first clock distribution circuit 6 determines the clock wiring 1 for each arrangement of the second clock distribution circuits.
The clock wirings 10A to 10D were connected to the clock wirings 10A to 10D, which were arranged at locations where the lengths of 0A to 10D were substantially equal. As described above, the flip-flops 8A1 to 8A4, 8B1 to 8B4, 8C1 and 8C38 located at the end of the first clock distribution circuit 6 are connected.
The wiring skews of D1 to 8D4 were set to be substantially equal.

[0006]

In the above-mentioned conventional clock synthesis technique, the clock wirings 10A1 to 10A4 and 10B are provided in order to equalize the capacity of the clock signal wirings.
1-10B4, 10C1-103, 10D1-10D4
There is a problem in that it is necessary to additionally route 11A to 11D, so that the wiring region is lost, and as a result, the automatic wiring property is deteriorated. In addition, the first clock distribution circuit 6
And a second clock distribution circuit 7A to 7D, or between the second clock distribution circuit 7A to 7D and each flip-flop 8, there is a circuit having a large area,
In order to avoid the circuit having the large area region, the clock wirings 10 and 11 are laid around, and as a result, there is a problem that the wiring skew occurs between several tens ps and several hundreds ps.

An object of the present invention is to provide a method of designing a semiconductor device in which wirings are reduced, automatic wiring performance is improved, and skew between wirings is significantly reduced.

[0008]

According to the structure of the present invention, a semiconductor element formation region is provided as a capacitance region in a part of a layout of a clock distribution circuit that distributes a clock signal to each unit circuit, and a delay of each clock wiring is provided. In a method of designing a semiconductor device in which the amount of wiring is adjusted, the clock distribution circuit and each of the unit circuits are provisionally connected to obtain respective wiring delay amounts, and each wiring with respect to the maximum delay amount of these wiring delay amounts. The difference with the delay amount is obtained, the delay amount difference is formed into the capacitance regions having the capacitance values corresponding to the respective delay amount differences, and the capacitance regions are connected to the clock wirings, respectively. The feature is that the wiring delay amount is adjusted to be equal.

[0009]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings. 1A and 1B are a layout diagram of a semiconductor device and an equivalent circuit diagram thereof for explaining an embodiment of the present invention. In this case, as shown in FIG. 1A, the buffer area (region) 12 is formed by connecting transistors (semiconductor elements) including a diffusion region 15 and a gate region 17 by an aluminum wiring region 16, and A part of the region is connected by an aluminum wiring 14 to form a capacitance region 13. Therefore, the equivalent circuit is, as shown in FIG. 1B, the transistors Q1 to Q4 and the capacitor (capacitance) C1.
It is shown by the circuit consisting of and. In this capacitance region 13, the width and length of the aluminum wiring 14 in the element region can be changed to form a capacitance having an arbitrary capacitance value.

The cause of the delay of the wiring is mainly due to the resistance component and the capacitance component of the wiring itself. When the resistance component is R and the capacitance component is C, the wiring delay T is T = C.multidot.C. It can be obtained by the formula of R. Therefore, in the case of the present embodiment, each of the clock distribution circuits 6 and 7 as in FIG.
Flip-flop (unit circuit) 8 connected to the end
When the difference in delay time generated in the wirings 10 and 11 is different, the capacitance area 13 is added to adjust the delay amount of the aluminum wirings 10 and 11 of each clock distribution circuit as shown in FIG. The delay difference between them can be made almost zero.

Next, a method of adjusting the delay difference between wirings by the semiconductor device designing method of the present invention will be described with reference to the flowchart of FIG. First, in step S1, each clock distribution circuit and flip-flop are arranged and wired using the conventional clock synthesis technique. After this processing S1 is completed, the wiring length from each clock distribution circuit to the flip-flop is obtained and the wiring delay is obtained in step S2.

For example, in S2, the second clock distribution circuit 7A
After obtaining the wiring delays of the individual clock wirings 11A1 to 11A4 from .about.7D to the respective flip-flops 8A1 to 8A4, the average wiring delay is calculated. This second
From clock distribution circuit 7A to flip-flops 8A1-8
The wiring delay up to A4 is t1. With this calculation, the wiring delay from each second clock distribution circuit (7) to the flip-flop (8) is obtained.

Next, in step S3, wiring delays of the clock wirings 10A to 10D from the first clock distribution circuit 6 to the second clock distribution circuits 7A to 7D are obtained. The wiring delay from the first clock distribution circuit 6 to the second clock distribution circuit 7A is t2. Therefore, the wiring delay from the first clock distribution circuit 6 to the flip-flops 8A1 to 8A4 is calculated by t = t1 + t2 (step S4). Similarly, other wiring delays can be obtained. The latest time of each wiring delay thus obtained is tmax. Therefore, in step S5, the inter-wiring delay time Δt is obtained by subtracting each wiring delay from this tmax.

In the next step S6, a pattern of the capacitance area 13 having a wiring time equivalent to the inter-wiring delay time Δt obtained in S5 is automatically formed from the patterns provided in the file S8 in advance. The inter-wiring delay can be reduced to almost zero simply by replacing the layout of the capacitance area B added to the buffer area 12 of the clock distribution circuit in step S7.

FIG. 3 is a layout diagram for explaining the second embodiment of the present invention. In this layout, the aluminum wiring 14 of the capacitance area 13 of the first embodiment is replaced by the diffusion area 1
It is replaced with a capacity of 5. Also in this case, a similar capacity area can be formed.

[0016]

As described above, according to the method for designing a semiconductor device of the present invention, dozens of delays between wirings from an externally applied clock signal to each flip-flop arranged in the semiconductor device are provided. There is an effect that ~ several hundreds ps can be made almost zero. In addition, since a capacitance area is provided in advance in the layout area of each clock distribution circuit and automatic processing is performed, an arbitrary capacitance layout pattern can be automatically generated, and it is not necessary to route extra wiring. There is also an effect of improving the wiring property to.

[Brief description of drawings]

1A and 1B are a layout diagram and an equivalent circuit diagram for explaining an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an embodiment of the present invention.

FIG. 3 is a layout diagram of a capacity area for explaining another embodiment of the present invention.

FIG. 4 is a chip layout diagram illustrating a conventional clock synthesis technique.

[Explanation of symbols]

1 Semiconductor Chip 2 Internal Area 3 External Input / Output Area 4 External Connection Pad 5 External Input Buffer 6 First Clock Distribution Circuit 7A-7D Second Clock Distribution Circuit 8A1-8A4 / 8B1-8B4 / 8C1-8C3.8
D1-8D4 flip-flops 9 / 10A-10D / 11A1-11A4 / 11B1-
11B4 / 11C1 to 11C3 / 11D1 to 11D4
Clock wiring 12 Buffer layout 13 Capacitance area 14 Aluminum wiring 15 Diffusion area 16 Contacts 17 Gate area

Claims (3)

[Claims] 1. A semiconductor device in which a semiconductor element formation region is provided as a capacitance region in a part of a layout of a clock distribution circuit for distributing a clock signal to each unit circuit, and a delay amount of each clock wiring is adjusted. In the design method, the clock distribution circuit and each of the unit circuits are provisionally connected to obtain respective wiring delay amounts, and a difference between each wiring delay amount with respect to a maximum delay amount among these wiring delay amounts is obtained, respectively, The delay amount difference is adjusted so that the capacitance regions having the capacitance values corresponding to the respective delay amount differences are formed and these capacitance regions are connected to the respective clock wirings so that the wiring delay amounts of the respective wirings become equal. A method for designing a semiconductor device, comprising: 2. The method for designing a semiconductor device according to claim 1, wherein a metal wiring is used in a formation region of a semiconductor element serving as a buffer as a capacitance region. 3. The method for designing a semiconductor device according to claim 1, wherein a diffusion region of a formation region of a semiconductor element serving as a buffer is used as the capacitance region.