JPS63293941A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To avoid clock skew, and increase the speed, by providing a specific clock signal line with a capacitance element. CONSTITUTION:For a logic integrated circuit, a capacitance element Ca is arranged in a basic cell, and clock skew is reduced by the capacitance element Ca. For a gate array, the capacitance element Ca. For a gate array, the capacitance element Ca is arranged in, e.g., all basic cells 3A. This capacitance element Ca is connected with clock signal lines of the respective clock drivers driving a load capacitance smaller than the maximum load capacitance, among a plurality of clock drivers connected with the same terminal. The capacitance element Ca is constituted of, e.g., an N<+> semiconductor region formed by the same working process as the emitter region 12 of a transistor 5, a thin silicon oxide film 14, and a first layer aluminum film 16 formed thereon. Thereby, the difference between load capacitances of clock drivers is made nearly zero, so that the clock skew can be avoided, and the high speed operation is enabled.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device that configures logic.
It is particularly effective when applied to semi-custom logic integrated circuit devices such as gate arrays and standard cell systems.

[Prior art]

In gate array and standard cell type logic integrated circuit devices, various registers and counters are configured in the logic area. Flip-flop (F/F) circuits forming these registers and counters operate in synchronization with a clock signal. In order to reduce attenuation and delay due to load capacitance, this clock signal is supplied to each flip-flop circuit through several clock drivers provided on the chip. However, the wiring length from the clock signal input terminal to each clock driver and the wiring length from each clock driver to each flip-flop circuit are different, and the number of fan-outs of each clock driver is also different.

Therefore, a time lag (clock skew) occurs in the clock signals supplied to each flip-flop circuit. Therefore, a technology for reducing clock skew by detouring clock signal lines with short wiring lengths was proposed in Information Processing Society of Japan Research Report, 1986, Vo 1.86. No. 7
0 r large high-density substrate lauter system”.

[Problem that the invention seeks to solve]

The inventor of the present invention discovered that with the method of reducing clock skew by detouring clock signal lines with short wiring lengths, it is difficult to significantly detour due to changes in wiring layout, excessive wiring density, etc. It was found that the skew reduction rate was small.

An object of the present invention is to reduce clock skew and increase speed.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of one typical invention disclosed in this application is as follows.

That is, a capacitive element is provided on a predetermined clock signal line extending from the circuit.

[Effect]

According to the above-mentioned means, the difference in load capacitance between each clock driver due to the difference in wiring length or the difference in the number of fan-outs is eliminated, so clock skew can be eliminated.
You can measure the speed.

[Embodiment of the invention■]

Embodiment I of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of a standard cell type semi-custom integrated circuit.

In FIG. 1, reference numeral 1 denotes a substrate made of P-single-crystal silicon, and around it a bonding pad Pad formed by laminating, for example, a first layer and a second layer of aluminum film.
There are multiple locations. In addition, the pounding pad Pad
An input buffer circuit 2 or an output buffer circuit 2 composed of, for example, a bipolar transistor or a resistor element is provided inside the circuit (hereinafter simply referred to as the buffer circuit 2).
.

The area surrounded by the buffer circuit 2 is an internal logic area in which various logic circuits, registers, counters, drivers, etc. It consists of cell 3A. Wiring channels 4 are formed between the basic cell rows 3 and around the basic cell rows 3.

Here, FIG. 2 shows an example of the layout of elements provided in one basic cell 3A, and FIG. 3 shows an example of the cross-sectional structure of a bipolar transistor provided in the basic cell 3A.

As shown in FIG. 2, one basic cell 3A includes, for example,
It is configured by providing five bipolar transistors 5 and four resistance elements 6. The bipolar transistor 5 is the third
As shown in the figure, N″″″embedding 9, N″collector area 1
0, P type base region 11, N emitter region 12, N3
It is composed of a pull-out area 13. Reference numeral 7 denotes a field insulating film made of a silicon oxide film formed by thermally oxidizing an epitaxial layer, that is, a single crystal silicon layer, and a P-type channel stopper region 8 is formed below the field insulating film.

The surface of the substrate 1 exposed from the field insulating film 7 is
It is covered with a thin silicon oxide film 14 formed by thermal oxidation.

Base region 11, emitter region 12, extraction region 13
An electrode 16 made of a first layer of aluminum film is connected to each of the electrodes 16 through an opening 15 formed by removing the silicon oxide film 14. On the electrode 16, for example, phosphosilicate glass (PS) is formed on a silicon oxide film formed by CVD.
a) Covered by a first layer interlayer insulating film 17 formed by laminating films. Although not shown, a wiring made of a second layer of aluminum film extends over this interlayer insulating film 17. On top of the wiring made of the second layer of aluminum film is a second layer formed by laminating a coated glass (SOG) film on a silicon oxide film by CVD, for example, and then a PSG film on top of that. An interlayer insulating film 18 is provided. The resistive element 6 shown in FIG. 2 consists of a P-type semiconductor region formed in the same process as the base region 11 of a bipolar transistor, for example.

Next, FIG. 4 shows an example of connections between the basic cells 3A of this embodiment.

FIG. 4 is a plan view schematically showing a part of the integrated circuit of Example 2 of the present invention.

In this embodiment, the capacitive element Ca is configured using the regions of several basic cells 3A. Note that FIG. 4 shows one capacitive element Ca. D2 is a clock driver, and F/F is a flip-flop circuit. These clock drivers D, Dl, and flip-flop circuits F
/F is configured in one basic cell 3A in FIG. 4, but it may also be configured using the transistor 5 and resistance element 6 in one basic cell 3A, or it can be configured by using a plurality of neighboring basic cells. For example, the wiring channel 4 may be connected between the transistors 5 and the resistance elements 6 in the basic cell 3A using the wiring 16 made of the first layer of aluminum film. A second layer of aluminum film is used for the wiring 23 extending in the same direction as the cell row 3, and the wiring 24 extending in the direction crossing the basic cell row 3
for.

For example, a third layer of aluminum film is used.

Note that in FIG. 4 and FIGS. 8, 9, and 10 used in later explanations, the wiring 23.
24 is a clock signal line that supplies a clock signal.

22 is a power supply circuit, and 21 is a power supply wiring channel in which wiring connecting between the power supply circuits 22 is provided. In addition,
These power supply wiring channel 21 and power supply circuit 22 are not shown in FIG.

Clock driver D4 and clock driver D2 are connected to the same terminal IN, that is, for example, the output terminal of clock driver D in the previous stage, but five flip-flops F/F are connected to clock driver D1, and clock driver D2 is connected to five flip-flops F/F. Three flip-flop F/Fs are connected, and the fan-out numbers are different. This same terminal I
To eliminate clock skew due to the difference in fan-out numbers of clock drivers D1 and D8 connected to N.

A capacitive element Ca is connected to the clock driver D3.

The capacitive element Ca is used in a standard cell type semiconductor integrated circuit device like this embodiment.

For example, it is formed in the region of one basic cell 3A using a part of the manufacturing process of the transistor 5, for example.

A gate array using a bipolar transistor as the basic cell 3A is constructed using the junction capacitance between the emitter region 12 and base region 11 or the junction capacitance between the base region 11 and collector region 10 of the bipolar transistor. In a gate array using a MISFET as the basic cell 3A, the capacitance of the gate electrode of the MISFET is used.

Next, an example of the structure of the capacitive element Ca will be explained.

FIG. 5 is a plan view of the capacitive element, and FIG. 6 is a sectional view taken along the line 1-1 in FIG. 5. Note that FIG. 5 does not illustrate any insulating films other than the field insulating film 7. The capacitive element Ca is made of 1, for example, an N° semiconductor region 12 formed in the same process as the emitter region 12, and a thin silicon oxide film 14 thereon. ．． It is composed of a first layer of aluminum film 16A on top of this. Since the capacitive element Ca is formed in the same process as the bipolar transistor, there is an N− semiconductor region (epitaxial layer) under the N− semiconductor region 12.
10. An N'' buried layer 9 is provided. Aluminum tl 16A is provided on the silicon oxide film 14 in an elongated pattern.

The ends of the aluminum M16A on this N2 semiconductor region 12 are integrated on the field insulating film 7, and connected to the clock signal wiring through the second or third layer aluminum wiring (not shown). ing. The respective aluminum films 16A on the silicon oxide film 14 have approximately the same width and are repeatedly provided at predetermined intervals. For example, the first semiconductor region 12 has a
For example, a ground potential Vss, for example, 0.times., is applied through a wiring made of a second or third layer of aluminum film (not shown) to the layered aluminum wiring 161.

Here, the maximum load capacitance driven by the clock driver D (D□ in FIG. 4) connected to the same terminal IN is set as CMA,l, and the other clock drivers D
One of the clock drivers D (in Fig. 4)
If the load capacity of C is CL, then this load capacity C,, is C
, 4A, -C, is less than the maximum one. This small load capacity is made up of the load capacitance Ca, and the load capacity C
, to the clock driver D that drives the . Similarly, for the clock driver D that drives the other load capacitors CL, the capacitive element Ca is configured to have a capacitance value that is the difference between the maximum load capacitance (: N A Ca is connected to a clock driver D that drives each load capacitance C, .The capacitance obtained by one aluminum film 16A on the silicon oxide film 14 is set as C0, and the aluminum film on the silicon oxide film 14 When the number of films 16A is K, the capacitance value of the capacitive element Ca is K·C0.Aluminum 1lI16A to be provided on the silicon oxide film 14
The number of lines is obtained by CC-A-Ct, )/C0. This capacitive element Ca connects the clock signal input pin (ponding pad Pad) to the flip-flop circuit F.
Of the several clock drivers D provided up to /F, the final stage, that is, the most flip-flop circuit F
Connect to clock driver D near /F.

This is because the clock skew caused by the difference in the fan-out number of the clock driver D is larger than the clock skew caused by the wiring capacitance.

Note that the aluminum [16A on the silicon oxide film 14 may be formed in a plate shape to cover the silicon oxide film 14 instead of being formed into a plurality of wiring shapes as shown in FIG.

As explained above, according to this embodiment, in a plurality of clock drivers connected to the same terminal, the maximum load capacity driven by the clock driver and the clock driver smaller than this load capacity or different from the above configuring a capacitive element Ca having a capacitance value difference from each load capacitance driven by the maximum load capacitance, and connecting each capacitive element Ca to each clock driver driving a load capacitance smaller than the maximum load capacitance. As a result, the difference in load capacitance between the respective chloracts 544D is almost eliminated, so clock skew can be eliminated and speeding up can be achieved.

[Example ■ of the present invention]

FIG. 7 shows one basic cell 3 in Example H of the present invention.
It is a top view of A.

Embodiment (2) of the present invention is such that in a standard cell type logic integrated circuit, a capacitive element Ca is provided in a selected basic cell 3, and this capacitive element Ca is used to reduce clock skew, and in a gate array, for example, all The basic cell 8A is provided with a capacitive element Ca.

This capacitive element Ca is connected to the clock signal line of each clock driver that drives a load capacitance not less than the maximum load capacitance among a plurality of clock drivers D connected to the same terminal.

The capacitive element Ca is the one shown in FIGS. 5 and 6, reduced in size and placed in the basic cell 3A. Therefore, for example, the N semiconductor region 12 formed in the same process as the emitter region 12 of the transistor 5, the thin silicon oxide film 14, and the first layer aluminum film 1 provided thereon.
It consists of 6.

As explained above, also according to this embodiment (2).

Similar to Embodiment I, in a plurality of clock drivers connected to the same terminal, the maximum load capacitance driven by the clock driver and the load capacitance smaller than that load capacitance and driven by a different clock driver than the above-described one are The difference in the load capacitance of the clock drivers is almost eliminated by configuring the difference in the capacitance element Ca and connecting each capacitor Ca to each clock driver that drives a load capacitance smaller than the maximum load capacitance. It is possible to eliminate clock skew and increase speed.

[Example ■ of the present invention]

FIG. 8 is a plan view schematically showing a part of the integrated circuit in Example 2 of the present invention, and FIG. It is an enlarged view.

Embodiment (2) of the present invention is intended to eliminate differences in load capacity due to differences in fan-out number or wiring length.

Aluminum wires 23A and 24A are provided with one end open, that is, not connected to the circuit, and their stray capacitance constitutes a capacitive element, and this is connected to a load smaller than the maximum load capacity of the multiple clock drivers connected to the same terminal. It is connected to the clock driver D that drives the capacitor to eliminate clock skew.

In FIG. 8, the input terminal IN is connected to the output terminal of a clock driver D one stage before the final stage, as well as a plurality of other clock drivers D not shown.

The plurality of clock drivers D connected to the same clock driver D in the preceding stage do not drive the maximum load capacity, but drive a smaller load capacity.

The capacitance smaller than the maximum load capacity is compensated for by the stray capacitance to the second layer aluminum wiring 23A and the third layer aluminum wiring 24. Here, the wiring 23A, 24
As shown in FIG. 9, the circle mark (0) at one end of A means that although the wiring extends above the basic cell 3A, it is not connected to the transistor 5 or the resistance element 6 therein.

Further, for each of the wirings 23A and 24A, after the wiring layout of the regular signal wiring, power supply wiring, etc. is completed, the load capacitance of each clock driver D is calculated, and then the shortage of the load capacitance is compensated for. It is laid out using the same design method as the normal signal wiring 23 and 24. Therefore, it is provided on the wiring channel 4 or on the insulating film 17 in a region where no wiring has been provided yet. Note that the wiring 23A does not always extend to the basic cell 3A like the normal signal wiring 23 and 24, but is connected to the wiring 24A at the connection point (・).
It is also possible to stop at

As explained above, the wirings 23A and 24A are provided.

This stray capacitance constitutes a capacitive element, and by connecting this to a clock driver D that drives a load capacitance smaller than the maximum load capacitance among multiple clock drivers connected to the same terminal, each clock driver Since the difference in the load capacitance of D can be eliminated, clock skew can be eliminated.

In addition, the wirings 23A and 24A are 1 normal signal wiring 23.2
Since the layout is performed using the same design method as 4, the arrangement can be easily performed.

[Embodiment of the invention■]

FIG. 10 is a plan view schematically showing a part of an integrated circuit in Embodiment 2 of the present invention.

In the embodiment (2), the wirings 23A and 24A, which were provided to eliminate the clock skew in the embodiment (2), are provided in the wiring channel 21 of the power supply circuit 22.

In FIG. 10, the input terminals IN and IN are connected to each other.

Although not shown, they are connected to the same terminal, ie, for example, the same preceding clock driver D. However, the load on the clock driver D is two flip-flop circuits F/F and one clock driver D2, and the load on the clock driver D is as follows.

There are four flip-flop circuits F/F and one clock driver D4. Along with this, the load capacity also differs, so
The second layer of aluminum wiring 2 is connected to the clock driver D1.
3A and the third layer aluminum wiring 24A,
This is to eliminate taro skew between clock driver D and clock driver D.

Wiring 24A is TI! It is provided in the source wiring channel 21.

This wiring 24A is the wiring 2 that connects between the power supply circuits 22.
After completing the layout design of 4, power wiring channel 2
The layout design is performed in the empty area of 1. The length of the wiring 24A is determined as appropriate, and where on the wiring channel 21 both ends thereof are terminated is arbitrary. Namely.

There is a high degree of freedom in wiring layout, making it easier to design. The wiring 23A is a wiring for connecting the wiring 24A to the clock driver Di, and is provided in an empty area of the wiring channel 4. That is, the wiring 23A is
The wiring channel 4 is not provided with a dedicated track. In addition, wiring 23A.

24A may be provided with a dedicated wiring channel (track) for arranging them on the wiring channel 4 or substrate l.

Similarly, in the clock drivers D2 and D4, in order to eliminate clock skew between them, the second layer aluminum wiring 23A and the third layer aluminum wiring 24A are connected to the clock driver D2.

As explained above, according to this embodiment, the
, 24A are provided, and their stray capacitance constitutes a capacitive element,
By connecting this to each clock driver D that drives a load capacitance smaller than the maximum load capacitance among multiple clock drivers connected to the same terminal,
Since the difference in load capacitance of each clock driver D can be eliminated, clock skew can be eliminated.

In addition, without specifying the position where the end of the wiring 24A is terminated,
Since the wiring channel 21 is terminated at an arbitrary point, there is a high degree of freedom in the wiring layout, and it is easy to design a stray capacitance as a capacitive element.

Above, the present invention has been explained in detail based on the examples.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, by providing a capacitive element on a predetermined clock signal line, there is no difference in load capacitance between clock drivers due to differences in wiring length or fan-out number, so clock skew can be eliminated and high-speed It is possible to measure the

[Brief explanation of drawings]

FIG. 1 is a plan view of a standard cell type semi-custom integrated circuit. FIG. 2 is a plan view showing an example of the layout of elements provided in one basic cell 3A. FIG. 3 is a cross-sectional view showing the cross-sectional structure of a bipolar transistor provided in the basic cell 3A, and FIG. 4 is a plan view schematically showing a part of the integrated circuit according to the first embodiment of the present invention. , FIG. 5 is a plan view of the capacitive element, and FIG. 6 is a sectional view taken along the line 1-1 in FIG. 5. FIG. 7 shows one basic cell 3 in Embodiment 3 of the present invention.
A. FIG. 8 is a plan view schematically showing a part of the integrated circuit in Embodiment (2) of the present invention. FIG. ), FIG. 10 is a plan view schematically showing a part of the integrated circuit in Example 2 of the present invention. In the figure, Pad...ponding pad, D...clock driver, F/F...flip-flop circuit, 1
... Substrate, 2... Buffer circuit, 3... Basic cell row, 3A... Basic cell, 4... Wiring channel, 5...
... Bipolar transistor, 6... Resistance element, 7.
...Field insulating film, 8...Channel stopper, 9
...Buried layer, 10...Collector region, 11...
Base region, 12... Emitter region, 13... Extraction region, 14... Silicon oxide film, 15... Opening, 16.23.24... Aluminum wiring, 17.1
8... Interlayer insulating film, 21... Power wiring channel, 2
2...Power supply circuit, 23A, 24A...Clock signal line. Agent Patent Attorney Katsuma Ogawa 2 Figure 1 Figure 2 Figure 3 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1. Basic cells having a plurality of semiconductor elements are repeatedly arranged to form a basic cell row, and semiconductor elements in the basic cell or in a plurality of adjacent cells are connected to each other. A semiconductor integrated circuit device comprising one circuit and connecting each of the first circuits to constitute a larger second circuit, the semiconductor integrated circuit device comprising a predetermined signal line extending from the first circuit. A semiconductor integrated circuit device characterized in that a capacitive element is provided in the semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a semi-custom integrated circuit such as a gate array or a standard cell type. 3. The semiconductor integrated circuit device according to claim 1, wherein the predetermined signal line provided with the capacitive element is a clock signal line extending from a clock driver. 4. In the gate array, the capacitive element is configured using a semiconductor element in an unused basic cell, and in the standard cell method, the capacitive element is configured in almost the entire area of the selected basic cell area. A semiconductor integrated circuit device according to claim 1, characterized in that: 5. The capacitive element is characterized in that a wiring that does not connect circuits is provided on the substrate, this is connected to the clock signal line, and the capacitive element is constituted by the stray capacitance of the wiring. The semiconductor integrated circuit device described in . 6. Claim 1, wherein the wiring as the capacitive element is provided in a dedicated wiring channel.
5. The semiconductor integrated circuit device according to item 5. 7. The semiconductor integrated circuit device according to claim 1 or 5, wherein the wiring as the capacitive element is provided in a wiring channel in which a signal wiring is extended. 8. The semiconductor integrated circuit device according to claim 1, wherein the capacitive element is provided together with other semiconductor elements within a cell region.