JPS59139646A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase capacitance while preventing an enlargement of the area of a chip by arranging bondig pads for an input and an output near each of input/output buffer cell while disposing them at pinched corner sections so that one parts are extended. CONSTITUTION:With a gate array, base body cells 6 are arranged cross-wise in the central section of the main surface of a semiconductor base body 4, and CMOS logic arrays 5 are formed. Cells 7 for input/output buffers using low- power Schottky TTLs are disposed at four corners of a chip in a peripheral section. One input/output buffer cell 7 is functionally separated completely into an input buffer section and an output buffer section, and a large number of the cells forming pairs are disposed to the peripheral section of the chip, and arranged uniformly. One bonding pad 10 is disposed positively outside and near the input/output buffer cell in response to several input buffer and output buffer. The cells are displaced so that at least one parts of one input/output buffer cells are extended at pinched corner sections 8, and the size of the chip can be reduced only by displaced sections.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device (hereinafter referred to as IO), and particularly to a semi-customized device.

[Background technology]

Semi-force Nutamue O, which is usually called a gate array, is made by forming a large number of semiconductor diffusion regions forming basic cells (blocks) in vertical and horizontal columns (plays) in advance in a semiconductor substrate, and connecting these diffusion regions with wiring. Connect in part,
A method is adopted in which the desired logic circuit is formed without connecting in other parts.

Therefore, for the same product series of gate arrays, the diffusion process is common, and the desired logic can be linked just by processing the wiring layer, so the number of photomasks can be reduced, and the process can be shortened by 1.
It is highly effective as a semiconductor logic circuit device with low cost and high quality.

By the way, in this Kate array, the basic cells are composed of ○MOE+ (complementary insulated gate field effect transistor), nMo5 (n-channel full type insulated gate field effect transistor), and 2L (concentrated private injection). Various devices have been proposed in the past, such as TTL (transistor logic), ECL (emitter coupled logic), and ECL (emitter coupled logic). The inventor of this application adopted a low power consumption 0M0B as a device constituting the logic circuit', and used a high-speed bipolar transistor as an interface circuit (input/output buffer) that enables connection with an external TTL circuit, etc. 7'jBi-
I thought about CMOS gate array technology. According to this technology, it is possible to interface with an external TTL circuit, the signal processing speed of the input/output buffer is fast, and the logic circuit can be configured with only a small amount of power, using bipolar transistors and C
It becomes possible to provide a process that takes advantage of each feature of MOB. However, the number of logic gates is 16, for example.
Large capacity so that it can be taken in one size.

The inventor of the present application has found that it is extremely difficult to secure a sufficient number of input/output buffers within the specified chip size in the case of became. This is B1-0M0B
In order to maintain the withstand voltage of the source and drain of 0MO8 among the OMOELs that constitute the logic circuit in the gate array, a deep p-type well of 6 μm or more is required, and accordingly, the depth of the epitaxial layer formed on the semiconductor substrate is 7 μm or more.
Since the input/output buffer section is composed of k-th bipolar transistors with a pap-8μ-magnification, the area occupied by the isolation circuit cannot be made small, and the cell size of the input/output buffer is 360 μm x 600 μm, which is the size of the CM<) day array. This is because p becomes larger than the cell (48 μm×152.un).

Furthermore, in order to effectively combine both large-capacity logic gates and their corresponding input/output buffers within one chip, it is necessary to make effective use of spacing, which is difficult to achieve using conventional layout methods. Revealed by the inventor.

[Purpose of the invention]

The present invention has been made to improve the above-mentioned drawbacks, and its purpose is to improve the interface circuit (
In a semiconductor integrated circuit device having an input/output buffer (input/output buffer) and a logic circuit on the same chip, the input/output buffer and the logic gate can function effectively while preventing an increase in chip area, thereby increasing the capacity. There is K.

[Summary of the invention]

A feature of the present invention for achieving the above object is that for one input/output buffer cell, bonding pads for input and output are arranged near each output buffer cell, and pads for input and output are arranged near each output buffer cell. At least a portion of one input/output buffer cell is provided with tIE (overlap) in a corner sandwiched between adjacent input/output buffer cells.
If the cells are arranged so that they are shifted, there will be K.

〔Example〕

Hereinafter, the present invention will be described with reference to all the drawings of an embodiment of the Kudo array according to the present invention.

FIG. 1 shows the configuration of a B1-0M0S gate array according to the present invention, the flow of electrical signals, and the voltage levels at each location. Note that since a TTL circuit is generally used as an external circuit connected to the gate array, an interfunisque concept with respect to the TTL circuit will be used here. The input buffer of the gate array in this embodiment is an inverter made of bipolar transistors, the logic circuit is made of 0MO8, and the output buffer is a high-speed pipe that logically processes a large number of output signals of the logic circuit and transmits it to its output. It consists of a Borapvushupuru output circuit.

Next, the flow of electrical signals will be explained.

In the figure 'iHI Lth l iL = vOH-v
Otll1voL represents input high level, input logic threshold, input low level, output high level, output logic threshold, and output low level, respectively. Note that the subscript A-
F corresponds to the symbol in the diagram showing the flow of electrical signals. An input signal A (vl,,=2.Ov) is input from the external TTL to the input terminals IN1 to ND of the input buffer 1.

v = Q, 87. v = 1,4v) is input and LLA 1thA and CMOS
Output signal B converted to level (vOTlB"'4-'
vl vOLB=O-6vl vOthB”2.5V
) is output and then input as the input signal 0 of the 0M08CI switch. The output signal after the logic processing is inputted as the input signal E of the output buffer, converted back to the TTLt pressure level, and output as the signal F. Here signal 0.
The voltage levels of D and El are equal to the level of signal B, and the voltage level of signal F is equal to the level of signal A. In this way, the gate array of this implementation project has an input buffer of 1,0M0
S logic circuit 2. An output buffer 3 is provided within the same chip, and an interface with an external TTL is possible.

FIG. 2 is a plan layout diagram showing the cell arrangement of the gate array described above. As shown in the figure, this gate array is located at the center of the main surface of the semiconductor substrate (chip) 4.
The base cells 6 made up of the
Cells (blocks) 7 of input/output buffers using the STT II) are arranged at the four corners of the chip so as to surround the OMOS logic array. The rectangular area (approximately square in the figure) indicated by the dashed line in the figure is the 0MO8 logic circuit area in which the number of 0M080 six arrays is arranged. Here, each input/output buffer self is functionally and completely separated into an input buffer section and an output buffer section. If a large number of cells with such input and output buffers are arranged around the chip, the input and output buffers will be arranged evenly around the chip.
Compared to the case where the input and output buffers are arranged separately and apart from each other, it is very convenient in terms of terminal and wiring layout, and has the effect that the degree of freedom in layout is improved. Corresponding to each input buffer and output buffer, one bonding pad (total of two for one input/output buffer cell) is always arranged outside and near the input/output buffer cell. By adopting such a layout, the input buffer section and output buffer section of all input/output cover cells are functionally independent, and
Since they can operate simultaneously, the efficiency of using input and output buffers is greatly improved. That is, as shown in FIG. 3, the input buffer section of the input/output buffer self (1n1,
tn2, in3) and the output buffer section (ou in the figure)
Ti, ouT2, ouT3) v all, corresponding bonding pads P1Ω1~3 + PouT
Since the input/output buffers and the aluminum (hL) wiring Ih12 are arranged, each buffer can be used independently and simultaneously. Here, 11 is a gold (Au) wire, 13 is an output terminal of the input buffer, and 14 is an input terminal of the output buffer.It goes without saying that the usage as shown in Figure 4 is possible if necessary. It's also out. In this case, the input buffer tn
i and the output buffer 0uT1 are connected to the input bonding pad P1n1 by aluminum wiring, and as shown by the arrow in the figure, the fC@ signal that is output from the output buffer outTl is returned to the input buffer 101 again. In addition, in the other two input/output buffer cells in the figure, only the output buffer outT2> and the input buffer tna are used. Providing bonding pads corresponding to each input/output buffer in this way allows full utilization of the input/output buffer function and improves the degree of design freedom.

Furthermore, if a large number of bonding pads are arranged around the chip, heat dissipation from these bonding pads can be expected, and in the B1-0M0S gate array according to the present invention,
The input/output capacitor, which consumes a large amount of power and consists of transistors, is placed around the chip to quickly dissipate heat from the periphery of the chip, which in turn has the effect of preventing characteristic deterioration of the gate array due to heat. .

This effect will be explained in more detail.

According to the inventor, the number of gates and power consumption of the gate array according to the present invention are as follows.

1 As shown in Table 1, even a simple calculation shows that about 85% of the power consumption of the entire chip is consumed by input/output. This means that the most amount of heat is generated from here. By arranging the heat generated by such a pibora transistor on multiple peripheries and arranging a large number of bonding pads on the outside thereof, the heat generated by the input/output buffer itself and the bonding pad 10 wire can be 1. Through t6, it becomes possible to dissipate heat in a movable manner through multiple leads Lo to Lack placed around the chip.In the figure, the input, output cover, and sofa are each marked with a triangle. A side line is applied to the inserted cover. Fig. 13 shows the state in which the lead frame and chip shown in Fig. 12 are mounted by the resin molding method. Also, in the gate and array of this embodiment, the second paulownia As shown in the figure, the cells are arranged so that at least a part of one input/output buffer cell extends (overlaps) into the corner 8 sandwiched between adjacent input/output buffer cells on the periphery of the chip. In other words, by shifting the cells to the corner 8 by 9a, 9b, 9c, and 94 indicated by the body lines in the figure, the chip size is reduced by 1) eLB -44:1i11+ey. When such an arrangement is short, the distance from the end of the input/output buffer cell to the end trench is dl, which can be reduced to d2.FIG.

13th! As shown in FIG. 2, in a large-capacity device having leads as large as 6° and 44 inches, an increase in the chip area is difficult, but according to the present invention, the chip size can be reduced, which is highly effective. FIG. 5 shows an enlarged plan layout diagram of a specific part of the gate array using the above-described layout method. Components common to those in the previous drawings are designated by the same reference numerals.

In the embodiment shown in the figure, the output buffer has not only a voltage level conversion function but also a logic function, thereby increasing the capacity of the semiconductor logic circuit device. In the figure, 15 is a ground wiring using Atf in the second layer, and 16 is yc V 6 using ALf in the second layer.

Wiring 17 is the internal pin of the CMOS array, 18 is the CM
O87vit DVc0 (ml source) wiring, 19 is the ground wiring for the input buffer, 20 is the ground wiring for the output cover 1F', and 21 is used for both the input and output buffers. C wiring,
22 is connected to the ground wiring of the 0M0EI array 2
V using layered Al. . These are the wiring, the terminals for the 23c input/output wire, and the contact poles for opening. Furthermore, the first layer A
All solid lines using t, wiring va'J using second layer At
It is represented by a k2 dotted chain line. Here, the first layer At wiring is connected to the underlying semiconductor element area through the entire insulating # (not shown) contact hole formed on the entire surface of the chip, and the second layer At wiring is interlayer insulated to the first layer At wiring. Connections are made through through holes in the membrane (not shown). Note that an inorganic film such as kesto, psG, etc. is used as the interlayer insulating film. As shown in the figure, the ground wiring 17 of the 0M0S array runs over the 2
It is connected to the input or output buffer ground wiring wI19, 20 which is in contact with the ground wiring 15 made of the layer At through a through hole (not shown) to form a common ground connection. With such a configuration, the number of ground wirings using the second layer A/, can be reduced by one. On the other hand, vo of 0MO8 array. Wiring 1
7 is in contact with the VC8 wiring 22 of the second layer At through a null-hole (not shown), and is connected to the V of the input/output buffer cell 7. . The wiring is 2/e A4 and V. . There is a wiring 16 and a contact wire 2. Although not shown, there is a ground layer on the chip using a second layer of At.
and・Vo.

Several more wires are placed horizontally and vertically. A total of 8 contact holes 23 for terminals and extraction are formed in each input/output buffer cell (one hole for taking out the input buffer output terminal and 7 holes for taking out the input terminal of the output buffer). It is possible to take out a maximum of seven input terminals for the output buffer. 11.14 in the figure is
These are the output terminal of the input buffer and the input terminal of the output buffer, which are taken out via the above-mentioned contact hole and are made up of the first layer At. As can be seen from the figure, these terminals are arranged to intersect with the output buffer in the input/output buffer cell. Even if this friend input buffer cell is placed at the corner 8 of the chip, shifted by the amount indicated by the fp4 line in the figure, crowding of terminals and wiring connected to them at the corner, sheets, etc. can be prevented. This makes it possible to create layout '2' in which the cells are arranged in a staggered manner as described above. In addition, the wiring of the input/output terminals of the input/output buffer is arranged at equal intervals (1 = 24 μm) with an interval d.A design automation (DA) system is used to design the gate array, and the logic From determining the optimal placement of cells on the chip based on connection information,
The DA system is used for everything up to the determination of wiring patterns. Therefore, as mentioned above, the regular spacing between each terminal means that each terminal and logic circuit can be configured.
This is very convenient when automatically creating a wiring pattern for connecting all the N, -f' MOS cells using a DA system. In addition, in this gate array, the output areas of each terminal are gathered on the output buffer side, so there is no need to take out the input/output terminals from the side surface facing the 0M0B play area of the input/output sofa. , the 0 part surrounded by the dotted circle) is the ground wiring of the input buffer M19
' can be extended to '. As mentioned above, 0M0S
Array ground lines #1 and 7 and input/output buffer ground line 1R19 are connected at one place and are common, so the fact that the input buffer ground line 1N19 extends to the 0 section means that the ground line of CMOS array and It is better to use a LayAct upper stand as it is easier to connect with the wiring. In addition, the extended part of the ground wiring acts as a shield between the input buffer that requires power and the wiring area 24, and has the effect of preventing mutual signal interference from occurring.
have FIG. 6 is a partial plan layout diagram of such a gate array. Components that are the same as those in the previous drawings are represented using the same symbols. In the same figure, around the chip,
- Using second layer Al. . The wirings 16 and 26 and the ground wirings 15 and 25 are not arranged properly.

Note that in order to reduce the chip surface 'S by shifting the input/output buffer cells to the corners of the chip periphery,
It is also possible to use a rayaratora as shown in Figure 7. FIGS. 8 and 9 show examples of how to take out the input/output terminals from the input/output buffer cells at the corners when the layout controller as shown in FIG. 7 is employed. FIG. 9 is an example in which the adjacent part (H area) of the adjacent input/output cover lnor cell is opened and the terminal metal is taken out from there. In Figures 7 to 9, the same components as in the previous drawings are designated using the same symbols and sounds. It should be noted that the extended portion of the input/output buffer cell may be formed so as to take out the terminal and, if possible, completely fill the corner 8'.

Next, the enlarged partial plane layout of the 0M08 array is shown as the 10th
As shown in the figure. In the figure, 27 is a p-type cell region, 28 is a polysilicon gate, 29 is a polysilicon layer, 30.31 is the drain (D) of a D-channel MOE+ (in this embodiment) range nut, and 32U is also an n-channel transistor. MO8) is the source (S) of the transistor. 33 is p channel MO8)
The source (8), 34.35 of the transistor is also the drain (D) of the p-channel transistor. In addition, from 30
Whether to use it as a source or a drain can be freely selected depending on the circuit and layout. 36,
37.38 is MO8) First layer A connecting between transistors
1 wiring and 39 to 50 contact holes. (Also, in the figure, the chip surface other than the −fc area surrounded by a dotted line is covered with a thick oxide film (Looos oxide film), although not shown.) [1O
Using 1 and U, a circuit as shown in FIG. 11 is constructed and an example sentence is shown. It should be noted that since the cells (2), (2), and (2) each have the same configuration, common parts are indicated by the same designation symbol. Here, the manufacturing process will be briefly explained. After forming a p-type well 27 on the main surface of the chip using normal lithography and diffusion techniques, the chip surface other than the area surrounded by the dashed line in the figure is selectively liquefied to form a thick oxide film (LOOO).
8 oxide film) is formed. Next, polysilicon is deposited on the entire surface of the tube, and unnecessary parts are removed by machining and sowing to form a wrinkled silicon groove.28. and a polysilicon layer 29 is formed. This polysilicon layer 29 is
It is used as a resistor or wiring as necessary in the circuit structure. Next, the above-mentioned kt/'1 intoxication film and polysilicon film) 28
P-type undesirables (such as boron) and n
The source (
S)32. Drain (D) ao, at, source (S) of transistor 33. drain(
D) form 34.35. Thereafter, wirings 17, 18, 36, 37, and 38 are formed by depositing Al on the entire surface of the chip and removing the cine portion. Note that the wiring 18 is the second layer Atvoc wiring flii 116
The wiring 17 is connected to the ground wiring of the crowd buffer as described above. In this way the first
An 0M0S array constituting the circuit shown in FIG. 1 is formed.

[Effect of non-invention]

The present invention described in the above embodiments has the following effects.

■ Most of the chip is composed of 'ioMO8', which can reduce the total power consumption. Since it is composed of bipolar transistors with high input/output speeds of kA, it is possible to improve the driving ability.

■ OMOS array is placed inside the chip (center),
By arranging the input/output buffer at the periphery of the chip so as to surround the 0M0S array, it is possible to effectively dissipate all the heat generated from the input/output buffer, which consumes a large amount of power, to the periphery of the chip.

■ Since one bonding pad is always placed outside and near the output buffer cell for each input and output cover, all input and output buffers are functionally independent. , multiple output buffers can be operated at the same time, and the efficiency and layout of the output buffers are greatly improved. Furthermore, if a large number of bonding pads are arranged around the chip, heat dissipation can be expected from these pads, and the above-mentioned power buffers, which require power, can be placed around the chip to effectively dissipate heat. Together with the young buds, this prevents the characteristics of the gate array from deteriorating due to heat. Also, the fact that the input/output buffer and the bonding pad are placed close to each other means that V. There is an advantage of being able to reduce 1.

■ When arranging the input/output buffer cells, place cells so that at least a portion of one input/output buffer cell is 1# in the corner between the input/output buffer cells that match *a on the periphery of the chip. By staggering the arrangement, the area used for cine can be reduced and the chip size can be reduced.

As above, the invention made by the present inventor has been carried out and specifically explained based on 11, but the present invention is not limited to the above embodiments, and can be modified at will without departing from the gist of the invention. Needless to say.

[Application field]

The above explanation will mainly focus on the B1-CMOS game field, which is the field of application in which the invention was made by the present inventor.
) 7-lay technology, fc is not limited to this, but for example, a layout technology in which cells are shifted and placed at the corner of a chip is applied to the entire 'Ico
The present invention can also be applied to a logic device 0 composed of only MO8 or bipolar transistors. The present invention can be applied at least to an IC that requires a large number of cells to be arranged on the entire surface of the chip.

[Brief explanation of drawings]

1A is a diagram for explaining the function of the gate array according to the present invention. FIG. 2 is a plan layout diagram showing the cell arrangement of the gate array. FIG. 3 is a partial plan view for explaining the connection state between the input/output buffer and the bonding pad, and FIG.
5 and 6 are partial enlarged plan views of the chip including wiring patterns, respectively. FIG. 7 is a plan view showing a cell arrangement according to another embodiment of the present invention, FIGS. 8 and 9 are plan views each illustrating a terminal extraction method, and FIG. 10 is a portion of an 0M0S array. The enlarged layout diagram, FIG. 11, is a diagram showing a circuit configuration corresponding to FIG. 10. Figure 12 is a plan view of the chip and lead frame,
FIG. 3 is a milling view showing the mounting state of the IO. DESCRIPTION OF SYMBOLS 1... Input buffer, 2... 0MO8 Russian array, 3... Output buffer, 4... Chip, 5...
0M0S array, 6...0M0S cell, 7...I/O buffer cell, 8...Corner, 9a, 9b,
9c, 9d=displacement area of input/output buffer cell toward corner 8, 10...bonding pad, 11...bonding wire, 12...At wiring, 13...
- Output terminal of input buffer, 14... Input terminal of output buffer, G5... Ground wiring using second layer At, 16... f5V using second layer At. . Wiring, 17.
・・CMOS play ground wiring, 18...0MO
8 array V. . Wiring, 19... Input buffer ground wiring, 20... Output buffer ground wiring, 2
1...V that serves as input and output buffer. . Wiring, 22・
...Second layer At was utilized ■. . Wiring, 23... Contact hole, 24... Input/output buffer cell and 0M0E
Wiring area sandwiched between I arrays, 25... Ground wiring, 26... VAC gauze, 27... P-type well, 2
8... Polysilicon gate, 29... Polysilicon wiring, 30.31... Drain (D) of n-channel MOS transistor, 32... Source (S) of Ω channel MOB transistor, 33・-・p channel MOE+
) Source of transistor (S), 34.35...n channel MO8) Drain of transistor (D), 36.37
．． 38... At wiring, 39-50... Contact hole, 51... Lead frame, 52... Engineering C1t
I~t6...Au wire Lo~Ll14...Lead. Figure 3 Figure 4 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] 1. A rectangular logic circuit section is arranged at the center of one principal surface of a semiconductor substrate, and a first section having a voltage level conversion function is arranged along at least adjacent sides of the logic circuit section. A second buffer cell section is arranged, and the first. The semiconductor integrated circuit device 2 is characterized in that the ends of the second buffer cell portions intersect with each other, the logic circuit portion is constituted by a plurality of complementary insulated gate field effect transistors, and the first , the semiconductor integrated circuit device according to claim 1, wherein the second breadth cell section is constituted by a plurality of bipolar transistors.