JP2737620B2 - Semiconductor integrated circuit wiring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a layout of a semiconductor integrated circuit which operates in synchronization with a clock. The present invention relates to a semiconductor integrated circuit capable of reducing clock skew and a wiring method thereof.

The present invention relates to a technique effective for skew prevention when a clock signal is supplied from a single clock supply source to a plurality of logic circuits arranged on a substrate, and relates to a computer or a logic LSI constituting the computer. It concerns the technology used.

[0003]

2. Description of the Related Art Conventionally, the layout of a semiconductor integrated circuit is as follows.
As shown in FIG. 4, wirings having the same potential are grouped, wiring paths 1, 2, and 3 are determined for each group, wiring prohibited areas 4 and 5 are provided, and wiring between the groups is crosstalk. In order to avoid this, there is a method of separating at least a certain interval (Japanese Patent Application No. 60-275435). In this method, even if the wiring length is the same, the wiring capacitance greatly differs depending on the presence or absence of the adjacent wiring.
For example, when the wiring width and interval are 1 μm, the wiring capacity per unit length when there is no adjacent wiring and when there is an adjacent wiring is about 3
In contrast to the doubling, a skew difference of about 1 ns occurs due to a delay of only the wiring resistance and the wiring capacitance per wiring length of 10 mm. Therefore, especially for clock signals, it is increasingly necessary in the future to make the adjacent wiring section another wiring prohibited area.

On the other hand, there is a method shown in FIGS. 5 and 6 for reducing clock skew. In the method shown in FIG. 5, a node is set at an intermediate point between pairs of adjacent flip-flops A and B, C and D, E and F, and G and H, and a higher-order node is arranged in the middle of a pair of adjacent nodes. I do. This procedure is repeated to determine a wiring route. This reduces the skew from the clock driver to each flip-flop (28th DACproc. 1991: P322-3).
27). In the method shown in FIG. 6, additional wiring is performed so that the load becomes equal after completion of the wiring (28th DAC).
proc. 1991: pages 253-258).

As a method for determining a wiring route, Japanese Patent Laid-Open No.
In the case where signal nets of different voltage levels are mixed, the wiring is performed for each signal net of the same voltage level, and the wiring of the same kind of signal net is completed. Before starting the wiring of the heterogeneous signal net, determine the wiring prohibited area by the existing wiring so that the wiring of the subsequent heterogeneous signal net does not adjoin the existing wiring within a certain interval, and avoid wiring to this area. This enables wiring of nets having different voltage levels in the same layer, thereby reducing the number of layers of the wiring board.

Japanese Patent Application Laid-Open No. 63-13517 and Japanese Patent Application Laid-Open No.
There is one disclosed in Japanese Patent Application Publication No. 101412. In the former, a gate having a large fan-out is dedicated to a clock driver, and a clock wiring is fixed in advance in a transistor diffusion layer. In the latter, a clock skew adjusting circuit including a variable delay means for clock, a phase comparing means, and a frequency dividing means is arranged at a plurality of positions, and a wiring distance between one clock generating source and each clock skew adjusting circuit is made substantially equal. Further, a common frequency information and a phase information signal are supplied from one clock generation source to each clock skew adjustment circuit, and the adjusted clock is supplied to a flip-flop or the like, and a clock skew is supplied from a clock input terminal of a supply destination circuit. The clock is fed back to the phase comparison means of the queue adjustment circuit, the phase difference with the phase information is detected, and the variable delay means is controlled so that the phase difference becomes zero.

[0007]

In such a conventional layout method, the wiring length cannot be adjusted.
In the example shown in (1), the crosstalk is reduced by providing the wiring prohibited area, but the equal length wiring is not considered. On the other hand, in the example shown in FIG. 5, the wiring path is specified so that the wiring is of the same length in consideration of the reduction of the clock skew. Further, in the example shown in FIG. 6, there is a problem that the clock skew cannot be completely suppressed to zero because the skew differs due to the delay due to the wiring resistance even when the load becomes equal.

[0008] The present invention was done based on such a background, and an object thereof is to provide a wiring method of a semiconductor integrated circuits which can be clock skew to zero.

[0009]

This onset bright [Means for solving problems] In the clock signal wiring method for a semiconductor integrated circuit including a logic circuit which operates in synchronization with a clock signal, two adjacent on the basis of the position information of the logic circuit the intermediate position of the logical circuits and nodes, Bruno logic circuit between further adjacent to this node
To a node at the intermediate position on the wiring route.
The operation to make is repeated hierarchically, and finally one higher
Wiring for a clock signal is performed until integration into a node, and a wiring prohibited area is provided in an adjacent portion of the clock signal wiring path, and the wiring length from the highest node to each logic circuit is equal to this wiring prohibited area. It is characterized by performing additional wiring.

[0010]

After arranging the cells on the substrate, position information of the cells connected to the clock signal is extracted to form pairs of adjacent cells, and nodes are set at the same position from each pair of adjacent cells. Further, an adjacent pair of the nodes is formed, and a higher-order node is formed at the same position from the pair until the highest-order node becomes one, and wiring of the clock signal is set. After the clock signal wiring, a wiring prohibited area is provided in an adjacent part thereof, and the wiring prohibited area is used to equalize the wiring lengths from the highest node to each cell connected to the clock signal.

As a result, the skew of the clock signal can be made substantially zero.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention.

The embodiment of the present invention includes logic circuits A and C, B and D, E and G, F and H operating in synchronization with a clock signal, and at least two logic circuit columns to which the clock signal is connected are provided. The intermediate positions of the clock signal wiring paths arranged and connected to this logic circuit are nodes I, J, K, and L. The nodes I, J, K, and L are connected to each other to The uppermost node is arranged at one position until the clock signal wiring path is adjacent to one, and the adjacent portion of the clock signal wiring path is a wiring prohibited area. An additional wiring portion is provided for equalizing the wiring length of the signal wiring.

The wiring has a node at an intermediate point with an adjacent logic circuit based on position information of the logic circuit operating in synchronization with the clock signal. The wiring for the clock signal is performed until the upper node becomes one at the position, and a wiring prohibited area is provided in an adjacent portion of the clock signal wiring path, and the wiring prohibited area is provided from the highest node to each logic circuit. Additional wiring is performed so that the wiring lengths are equal.

Here, a wiring method of a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG.
Is a flowchart showing a flow of a wiring method in the embodiment of the present invention,
FIG. 3 is a diagram for explaining a node arrangement in the embodiment of the present invention.

First, the cells are arranged and the positions of the flip-flops A, B, C, D, E, F, G, and H are extracted. Next, as shown in FIG. 3, pairs of adjacent flip-flops A, B, C, D, E, F, G, and H are formed, and nodes I, J, K, and L at the intermediate points are determined. At this time, the nodes are determined so that the wiring lengths connecting the pairs and the nodes are equal to each other. Next, pairs IJ and KL between adjacent nodes are created, and upper nodes M and N are determined at the intermediate points. At this time, the wiring length I− connecting the lower node and the upper node
The upper nodes M and N are determined so that M, MJ, KN, and NL are equal to each other. Repeat this step,
The route of the clock wiring is determined and wiring is performed. At this time, the wiring part adjacent to the clock wiring is a wiring prohibited area. After completion of the wiring, since the wiring length is not uniform, the node O shown in FIG.
, The skew is set to 0 by using the adjacent wiring portion S so that the wiring lengths are all equal, as shown at the node N.

[0017]

As described above, according to the present invention, the route of the clock wiring is determined in advance, the wiring adjacent to the clock wiring is prohibited, and the clock wiring is made equal length using the wiring prohibited area. By doing so, there is an effect that the clock skew can be suppressed to almost zero.

Further, since the clock signal wiring length can be made equal by using the wiring prohibited area provided for preventing the crosstalk, there is an effect that the integrated circuit area can be effectively used.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing a flow of a manufacturing method according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating a node arrangement in the embodiment of the present invention.

FIG. 4 is a diagram illustrating setting of a wiring and a wiring prohibited area in a conventional example.

FIG. 5 is a diagram illustrating node setting in a conventional example.

FIG. 6 is a diagram showing a semiconductor integrated circuit provided with additional wiring in a conventional example.

[Explanation of symbols]

 A to H flip-flop I to O node S Adjacent wiring part (additional wiring) 1-3 Wiring 4, 5 Wiring prohibited area

Claims (1)

(57) [Claims] 1. A clock signal wiring method for a semiconductor integrated circuit including a logic circuit that operates in synchronization with a clock signal, the middle two logical <br/> circuits adjacent on the basis of the position information of the logic circuit The position is a node and it is further adjacent to this node
Logic nodes to be connected to each other
To create a node at the middle position of
The wiring for the clock signal is performed until it is finally integrated into one upper node, and a wiring prohibited area is provided in an adjacent portion of the clock signal wiring path. A wiring method for a semiconductor integrated circuit, wherein additional wiring is performed so that the wiring lengths up to the same are equal.