JPH03101412A - Logic integrated circuit - Google Patents

Abstract

PURPOSE:To reduce clock skew in a clock synchronization system and to quicken the system by making the wired distance between one clock generating source and each clock skew adjustment circuit nearly equal to each other. CONSTITUTION:A clock generating circuit 1 is provided in the middle of an LSI chip A. Moreover, 4 clock skew adjustment circuits 2 are provided with nearly equal distance from the clock generating circuit 1 and a reference clock MCK as frequency information and a comparison clock REF as phase informa tion resulting from frequency-dividing the reference clock MCK by 1/16 are fed respectively from the clock generating circuit 1 to each clock skew adjust ment circuit 2. Thus, clock skew is reduced in the system in which the inside of the LSI is operated synchronously with the clock and the system speed is quickened.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock adjustment technique, which is particularly effective when applied to countermeasures against skew when clocks are supplied from one clock supply source to a plurality of locations. The present invention relates to a technique that is effective when used in logic LSIs that constitute a .

[Conventional technology]

In systems such as computers, speeding up is achieved by supplying the same clock from one clock generation source to the many L8IKs that make up the system, and latching data in synchronization with that reference clock. ing.

[Problem to be solved by the invention]

However, the clock supply method in the conventional system is a so-called trickle-down method, and the distances from one clock generation source to each logic LSI receiving clock supply are different, so that clock skew occurs. Therefore, in order to prevent erroneous data from being latched due to this skew, conventional designs have been made to provide a considerable margin for latch timing, etc.

Note that regarding the provision of a plurality of phase adjustment means that receive clock supply from a clock generation source, see Japanese Patent Publication No. 63-231516 (corresponding U).

B, 5eria 1 ship 152,916).

Further, a technique for reducing clock-to-clock skiing is described in 1'-NEC Technical Report 3, pp. 85-90, published by NEC, August 1983.

If a signal transmission delay difference occurs due to differences in the distance from the clock generation source to each circuit receiving the clock supply, it becomes necessary to consider four margins based on the delay difference when designing the latch timing, etc. .

As a result, it became clear that the operating speed of the system was slowed down by the amount of timing margin.

SUMMARY OF THE INVENTION An object of the present invention is to reduce clock skiing in a clock synchronous type system, thereby increasing the speed of the system.

The above and other objects and novel features of this invention
K will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A summary of typical inventions disclosed in this application is as follows.

In other words, clock skew adjustment circuits each consisting of a variable clock delay means, a phase comparison means, and a frequency division stage are arranged at multiple locations in the system, and wiring between one clock generation source and each clock skew adjustment circuit is arranged. Make the distances approximately equal. Furthermore, common frequency information and phase information signals are supplied from one clock generation source to each clock key adjustment circuit, and the adjusted clock is supplied to a 7-lip flop, etc., and the clock input terminal of the supplied circuit is supplied with a common frequency information and phase information signal. The clock is fed back to the phase comparison means of the skinny adjustment circuit, the phase difference with the phase information signal is detected, and the variable delay means is controlled so that the phase difference becomes zero.

[For production]

According to the above-described means, it is possible to prevent a difference in signal transmission delay from occurring between one clock generation source and each clock skew adjustment circuit. Furthermore, each clock key adjustment circuit forms a clock whose phase matches that of the reference clock based on the phase information from the clock generation source and supplies it to each part. The clock deviation can be reduced compared to a system in which a clock is supplied to the clock.

〔Example〕

FIG. 1 shows an embodiment in which the present invention is applied to an LSI internal system.

That is, each circuit block surrounded by a solid line A in the figure is formed on a single conductive chip such as a single crystal silicon substrate.

In this embodiment, although not particularly limited, a clock generation circuit 1 is provided at the center of the LSI chip A.

Also, at approximately the same distance from this clock generation circuit 1,
Four clock skew adjustment circuits 2 are provided, and the clock generation circuit 1 sends a reference clock MCK as frequency information to each clock skinny adjustment circuit 2.
Comparison clock RE as phase information divided by IK by 6
F and are supplied respectively. Then, from each clock skew adjustment circuit 2, a slave clock SCK, which is formed based on the reference clock MCKK, is sent to the nearby flip-flop 3 that matches the operation timing.
is configured to supply. Further, a signal line 4 is formed so as to feed back the supplied clock from the clock input terminal of the flip 70 to the clock skew adjustment circuit 2 which is the supply source, from the clock input terminal of the flip 70 to which the clock SCK is supplied.

FIG. 2 shows a variable delay means 21 which takes the semi-clockwise MCK of the clock key adjustment circuit 2 as an input signal and can delay it by an arbitrary amount of time within one clock period, for example;
A frequency division stage 22 divides the reference clock MCK delayed by the variable delay means 21, and the position of the comparison clock REF as phase information from the clock generation circuit 1 and the feedback signal FB from the flip-flop 3 to which the clock is supplied. It consists of a phase comparison circuit 23 that detects a phase difference. The phase comparison circuit 23Fi supplies a signal C corresponding to the phase difference between the comparison clocks R and EF and the feedback signal FB to the variable delay means 21. For example, as shown in FIG. 3, the variable delay means 21 includes a plurality of delay means DLY1. DLY2. ...DLYn and the selector SEL that selects one of them and passes the reference clock MCK, and it becomes zero in response to the signal Cvc indicating the phase difference from the phase comparator circuit 23. Determine the delay means through which the reference clock MCK passes.

The signal FB fed back to the phase comparison circuit 23 is the slave clock SCK supplied to the clock input terminal of the seven lip-flops to which the clock is supplied. Therefore, if the clock skinny adjustment circuit 2 and the 7-lip flop 3 are close to each other, there will be almost no delay in the feedback clock, so the stove clock SCK output from the clock skinny adjustment circuit 2 will be as shown by the broken line in FIG. Even if a phase difference occurs with the comparison clock REF, the phase difference is immediately corrected to zero. Moreover, since common phase information is given from the clock generation circuit 1 to all the clock key adjustment circuits 2 in the LSI, even if the skinny adjustment circuits 2 receiving the clock supply are different, each flip-flop 3Fi will be operated simultaneously by clocks of the same phase.

In the above embodiment, a dummy signal line 5 of the same length as the clock supply signal line 5 from the path 2 to the 7 flip-flop 3 which feeds back the clock to the clock input terminal of the clock key adjustment circuit 2 and the flip-flop 3 is used. A feedback signal line 4 may be provided to provide feedback. As a result, even if the length of the signal @5 differs for every 70 clips, the inter-clock skinny can be made zero.

In the above embodiment, the comparison clock REF is used to facilitate the detection of the phase difference in the phase comparison circuit 23.
It is preferable that the frequency is the same as that of the clock 8CK supplied to the flip-flop. The reference clock MCK is preferably an integral multiple (preferably a power of 2) of the frequency of the comparison clock REF. Therefore, in the above embodiment, the clock generation circuit 1 generates the reference clock MCK having a frequency 16 times that of the comparison clock REF.
It is supplied to each clock skew adjustment circuit 2. Then, in each clock skew adjustment circuit 2, the supplied reference clock MCK is divided into 16 parts by IK, and the corresponding 7 lips 7 are divided.
I am trying to supply it to 0tsugu3.

Furthermore, when this invention is applied, the clock skew adjustment circuit 2 may be provided for all the flip-flops 3 in the LSI, but when there are many 7-lip and 70-tub chips, the chip size increases. Because I end up doing it,
The number of clock skinny adjustment circuits may be reduced by selecting seven lip-flops to feed back the clock to the clock skew adjustment circuit 2. In this case, the number of 7 lip-flops can be determined by, for example, selecting 7 lip-flops on the critical path that directly affects the operating speed of the system, or dividing the internal circuit of the LSI into multiple blocks and 7 in the center of
Possible methods include selecting 70 Lips as a representative.

As explained above, in the above embodiment, clock key adjustment circuits each consisting of a one-clock variable delay means, a phase comparison means, and a frequency dividing stage are arranged at multiple locations in the system, and each clock is transmitted from one clock generation source. Clock key - provides a common frequency quantity, f, and phase information signal to the adjustment circuit. The length of each signal line that transmits the common frequency information (MCK) is approximately equal, and the phase information signal (RE
The lengths of the respective signal lines transmitting F) are also approximately equal. Therefore, clock skew can be reduced.

Furthermore, the clock is fed back from the clock input terminal of the circuit to which the output signal of the clock skew adjustment circuit is supplied to the phase comparison means of the clock skew adjustment circuit,
Since the phase difference with the phase information signal is detected and the variable delay means is operated so that the phase difference becomes zero,
Based on the phase information from the clock generation source, each clock skinny adjustment circuit forms a clock whose phase matches that of the reference clock and supplies it to each section. Therefore, clock skew can be reduced compared to a system in which the distances from one clock generation source are different and clocks are directly supplied to multiple users without going through the clock key adjustment circuit. As a result, although the invention made by the present inventor has been specifically explained based on the embodiments, the present invention is not limited to the above embodiments, and is within the scope of the invention without departing from the gist of the invention. It goes without saying that various changes can be made. For example, the frequency division stage 22 in the clock skew adjustment circuit 2 is not necessarily required and can be omitted. Further, the clock supplied from the clock generation source 1 to the clock skinny adjustment circuit 2 does not need to be divided into two parts, the reference clock MCK as frequency information and the comparison clock REF as phase information, but the frequency information and the phase information. It is also possible to have one clock that has both types of information.

In the above explanation, the invention made by the present inventor was mainly applied to a logic LSI whose internal circuit operates in synchronization with a clock, which is the background of the invention, but this EA is limited to that. Instead, it can be used in computers and other clock synchronized systems configured by a plurality of LSIKs mounted on a board such as a ceramic substrate or by combining such boards.

(9) The distances between the clock generation source and each clock skew adjustment circuit do not necessarily have to be approximately equal; it is sufficient that the signal delays therebetween are approximately equal.

FIG. 6 shows another embodiment of the invention.

In this embodiment, the portion vcphase 1ocked 1oop circuit PL that can be equally delayed from the clock generator 1
A plurality of L61s are arranged to match the phase of the comparison clock RBF and the signal fed back from the 7-lip-flop 3.

By matching all the delays of the feedback signal lines 4, it is possible to accurately match the phases of the clocks supplied to each of the seven lip-flops.

FIG. 7 shows an internal block diagram of the PLL 61. Phase comparison circuit 23. Variable frequency generator (VFO)
71 and the frequency dividing circuit 22.

A signal with a frequency N times the frequency of the input signal is generated by the VFO 7, and then a signal with a necessary frequency from N times to 1 times is generated by the frequency dividing circuit 22. A signal having the same frequency as the frequency of the N×X comparison clocks R and EF is returned to the feedback signal line 4.

FIG. 8 shows an embodiment in which the clock generation circuit 1 and each PLL circuit 61 are coupled by an optical cable. By utilizing the high speed and steep rise and fall characteristics of light, variations in signal transmission delay can be reduced. Clock generation circuit 1
This is particularly effective when the distance between the clock generator 1 and the PLL circuits 61 is large, such as when the clock generator 1 and each PLL circuit 61 are formed on separate IC chips.

In the embodiment of FIG. 8, instead of the PLL circuit 61, the first
It is also possible to utilize the clock skinny adjustment circuit 2 shown in the figure.

FIG. 9(5) shows an embodiment of the delay means DLY1 shown in FIG. In this embodiment, a temperature compensation circuit TC is provided for adjusting the temperature characteristics of the delay circuit DL. The delay circuit DL includes a differential transistor pair Ql, Q2 receiving differential input signals I, I and their common current source transistor Q3, and emitter follower transistors Q4 . It is composed of Q5 and their current source transistors Q6, Q7, etc. The temperature compensation circuit TC includes a differential transistor pair Q8, Q9,
Their common current source transistor Q10. Darlington-connected output transistors Ql 3 and Q14, current source transistors Ql 5 and Ql 6, transistors Q11 and Q12 provided to form a base reference voltage of the common current source transistor QIO, a diode D1, etc. be done.

The output signal of the above temperature compensation circuit TC is the voltage 7 year old lower circuit O
It is supplied to the bases of the transistors Q6 and Q7 via P2. The temperature coefficient of the voltage VCS supplied to this base is 1 to 2 mv/.°C. By having such a temperature coefficient, the delay time tpd caused by temperature rise can be reduced by emitter follower transistors Q4 and Q5.
This can be canceled out by improving the driving capacity of ) in FIG. 9 shows the relationship with the delay time tpd when the temperature changes. The temperature is TI, T2. When the temperature coefficient of the voltage VO2 is OmV/'C when the voltage increases to T3, the delay tpd increases significantly as shown by the broken line 11.

On the other hand, when the temperature coefficient of the voltage VO2 is 2 mV/'C as shown by the broken line J3, the delay tpd hardly increases as shown by the broken line 13. Ideally 2tpd
/2Tj=0 is desirable.

Vcs which determines the emitter 7 lower current by this circuit
Control people, 2 tpd 72 Tj 2:o, 1
~0.15ts/°C.

In addition, in FIG. 9cA), the reference voltage generation circuit Vre
f,,Ge, form a reference voltage VC8 having a coefficient of −1,2 mV/”C (D temperature), and this reference voltage is supplied to the bases of the transistors Ql 5 , Ql 6 , Q8, and The voltage is supplied to the base of the transistor Q3 via the voltage follower circuit OPl.

The tenth position shows another embodiment of the delay means DLYI shown in FIG. Since the circuit of this embodiment and the delay circuit DL shown in the ninth section have the same basic components, corresponding components are given the same reference numerals. Figure 9 (8
) is different from the delay circuit DL in that it has a junction capacitor -1c1. Cz is connected and the delay is compensated for by applying the bias voltage Vc.

FIG. 10(B) shows the relationship between the bias voltage Vc and temperature Tj, and FIG. 10(C) shows the relationship between the junk silane capacitance C1°C2.
The relationship between the capacitance value C and the temperature Tj is shown. 2VC/2Tj is set negative as shown in Figure 10 (B), and as shown in Figure 10 (C)
By making 2C/2Tj negative as shown by K, the delay due to temperature rise can be canceled.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, in a system where the inside of an LSI operates in synchronization with a clock, it is possible to reduce clock skew and reduce the timing margin in system design.
System speedup can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the inventive part of a logic LSI to which the clock skew adjustment method according to the present invention is applied, and FIG. A block diagram showing an example of the Il adjustment circuit, FIG. 3 is a circuit diagram showing an example of the variable delay means constituting the clock ski-11 adjustment circuit, and FIG. 4 is a timing chart showing the input/output timing of the clock skew adjustment circuit. , FIG. 5 is a circuit configuration diagram showing an example of another feedback method in the clock skew adjustment circuit, FIG. 6 is a block diagram showing another embodiment of the present invention, and FIG. 7 is a diagram showing the PLL circuit shown in FIG. 6. FIG. 1 is a block diagram of an embodiment. FIG. 8 is a block diagram showing still another embodiment of the present invention, FIG. 9 (8) is a circuit diagram of one embodiment of the delay means shown in FIG. 3, and FIG. 9 (B) explains its operation. FIG. 10 (ASVi, another embodiment circuit diagram of the above-mentioned delay means, FIG. 10 03) and FIG. 10 (C) are characteristic diagrams for explaining its operation. DESCRIPTION OF SYMBOLS 1... Clock generation circuit, 2... Clock adjustment means (clock key adjustment circuit), 3... Flip-flop, 4... Feedback signal line, 23... Phase comparison circuit (PD), 61 ...Fizz locked lock (PLL), 71...Variable frequency generation circuit (VFO)
), 81... Spectrometer, 82... Optical cable, REF
...Comparison clock, MCK...Reference clock, F
B...Feedback signal line, SCK...Slave clock, DLYI, DLY2, ~DLYn-delay means, Vref, Ge, -base*m pressure generation circuit, D
L...Delay circuit, TC...Temperature compensation circuit, I, I・
... Differential input signal, OPI, OF2 ... Voltage follower circuit, C1C2 ... Junction capacitance. Figure 1 Figure 3 Figure B Figure

Claims (1)

[Claims] 1. A clock generation source, and a plurality of clock adjustment means for forming clocks whose phases match each other based on frequency information and phase information supplied from the clock generation source. . A logic integrated circuit, wherein the clock generation source and each clock adjustment means are arranged so that signal delays between them are approximately equal. 2. The clock adjustment means includes a phase comparison means for detecting a phase difference between a clock having phase information from a clock generation source and a signal from a feedback system, and delaying a clock having frequency information according to the phase difference. 2. The logic integrated circuit according to claim 1, further comprising variable delay means. 3. The clock having the phase information and the clock having the frequency information are separate clocks, and the clock having the frequency information has a higher frequency, and the clock adjustment means divides the clock delayed by the variable delay means. 3. The logic integrated circuit according to claim 2, further comprising a frequency dividing stage that rotates. 4. The variable delay means includes a plurality of delay circuits that receive a common input signal and each have a different delay time, and a selection circuit that selects one of the output signals of each delay circuit. Logic integrated circuit according to the second item in the range. 5. Each of the above delay circuits has an emitter follower output circuit that forms the above output signal, and by making the drive capability of this emitter follower output circuit variable, the temperature dependence of the delay time is compensated. A logic integrated circuit according to claim 4, characterized in that: 6. The emitter current source of the emitter follower output circuit includes a bipolar transistor whose base is supplied with a reference voltage, and the drive capability of the emitter follower output circuit is varied based on the temperature coefficient of the reference voltage. A logic integrated circuit according to claim 5, characterized in that: 7. The logic integrated circuit according to claim 6, wherein the temperature coefficient is a positive temperature coefficient. 8. Having a plurality of PLL circuits for forming, based on the phase information signal supplied from the clock generation source, clocks that are signals of a higher frequency than the frequency of the phase information signal and that are in phase with each other. A logic integrated circuit featuring: 9. The logic integrated circuit according to claim 9, wherein the clock generation source and each PLL circuit are arranged so that signal delays between them are approximately equal. 10. It has a plurality of PLL circuits for forming, based on the phase information signal supplied from the clock generation source, clocks having a frequency higher than that of the phase information signal and whose phases match each other. A clock signal supply system comprising: a plurality of optical cables coupled between the clock generation circuit and each PLL circuit for supplying the phase information signal to each PLL circuit.