JP3182244B2 - Method for optimizing signal propagation delay time in semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LS using a computer.
The present invention relates to a method of creating an accurate wiring prediction path and performing a signal propagation delay time using the created wiring prediction path when executing the schematic placement of a logic cell or improving the current placement state in connection with I design. is there.

[0002]

2. Description of the Related Art Microfabrication of a semiconductor integrated circuit can be expected to have advantages such as a reduction in manufacturing cost due to an increase in a circuit size mountable per chip and an increase in performance due to an increase in operation speed. The influence of the wiring resistance component on the delay time cannot be ignored, which causes a problem that it is difficult to guarantee the operation performance of the circuit in the layout design.

Conventionally, a method of estimating a delay time at the stage of layout, especially before wiring in response to the problem of timing assurance has been based on a method of simply considering a capacitance load ignoring a resistance component (Japanese Unexamined Patent Publication No. 048389, JP-A-4-106666). However, as the circuit becomes finer, the delay of the signal propagating on the wiring has increased in relative proportion compared to the internal delay of the gate. Delay prediction accuracy is not enough.

Therefore, even at a stage before wiring in a layout, it is necessary to accurately predict a propagation delay in consideration of wiring resistance. For that purpose, means for predicting the wiring path with high accuracy from the schematic arrangement state of the logic gates is indispensable.

In order to accurately estimate a signal propagation delay in consideration of wiring resistance, it is necessary to perform a path prediction in consideration of wiring branching. As a conventional wiring model for predicting a wiring length and a wiring path, Half Perimeter (half circumference of the minimum rectangle of the net / FIG. 7A) as shown in FIGS. , Minimum Spaning Tree (b), Ch
ain (c), complete graph (d), Single Trunk Steiner
Tree (e) and Steiner Tree (f) are known (M.
A. Breuer, “Design Automation od Degital System
s ”, Vol.1, Theory and Techniques, Prentice-Hall In
c., 1972). Note that the crosses in the figure indicate terminals.

[0006] Of these, (a) to (e) have a poor accuracy in predicting the wiring length of a multi-terminal net, and in (a) to (d), the total wiring length can be predicted, but the branching of the wiring is accurate. Therefore, it is not suitable for propagation delay prediction. (F) is a method with relatively high accuracy among these, but the number of net terminals that can be calculated within a finite time is limited and cannot be used practically.

On the other hand, the timing constraints include an upper limit constraint defining an upper limit value of the time from the start point (source) to the end point (sink) of the path and a lower limit constraint defining a lower limit value. Conventionally, Japanese Patent Application No. 3-167237 discloses a method for optimizing the upper limit of timing.

FIG. 8 is a flowchart for explaining a path delay optimizing arrangement method described in Japanese Patent Application No. 3-167237. At step P1 in FIG. 8, a critical path is extracted by performing a delay analysis of the circuit, and a timing constraint for properly operating the circuit with respect to all the critical paths is added. In the processing order of the paths in step P2, the paths are rearranged in ascending order of the difference (slack) between the design required time and the predicted or measured value, and the path processing order in the following processing is created.

When the path to be processed is selected, cells related to the path are classified into a path core cell which controls the path of the path and a path branch cell which does not. (P4).
First, an arrangement position of a path core cell is determined to minimize the path shape of a path (P5), and then an arrangement position of a path branch cell is determined to minimize an individual net length (P6).

If the arrangement positions of the path core cell and the path branch cell are determined, the processing of one path is completed, and the processing shifts to the next path (P7). Then, when the processing of all the paths is completed, the operation of the circuit is analyzed, and the critical path is updated (P8). If all the paths satisfy the design specifications, the processing is terminated, and if there are paths that do not meet the restrictions, the processing is performed again on those paths (P3).

However, in this method, attention is paid only to the upper limit of the timing, and there is no guarantee that the lower limit is satisfied. Therefore, this is not a method for truly optimizing the signal propagation delay time of a circuit.

[0012]

As described above, in the conventional method for analyzing signal propagation delay in an unwired state in a layout design, the method for predicting a wiring path has insufficient accuracy and prediction results. However, the signal propagation delay time cannot be optimized within a practical time.

In order to operate the circuit correctly,
The upper limit and lower limit of timing must be satisfied at the same time. However, the conventional method of optimizing the signal propagation delay time is a method of mainly optimizing the upper limit of timing. There were insufficient points to guarantee proper operation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the first invention is to accurately predict a wiring path from an arrangement state of a layout design, and to use the result to output a signal. An object of the present invention is to provide a method for optimizing a signal propagation delay time in a semiconductor integrated circuit capable of optimizing a propagation delay time.

The object of the second invention is as follows.
An object of the present invention is to provide a method for optimizing a signal propagation delay time in a semiconductor integrated circuit, which can simultaneously satisfy an upper limit constraint and a lower limit constraint on timing for all critical paths in order to guarantee circuit operation. .

[0016]

In order to achieve the above object, a first aspect of the present invention is to determine a layout position of a logic cell on a semiconductor integrated circuit by determining a terminal constituting a net based on the coordinates of the terminal. a plurality of terminals set formed from the relative distances between the terminals create the wiring predicted path of the terminal in the set to each set, the procedure for connecting the wiring predicted path of each terminal set created in the above, the entire net after creating the wiring predicted path hierarchically, and wherein optimizing the signal propagation delay time by using the wiring predicted path of the entire created net.

More specifically, a plurality of terminal sets are formed from the relative distances between the terminals constituting the net on the semiconductor integrated circuit, and the center of gravity of the terminals in the terminal set is determined within the formed terminal set. Pierce, with the minimum rectangular longitudinal wiring formed by the terminal set as the trunk, to create a wiring prediction path with the wiring generated vertically from each terminal to the trunk as a branch line, for each terminal set, A point on the wiring prediction path formed in the terminal set that is closest to the position of the center of gravity of all the terminals constituting the net is determined as a representative point of each terminal set, and passes through the center of gravity of each representative point. With the minimum rectangular longitudinal wiring formed by the representative point set of
A wiring prediction route for the entire net is created with the wiring generated from each representative point perpendicular to the trunk as a branch line, and the signal propagation delay time is optimized using the created wiring route for the entire net.

In particular, when forming a plurality of terminal sets from the relative distances between the terminals constituting the net, the terminal set is seeded in order from the terminal having the largest linear distance from the position of the center of gravity of all the terminals constituting the net. It is best to select terminals that belong to the same set of terminals whose linear distance from the selected seed is within the radius of a circle with an area approximately equivalent to the area occupied by the net divided into multiple equal parts It is.

According to a second aspect of the present invention, a signal path serving as an operation constraint on a semiconductor integrated circuit is extracted, an upper limit and a lower limit related to the extracted signal path are obtained, and a net constituting the extracted signal path is determined. The above lower limit constraint is distributed, and this is added as a constraint for each terminal to define a minimum range in which the terminals can be close to each other, and a plurality of logic cells constituting the extracted signal path are physically assigned to the entire signal path. The path core cell that governs the shape and the path branch cell that configures the net that branches off from the signal path are classified, the path core cell is arranged at a position where the signal path length is reduced, and the lower limit constraint added as a constraint for each terminal is If not,
The method is characterized in that the path branch cell is arranged at a position where the net length is shortened after a repulsive force for improving this is generated and the violation of the lower limit constraint is improved.

[0020]

According to the first aspect of the present invention, the wiring prediction route for the entire net is hierarchically created, and in particular, clusters (terminal sets) are formed from terminals far from the center of the net, so that highly accurate wiring route prediction is performed. Therefore, the signal propagation delay time can be optimized.

According to the second aspect of the present invention, the minimum range in which the terminal pair can approach each other with respect to the terminal connected to the net related to the critical path is defined in advance, so that the upper limit in consideration of the lower limit is considered. Constraint optimization becomes possible.
As a result, the upper limit value and the lower limit value of the timing constraint can be satisfied at the same time, and accurate operation of the entire circuit can be guaranteed.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

First Invention FIG. 1 is a simplified diagram for explaining a method of predicting a wiring path from a schematic arrangement state of a logic gate.

First, the terminals are clustered based on the relative distance between the terminals (marked by x) constituting the net to be processed (the whole of FIG. 1) to form a cluster 1 as a terminal set. Here, the terminal 3 is an independent terminal that could not be clustered.

As the clustering method, the method of forming the cluster 1 analytically only from the coordinates of the terminal according to the first invention is optimal. That is, first, based on the center of gravity position o of all the terminals constituting the net, the seeds of the cluster 1 are set in order from the terminal having the largest Euclidean distance (linear distance) therefrom.

A terminal whose Euclidean distance from the seed is within the radius of a circle having an area substantially equivalent to １ ／ of the area occupied by the minimum rectangle 5 of the net is assigned to the same cluster 1. The area is not limited to 1/4, but may be an area substantially equivalent to an area obtained by equally dividing the occupied area of the net into a plurality.

The clustering method is not limited to the method according to the first invention, but may be the following method. Any method may be selected based on the size of data to be processed.

The following method is a method using the adjacency between terminals, which is a method based on an adjacency graph in both XY directions with terminals as nodes on a two-dimensional plane on which terminals are arranged. is there. The edge stretched between the terminals has a representative length (minimum rectangle 5 of the net) calculated from the spread of the net.
The distance x or y between the terminals standardized by the radius of a circle having an area substantially equivalent to the area of the terminal is expressed as the weight of the edge stretched between the terminals, and the adjacency is expressed.

If the adjacency is equal to or smaller than a predetermined threshold value (for example, 0.25) in order from the edge having the smallest adjacency, it is determined that the two nodes belong to one cluster 1. This is sequentially performed for each edge, and all nodes are clustered. However, one node shall not be allowed to belong to multiple clusters 1
The nodes that are not clustered are registered as forming one cluster 1 with the one node.

After clustering using any of the above-described methods, first, a wiring route prediction in each cluster 1 is performed. The prediction of the wiring path 7 in the cluster 1 is performed by penetrating the center of gravity position p of the position of the terminal in the cluster 1, setting the trunk in the longitudinal direction of the minimum rectangle of the terminal in the cluster 1, and branching from each terminal position perpendicularly to the trunk. Generate and create.

Next, the position on the wiring prediction path 7 in the cluster 1 where the Euclidean distance from the center of gravity o of all the terminals constituting the net is the shortest is defined as the cluster 1
And register it as a representative point 9 (double circle in the figure). Since the terminal 3 is an independent terminal, the position of the terminal is the representative point 9.

The representative point 9 obtained in this manner is used to create a wiring prediction path 11 for the entire net in the same procedure as the method for preparing the wiring prediction path 7 in the cluster 1.
Finally, the signal propagation delay time can be optimized by applying the ELMORE delay calculation method using the created wiring prediction path 11 for the entire net.

FIG. 2 is a diagram showing the accuracy of the wiring route prediction of the present invention with respect to the total wiring length of the net. The data used is data of a gate array of 129KG and 12000 cell scale, and the Single Trunk Steiner Tree method (broken line in the figure) has been used as a typical method conventionally used.
FIG. 4 is a diagram showing how much error the present method (solid line) and the conventional method have with respect to the actual wiring result, taking the Half Perimeter method (dotted line) as an example.

The horizontal axis of the graph is the number of terminals of the net, and the vertical axis is the average of the error between the wiring length of each net for each terminal and the actual wiring length. As shown in this graph, in the present invention, a higher prediction accuracy than the conventional method is obtained for the number of terminals of almost all nets.

FIG. 3 shows the accuracy of delay prediction by the signal propagation delay time optimizing method according to the present invention with respect to the above-mentioned data. The horizontal axis indicates the error (absolute value) of the present invention with respect to the delay time calculated from the actual wiring path, and the vertical axis indicates the number of terminal pairs. As can be seen from this figure, in the present invention, 90% of all calculated terminal pairs
The above is within 20% error.

Second Invention FIG. 4 is a flowchart of the second invention. First, a delay analysis of a circuit is executed to extract a critical path (step Q1). In step Q1, a lower limit constraint on the path delay is allocated to each net, as will be described in detail later. Next, the lower limit constraint for each net allocated in step Q1 is added to each terminal (step Q2).

If the processing procedure is created in step Q3 and the constraint is not satisfied (step Q4 negative), the cells constituting the path to be processed are the path core cells that govern the physical shape of the entire path path. And path branch cells constituting a net branched from the path route (step Q5).

Next, if the lower limit constraint of each terminal added in step Q2 is not satisfied, a repulsive force is generated between the terminals to determine an arrangement position of the path core cell satisfying the lower limit constraint (step Q6).

Subsequently, the arrangement position of the path branch cell is determined in order to minimize the individual net length (step Q).
7). When the arrangement positions of the path core cell and the path branch cell are determined, the processing of one path is completed, and the path to be processed next is shifted (step Q8).

When all the paths have been processed, the operation of the circuit is analyzed, and the critical path is updated (step Q9). If all the paths satisfy the constraint, the process is terminated, and if there is a path that does not satisfy the constraint, the process is performed again on that path.

Hereinafter, specific processing in steps Q1, Q2, and Q6, which are features of the second invention, will be described. The lower limit constraint of the path delay is as follows. First, in step Q1, the lower limit constraint is allocated to each net in consideration of the fan-out of the net, and then, in step Q2, the terminal of the path core cell constituting each net to which the lower limit constraint is allocated is assigned. On the other hand, a lower limit constraint of the path delay is added.

First, in step Q1, an upper limit value and a lower limit value of the time required for a signal from the start point to the end point of a path are given to each critical path. In order to guarantee the required operation speed of the circuit, the signal propagating through each critical path must be within the arrival time required for each path.

The lower limit constraint of the path is satisfied if the sum of the lower limit constraints assigned to each net is equal to or larger than the lower limit value. That is, the lower limit constraint of the delay may be assigned to each net such that the lower limit constraint of the path ≤ the lower limit constraint of the net. In order to allocate delay equally to all nets, the lower limit constraint of the net A = the lower limit constraint of the path / the number of nets constituting the path may be set. Further, in order to further allocate in consideration of the fanout of the net, the lower limit constraint of the net B = the lower limit constraint of the net A × (the fanout of the net) / (the average fanout of the net constituting the path) good. By performing this for all the nets constituting the critical path, a lower limit constraint is assigned to each net.

Next, in step Q2, information on the lower limit constraint of the two upper and lower constraints is added to each terminal of the critical net. A method of adding a lower limit constraint to each terminal will be described with reference to FIG. Terminals A and B in FIG.
Indicates the lower limit of the path added to the terminals A and B related to the critical net. In the wiring process, when two orthogonal wiring layers are used,
The lower limit constraint allocated to the net is satisfied when the terminal B is placed on the quadrilateral shown by the solid line surrounding the terminal A in FIG.

As an example, if the lower limit constraint added to the terminals A and B is set to half the size of the constraint indicated by the solid line connecting A and B, the lower limit constraint added to the two terminals A and B is added. By matching, it becomes equal to the lower limit constraint assigned to the target net. That is, the lower limit constraint allocated to the net can be achieved by arranging the two terminals A and B so that the quadrilateral regions indicated by the dashed line do not overlap. In this way, in step Q2, a restriction distance between terminals that can secure a wiring length that satisfies the lower limit restriction of the path is defined in advance.

Finally, a method of generating a repulsive force in step Q6 will be described. FIG. 6 shows a path delay relaxation force (repulsive force) F defined for considering the lower limit value of the path delay in step Q6. If the lower limit constraints of the terminals A and B of the nets constituting the path added in step Q2 are not satisfied, they overlap with the lower limit constraint quadrilaterals added to the terminals A and B as shown in FIG. Is generated. At this time, forces acting in opposite directions on a straight line connecting the terminals A and B are applied to the respective terminals in proportion to the overlapping area of the quadrilateral corresponding to the lower limit constraint added to the terminals.

However, if there is no violation of the lower limit constraint, that is, if there is no overlap with the dashed-dotted quadrangle,
This force is defined as zero. By combining this force with the conventional path delay relaxation force (attraction) in step Q6, it is possible to obtain an arrangement result that satisfies not only the upper limit constraint but also the lower limit constraint.

[0048]

As is clear from the above description, the use of the first invention makes it possible to accurately predict the wiring path in the unwired state in the layout. The wiring resistance can also be taken into consideration, and the signal propagation delay time can be optimized.

According to the second aspect of the present invention, it is possible to obtain an arrangement result that simultaneously satisfies the upper limit and lower limit of the timing for all the critical paths of the circuit. Therefore, the signal delay time is optimized. Can be.

[Brief description of the drawings]

FIG. 1 is a simplified diagram for explaining a wiring path prediction method according to a first invention.

FIG. 2 is a graph showing a comparison between a wiring path prediction result of the first invention and a conventional wiring path prediction result.

FIG. 3 is a graph showing a signal propagation delay prediction accuracy according to the first invention.

FIG. 4 is a flowchart showing a processing outline of the second invention.

FIG. 5 is a simplified diagram for explaining a method of creating a lower limit constraint on a terminal.

FIG. 6 is a simplified diagram for explaining a path delay mitigation force used for improving a lower limit constraint violation.

FIG. 7 is a simplified diagram showing a conventional wiring path prediction method.

FIG. 8 is a flowchart showing a processing outline of a conventional path delay optimizing method.

[Explanation of symbols]

 Reference Signs List 1 cluster 3 terminal 5 smallest rectangle of net 7 predicted route in cluster 9 representative point 11 predicted route of entire net o, p center of gravity A, B terminal F relaxation force (repulsive force)

Claims (4)

(57) [Claims] Upon 1. A determines the arrangement position of the logic cells on the semiconductor integrated circuit, and the coordinates of the terminal group to form a plurality of terminals set from the relative distances between the terminals constituting the network, the terminal sets every to create a wire predicted path of terminals in the set, the procedure for connecting the wiring predicted path of each terminal set created in the above, after creating the wiring predicted path of the entire net hierarchically, the entire net created in the above A signal propagation delay time in a semiconductor integrated circuit, wherein the signal propagation delay time is optimized by using the wiring prediction path. 2. A plurality of terminal sets are formed from relative distances between terminals constituting nets on a semiconductor integrated circuit, and a center of gravity of a terminal in the terminal set is penetrated in the formed terminal set. A wiring prediction route is created with the wiring in the longitudinal direction of the smallest rectangle formed by the set as the trunk, and the wiring generated perpendicularly to the trunk from each terminal as a branch line. Find the point on the predicted wiring route formed in the terminal set that is closest to the center of gravity position of all the configured terminals as the representative point of each terminal set, penetrate the center of gravity position of each representative point, and execute all representative points. A wiring prediction route for the entire net is created, in which the wiring in the longitudinal direction of the minimum rectangle formed by the set is used as the trunk, and the wiring generated perpendicularly to the trunk from each representative point is a branch line. Predicted wiring route The optimizing of the signal propagation delay time in the semiconductor integrated circuit, characterized in that to optimize the signal propagation delay time using. 3. When forming a plurality of terminal sets from relative distances between terminals constituting the net, a terminal set is seeded in order from a terminal having a larger linear distance from the position of the center of gravity of all terminals constituting the net. It is characterized in that terminals whose linear distance from the selected seed is within the radius of a circle having an area approximately equivalent to the area occupied by the net is divided into the same terminal set. 3. The method for optimizing a signal propagation delay time in a semiconductor integrated circuit according to claim 2. 4. A signal path serving as an operation constraint on the semiconductor integrated circuit is extracted, an upper limit constraint and a lower limit constraint relating to the extracted signal path are determined, and the lower limit constraint is distributed to nets constituting the extracted signal path. This is added as a constraint for each terminal to define a minimum range in which the terminals can be close to each other, and a plurality of logic cells constituting the extracted signal path are defined as a path core cell which controls the physical shape of the entire signal path. If the path core cells are classified into path branch cells constituting a net branched from the signal path, and the path core cells are arranged at positions where the signal path length is shortened, and if the lower limit constraint added as a constraint for each terminal is not satisfied, After generating a repulsive force for improving this, and improving the violation of the lower limit constraint, the path branch cell is arranged at a position where the net length is shortened. Optimization method of the signal propagation delay time in the semiconductor integrated circuit.