JP2002110797A - Method for designing clock wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for timing analysis of multiple number of times after modifying and completing a layout and reduce a clock skew, without using a dedicated clock interconnection layer. SOLUTION: A macro delay model F2 has been formed in advance, and a delay calculation of a top level is performed using the delay model F2, and thus the clock skew between each of macros 2 and 3 of clock supply targets in a function block which is a design target is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock wiring design method, and more particularly to a clock wiring design method in a layout design in which functional blocks are hierarchized.

[0002]

2. Description of the Related Art With the advance of semiconductor technology in recent years, LSI
In (large-scale semiconductor integrated circuits), higher speed, higher integration, and larger scale are being promoted. Particularly, in a logic circuit, an LSI chip is being designed according to a so-called deep submicron design rule of 0.35 μm or less. Many high-integration chips of this type use a frequency on the order of several hundred MHz to several GHz as a clock.

In such a high-speed LSI, a difference in clock delay time between functional circuits causing a malfunction,
That is, it is important to reduce clock skew.

Conventionally, clock transmission wiring (hereinafter referred to as clock wiring) for reducing such clock skew.
In general, a clock tree synthesis (CTS) from an output terminal of a clock generation circuit to a cell group as a functional block to which a clock is supplied is performed as a wiring method (hereinafter referred to as a clock wiring method). A method of reducing skew was used. However, with the recent increase in the scale of LSIs, the man-hours and processing time for layout design have increased, and enormous man-hours and processing time have been required to perform layout at one time.

[0005] As is well known, an LSI design generally includes a function design for defining and designing a function block, which is a component of a function unit, an operation to be realized, a logic design for converting a function block into a logic circuit, and a mask for a logic circuit. And a layout design for converting to a pattern.

In the layout design of an LSI chip in consideration of a wiring delay time, functional blocks are divided into two layers, an upper layer (hereinafter referred to as a top level) and a lower layer (hereinafter referred to as a macro), and are hierarchized. A layout design method called a top-down method in which a top-level layout is first performed using a hierarchical design method for individually performing each layout in a macro is widely used.

[0007] In order to solve the above problem and develop an LSI at low cost and in a short period of time, it is required to reduce clock skew when a top-down layout design method is performed.

To meet this demand, Japanese Patent Laid-Open Publication No.
FIG. 8 is a block diagram and an explanatory diagram showing the operation of the conventional first clock wiring design method described in Japanese Patent Application Publication No. 8376 (Document 1).
Referring to FIGS. 1A to 1C, in the first conventional clock wiring design method, a clock wiring target functional block includes a clock net output block 1 and two macros 2 and 3. The level wiring is a clock wiring from the output block 1 of the clock net to each of the two macros 2 and 3. In order to perform clock wiring from the output block 1 of the clock net to each of the two macros 2 and 3, first, the output terminals (hereinafter referred to as clock output terminals) 11 provided in the output block 1 of the clock net are connected to the macros 2 and 3.
Draw straight lines 7 and 8 connecting the centers 25 and 35 of the macros, and the intersection 20 between the straight lines 7 and 8 and the peripheral sides of the macros 2 and 3
1 and 301 are obtained (FIG. 8A).

Next, based on the longest distance from the clock output terminal 11 to the intersection on the peripheral sides of the macros 2 and 3,
Intersections 201 and 302 on the peripheral sides of the macros 2 and 3 are obtained (FIG. 8B). Finally, the intersections 201 and 302 are set as the positions of the external (clock) terminals of the macros 2 and 3 in the macro. A wiring process is performed (FIG. 8C). By the above processing, the wiring from the clock output terminal 11 to the clock terminals (intersection points) 201 and 302 of the macros 2 and 3 becomes the same length. When arranging cells in each of the macros 2 and 3, cells connected to the clock terminals 201 and 302 (hereinafter referred to as clock terminal connection cells) are referred to as clock terminals 201 and 302.
By arranging the macro terminal 302 near the clock output terminal 11 and the clock terminal 20 inside each of the macros 2 and 3,
The clock skew is reduced by making the distances to the clock terminal connection cells of 1,302 equal.

However, in the first conventional method for designing clock wiring, a buffer for input / output separation is not added near the clock terminal, and a delay model of the macro itself is not created. The top-level delay calculation required for the down-type layout design cannot be performed with high accuracy.

For this reason, even when the top-level clock wiring is of the same length as described above, the difference between the capacitances between adjacent wirings due to the difference between wirings adjacent to the clock wiring and the like causes each macro from the clock output terminal to be connected to each macro. The delay value up to the clock terminal differs. As a result, even if the clock terminal connection cells are arranged near the terminals when performing the macro arrangement, the clock delays of the clock output terminal and the plurality of clock terminal connection cells in the macro are not equal, and the clock skew is large. May be.

Further, when performing the top-level delay calculation, since the functional blocks (cells) in the macro are not arranged, the top-level delay taking into account the accurate load after the placement and routing in the macro is considered. Cannot perform calculations.

Referring to FIG. 9 which shows a flow chart of a conventional method of designing a second clock wiring, FIG. 9 shows a conventional method of designing a second clock wiring. First, a macro is arranged (step P1). The terminal position of the level is determined (step P2). Next, top-level CTS
To match the clock skew up to the clock terminal of the macro (step P3), implement top-level wiring (step P4), and extract information (hereinafter, RC information) F101 on the resistance R and capacitance C of each wiring.

On the other hand, after step P2, the macros are arranged in the macros (step P11), and the CTSs in the macros are performed so that the delays of the macros are equal (step P1).
2) Wiring within the macro is performed (step P13), and RC information F102 of each wiring within the macro is extracted.

A static timing analysis between the clock output terminal and the clock terminal connection cell in the macro is performed based on the RC information F101 and F102 (step P
5) It is checked whether the clock skew is within a predetermined standard value (step P6).

If the result of the check in step P6 is unacceptable, C
Delay adjustment is performed by changing the driving capability of the buffer added in the TS and adding a buffer (step P6), and steps P5 and P6 are performed again.

If the result of the check in step P6 passes, the clock wiring is completed.

In the second conventional clock wiring design method, the load in the macro is not determined when the CTS is performed at the top level and in the macro.

For this reason, first, the input terminal capacitance of the buffer having the maximum driving capability is loaded, top-level CTS is performed, timing analysis is performed after the top-level and layout within the macro is completed, and the clock skew is rejected. As described above, the work of adjusting the delay by changing the driving capability of the buffer added by the CTS or adding the buffer, performing the timing analysis again, and confirming the clock skew occurs.

As a result, it is necessary to perform timing analysis a plurality of times after the end of the layout, in addition to after changing the driving capability of the buffer and after changing the layout for adding the buffer, thereby increasing the number of steps and processing time.

In the third conventional clock wiring design method for reducing clock skew, clock skew is reduced by setting the uppermost layer to a layer dedicated to clock wiring and reducing the capacitance between adjacent wirings.

However, the third conventional method for designing clock wiring requires a layer dedicated to clock wiring, so that it is necessary to increase the number of wiring layers dedicated to clock even in a case where wiring congestion does not occur due to the implementation of clock wiring. . as a result,
The number of wiring layers that are not always necessary increases and the cost increases.

[0023]

In the above-mentioned first conventional method for designing a clock wiring, a buffer for input / output separation is not added near a clock terminal, and a delay model of a macro itself is created. Therefore, the top-level delay calculation required for the top-down layout design cannot be performed with high accuracy. The delay value from the clock output terminal to the clock terminal of each macro is different due to the difference in the capacitance between the wirings. As a result, even if the clock terminal connection cell is placed near the terminal when placing the macro, the clock output terminal and the macro The clock delay of each of the plurality of clock terminal connection cells is not equal, and the clock skew may increase.

Further, when performing the top-level delay calculation, since the functional blocks in the macro are not arranged,
There is a disadvantage that it is not possible to perform top-level delay calculation in consideration of an accurate load after placement and routing in a macro.

In the second conventional clock wiring design method, the load in the macro is not determined at the time of performing the CTS in the top level and in the macro. Therefore, the timing analysis after the layout in the top level and in the macro is completed.・
If the result of the clock skew check indicates that the clock skew is unacceptable, adjust the delay by changing the drive capacity of the buffer added by CTS or adding a buffer, and then perform timing analysis and clock skew check again. Further, in addition to after the layout is changed for adding a buffer, it is necessary to perform timing analysis a plurality of times after the layout is completed, resulting in an increase in man-hours and processing time.

Furthermore, the third conventional clock wiring design method requires a dedicated clock wiring layer. Therefore, it is necessary to increase the number of dedicated clock wiring layers even when the wiring is not congested due to clock wiring. As a result, there is a drawback that the number of wiring layers which are not always required increases and the cost increases.

An object of the present invention is to provide a method of designing a clock wiring which can reduce the clock skew without using a dedicated clock wiring layer and eliminating the need for a plurality of timing analyzes after layout change and completion. Is to provide.

[0028]

According to the clock wiring designing method of the present invention, the functional blocks are divided into two layers, that is, a top level which is an upper layer and a macro which is a lower layer. In a clock wiring design method in a top-down type LSI layout design in which a top-level layout is first performed by using a hierarchical design method in which layouts in a top-level and a macro are individually performed, a delay model of the macro is previously determined. And performing the top-level delay calculation using the delay model to reduce clock skew between each of the plurality of macros to be supplied with clocks in the functional block to be designed. Is what you do.

According to a second aspect of the present invention, in the clock wiring design method according to the first aspect, the macro delay model includes a buffer logic of a library cell description file at a clock terminal in the macro netlist. In addition, a buffer having the same driving capability corresponding to the buffer logic is arranged near the clock terminal when the macro is laid out.

According to a third aspect of the present invention, there is provided a clock wiring designing method, wherein functional blocks are divided into two layers, that is, an upper layer, which is a top level, and a lower layer, which is a macro. Top-down LSI that first performs top-level layout using a hierarchical design method that individually performs each layout
A clock terminal determining step of setting a clock terminal to receive a supply of a clock of each of unplaced first and second macros which are not arranged and routed in a macro in the method of designing a clock wiring in the layout design of A wiring path determining step of performing a general wiring between the clock output terminal and each of the first and second clock terminals set in the macro clock terminal determining step to determine a wiring path; Wiring is performed between the clock output terminal and each of the first and second clock terminals based on the wiring path determined in the path determining step, and RC and information on resistance and capacitance of each wiring are provided.
A top-level wiring step for extracting information; a delay model creation step for creating delay models for each of the first and second macros; and a clock output terminal and the first and second clock output terminals based on the RC information and the delay model. And a static timing analysis between each of the clock terminals and the second clock terminal to calculate first and second delay values which are clock delay values between the clock output terminal and each of the first and second macros. A top-level delay calculation step; a delay difference calculation step of calculating a clock delay difference between the clock output terminal and each of the first and second macros from the first and second delay values; At the time of layout in each of the second macros, a buffer having the same driving capability corresponding to the buffer logic is provided near each of the first and second clock terminals. A buffer arrangement step of location,
A macro arranging step for arranging each of the first and second macros, and a macro for performing clock wiring by a clock tree synthesis method in each of the first and second macros in consideration of the clock delay difference And an internal clock wiring step.

According to a fourth aspect of the present invention, in the clock wiring designing method according to the third aspect, the step of determining the clock terminal of the macro includes the step of determining each of the first and second macros from the clock output terminal of the output block. First and second straight lines connecting the centers of the first and second macros are drawn, and first and second intersections, which are intersections between the first and second straight lines and the periphery of each of the first and second macros, are obtained. At each of these first and second intersections, the first and second macros of the first and second macros, respectively.
Are set respectively.

According to a fifth aspect of the present invention, in the clock wiring designing method according to the third aspect, the delay model creating step includes the step of generating a clock terminal in a macro netlist of the first and second macros. And a buffer model of a cell group of a library cell description file is added to the first and second macros to create a delay model for each of the first and second macros.

According to a sixth aspect of the present invention, in the clock wiring designing method of the third aspect, the functional block includes a clock net having an output block having a clock output terminal for the clock output. The first and second macros each having the first and second clock terminals for clock input, and a clock from the output block, which is the top level wiring, to each of the first and second macros And wiring.

In the clock wiring designing method according to the present invention, the functional blocks are divided into two layers, that is, a top level, which is an upper layer, and a macro, which is a lower layer. Top-down LSI that first performs top-level layout using a hierarchical design method that individually performs each layout
In the method of designing a clock wiring in the layout design, the clocks of the unplaced first and second macros, each of which is not arranged and wired within the macro, and the already arranged third macro already arranged and wired within the macro, A clock terminal for setting a clock terminal to receive the supply of the clock signal, and a step between the clock output terminal and each of the first, second and third clock terminals set in the step for determining the clock terminal of the macro. A step of determining a wiring path for performing a general wiring and determining a wiring path; and wiring between the clock output terminal and each of the first and second clock terminals based on the wiring path determined in the step of determining the wiring path. And a top-level wiring step of extracting RC information, which is information on resistance and capacitance of each wiring, and the first and second wiring steps. And a delay model for extracting a delay value of the third macro from the wiring information of the third macro and creating a delay model including the delay value of the third macro. Steps and
Perform static timing analysis between the clock output terminal and each of the first and second clock terminals based on the RC information and the delay model, and perform a static timing analysis between the clock output terminal and each of the first and second macros. A top-level delay calculating step of calculating first and second delay values, respectively, which are clock delay values, and a step of calculating a clock output terminal and each of the first and second macros from the first and second delay values. Calculating a clock delay difference between the first and second clock terminals during the layout in each of the first and second macros. A buffer arranging step of arranging a buffer, and the first and second buffer groups are arranged so as to be equal to a delay value between a cell group in the third macro and the clock output terminal. And macro intra-macro arranging step of arranging the inside of each of the second and second macros, and clock wiring within the macro for performing clock wiring by a clock tree synthesis method in each of the first and second macros in consideration of the clock delay difference And a step.

According to an eighth aspect of the present invention, in the clock wiring designing method according to the seventh aspect, the functional block includes a clock net having an output block having a clock output terminal for the clock output. A first and a second macro provided with each of the first and second clock terminals for clock input, and a third macro already arranged and wired in a macro having a third clock terminal; A clock wiring from the output block, which is the top-level wiring, to each of the first, second, and third macros.

According to a ninth aspect of the present invention, in the clock wiring design method of the sixth or eighth aspect, the clock wiring is connected to the clock output terminal and the first and second clock output terminals.
And a third buffer for driving the first and second buffers added to each of the first and second clock terminals inserted between the first and second clock terminals.

Further, the invention described in claim 10 is the same as claim 6.
Or the clock wiring design method according to 8, wherein the functional block comprises a clock net having an output block having a clock output terminal for the clock output, and the first and second clock terminals for the clock input. The first and second macros each including the first and second macros and the first and second macros from the output block as the top-level wiring.
Clock wiring to each of the macros, and a control circuit that outputs a control signal according to the setting of a predetermined operating condition, wherein the clock wiring is one of the first and second macros or Both input sides are provided with a logic circuit for stopping passage of the clock in response to the supply of the control signal.

[0038]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

In the clock wiring designing method according to the present embodiment, the functional blocks are divided into two layers, an upper layer (hereinafter referred to as a top level) and a lower layer (hereinafter referred to as a macro), thereby forming a hierarchy. In a clock wiring design method in an LSI layout design called a top-down method in which a top-level layout is first performed by using a hierarchical design method of individually performing each layout of the above, a delay model of the macro is created in advance,
By accurately performing top-level delay calculation using this delay model, clock skew between each of a plurality of macros to be supplied with clocks in a functional block to be designed is reduced. .

In the macro to be supplied with the clock, a delay model is created by adding the buffer logic of the library cell description file to the clock terminal in the net list in the macro.

On the other hand, at the time of layout, a buffer having the same driving capability (hereinafter, clock buffer) corresponding to the buffer logic added to the clock terminal in the macro netlist is arranged near the clock terminal. The delay model of the macro and the method of arranging the clock buffer when performing the intra-macro layout include the clock terminal load in the macro when performing the delay calculation of the top-level clock net and the clock terminal in the macro after the layout. There is an effect that the load becomes equal.

Therefore, even when the placement and routing in the macro is not completed, the same delay calculation as that of the final layout can be performed, and the clock tree synthesis (CTS) in the macro can be performed. By performing CTS in consideration of the delay difference between macros at the time of execution, skew between cells connected to the output terminal of the clock buffer in each macro can also be reduced.

Next, referring to FIG. 1 which shows the first embodiment of the present invention in the form of a flowchart, and FIG. 2 and FIG. 3 which show the operation of the present embodiment in the form of a block, FIG. In the clock wiring design method according to the embodiment, first, a macro terminal position is determined, a top-level wiring path is determined, a top-level wiring is performed, and information on a resistance R and a capacitance C of each wiring (hereinafter, RC information). F1 is extracted (steps S1 to S3).

On the other hand, the buffer logic of the cell group of the library cell description file is added to the clock terminal in the macro net list, and a macro delay model F2 is created (steps S11 and S12).

The static timing analysis between the clock output terminal and the macro clock terminal is performed based on the RC information F1 and the delay model F2, and the clock delay difference between the clock output terminal and each macro is calculated. Further, a buffer is added to the clock terminal in the macro netlist, a buffer corresponding to the buffer logic is arranged near the layout hierarchical terminal, and the macro is arranged. Finally, the CT which takes the delay difference between macros into consideration from the output terminal of the buffer added in the macro
S wiring is performed (steps S4 to S9).

FIG. 2 is a block diagram showing an example of functional blocks to which the clock wiring designing method according to the present embodiment is applied.
Referring to (B), this functional block is common to the conventional one for convenience of description, and is an output block 1 for clock output.
And two unplaced macros 2 and 3 which are not arranged and wired in the respective macros, and are used as top-level wiring from the output block 1 of the clock net to each of the two macros 2 and 3. Assume that a clock wiring is provided.

The output block 1 has a clock output terminal 11 for outputting a clock signal. Each of the macros 2 and 3 receives a clock terminal 21 for receiving a clock signal supplied from the clock output terminal 11 via a clock wiring. 31 is provided.

Each of the macros 2 and 3 has a plurality of cells (elements).
And each cell group has a clock terminal 2
The clock is supplied via an intra-macro clock net connected to 1, 31. However, at the stage of this diagram,
For each of the macros 2 and 3, the netlist in each of the macros 2 and 3 has not been determined, and the cells in the macro have not been arranged. Therefore, the number of cells connected to the clock net in the macro has been reduced. And the arrangement position has not been determined.

Next, in order to calculate a delay difference from the clock output terminal 11 to the clock terminals 21 and 31 of the macros 2 and 3, the output terminal 11 is connected to the clock terminals 21 and 31.
The delay calculation up to 31 is performed. At the time of executing the delay calculation, the delay model F2 of the macros 2 and 3 created separately (step S12) is used, and the load in each of the macros 2 and 3 is made the same as the load after the layout, thereby achieving the top level. An accurate delay calculation is performed (step S4).

The clock output terminal 11 thus obtained
The delay difference is calculated from the delay values between the macros 2 and 3 (hereinafter, the delay values of the macros 2 and 3) (step S5), and the CTS is performed in each of the macros 2 and 3 using the delay difference (step S5). Step S9).

Macros 2 and 3 constituting this functional block
Referring to FIG. 2C, which shows functional blocks obtained by modeling the above as delay models by blocks, first, the delay model 2M of the macro 2 is connected to the clock terminal 21 in the netlist in the macro by a library cell description file. The delay model 2M is created by adding the buffer logic 22M of the minimum driving capability in the cell group of
2 is stored. Similarly, the clock terminal 31 of the macro 3
, A delay model 3M is created by adding a buffer logic 32M, and stored in the delay model (file) F2 (step S12).

Referring to FIG. 3B, which shows the state after the top-level layout by using blocks, FIG.
After the layout in the macro 2, the buffer 22 of the same capacity corresponding to the buffer logic 22M added at the time of creating the delay model
Are arranged near the clock terminal 21 (steps S6 and S5).
7) Perform CTS from the buffer 22 to the cell group 23 to which the clock net is connected (steps S8 and S8).
9). Similarly, after the layout in the macro 3, the buffer 32 corresponding to the buffer logic 32M is arranged near the clock terminal 31, and the CT from the buffer 32 to the cell group 33 is
Perform S.

The cell groups 23 and 33 in these macros 2 and 3
Is a known technique and is not directly related to the present invention.

Next, the operation of the present embodiment will be described in detail with reference to FIGS. 1, 2 and 3 again.
In step S1, clock wiring is performed from the output block 1 of the clock net to each of the two macros 2 and 3.
First, from the clock output terminal (hereinafter, clock output terminal) 11 of the output block 1 to the center 25,
Draw straight lines 7 and 8 connecting 35, find intersections between the straight lines 7 and 8 and the periphery of each of macros 2 and 3, and set clock terminals 21 and 31 of macros 2 and 3 at each of these intersections. I do. At this time, each signal other than the clock net
The same processing is performed on a net such as a power supply to determine a terminal position (FIG. 2A).

Next, in step S2, the clock output terminal 11 and the clock terminals 21, 31 determined in step S1.
The general wiring between them is performed, and the wiring route is determined. At this time, the same processing is performed on nets other than the clock net to determine the wiring route.

Next, in step S3, wiring between the clock output terminal 11 and the clock terminals 21 and 31 is performed based on the wiring path determined in step S2 (FIG. 2B). At this time, the same processing is performed on the nets other than the clock net to perform wiring, and the RC information F1 is extracted.

On the other hand, in step S11, each macro 2, 3
Of the delay models 2M and 3M are created. As shown in FIG. 2C, the delay model 2M of the macro 2 has a buffer logic having the minimum driving capability in the cell group of the library cell description file and the clock terminal 21 in the macro netlist in which only the clock terminal 21 exists. Created by adding 22M. Similarly, a delay model 3M of the macro 3 is created by adding a buffer logic 32M to the clock terminal 31 in the macro netlist.

Next, in step S12, step S11
Using the netlist created in step 2, delay models 2M and 3
A delay model file F2 storing M is created.

In step S4, using the delay model file F3, the clock output terminal 11 and the clock terminal 2 are used.
A top-level delay calculation is performed in which the static timing analysis is performed up to 1, 31 and the delay value of each path is calculated.

In step S5, the delay difference between the clock terminals 21 and 31 is obtained from the result of the top-level delay value calculation in step S4.

Next, in step S6, when laying out the macros 2 and 3, the clock terminals 2 of the macros 2 and 3
Buffer logic 2 added to create delay model for 1, 31
Buffers 22 and 32 of the same capacity corresponding to 2M and 32M
And the buffers 22, 32 added in step S7.
Are arranged near each of the clock terminals 21 and 31 (FIG. 2C).

Next, in step S8, the arrangement in the macro is performed (FIG. 3A). The cell group 23 is a cell group existing in the macro 2 and connected to the output terminal of the buffer added to the clock terminal 21. The cell group 12 is a macro 3
And a cell group connected to the output terminal of the buffer added to the clock terminal 31.

Next, in step S9, clock wiring in the macros 2 and 3 is performed. In step S5, each macro terminal 2
Since the delay difference between the clock terminals 21 and 31 is calculated, the wiring between the clock terminal 21 and the cell group 23 and the wiring between the clock terminal 31 and the cell group 33 are C
TS wiring is performed (FIG. 3B).

In this way, the clock terminal 11 and the cell group 2
3 and the delay between the clock terminal 11 and the cell group 33 become equal, and the clock skew can be reduced.

When the layout of the macros 2 and 3 is completed, the cell group 23 existing in the macro 2 is changed, and when re-layout in the macro 2 is performed, the buffer 22 is added to the clock terminal 21 in the macro. Clock terminal 21
Since the delay value of the upper layer does not change by arranging in the vicinity, it is not necessary to change the top level and the macro 3.

Furthermore, the clock wiring designing method of the present embodiment greatly improves the layout design efficiency of recent highly integrated LSIs.

The number of elements that can be mounted on an LSI becomes enormous,
The function macro is called IP (Intellectual Pro
There is a current situation in which productivity is improved by converting to “party” (intellectual property right) and reusing. To keep (or derive) the superiority of others, new function macros are designed from the ground up, so they are initially treated as black boxes. It changes to gray box and white box as the design progresses.

The white box is data in which the required number of grids and cells can be accurately calculated in a netlist including all necessary functions and characteristics. The black box is data in which only terminal information exists. A gray box is a stage in the transition from a black box to a white box. Since the function macro with high diversion can be estimated in scale and performance from the beginning of design, it starts with a gray box. In other words, even if there is a mismatch during the design of the entire chip, the clock wiring design method of the present embodiment can absorb the mismatch.

Further, since the fluctuation of the delay value due to the capacitance of the adjacent wiring is also taken into consideration, the timing analysis is performed after the layout, the driving capability of the buffer is changed for skew adjustment, and the buffer is added and the timing analysis is performed again. Man-hour and processing time can be reduced.

Lastly, in order to eliminate the fluctuation of the delay value due to the influence of the adjacent wiring capacitance, there is a cost reduction effect such that it is not necessary to use an expensive layer dedicated to clock wiring, for example, six or more metal layers.

For reference on cost reduction, refer to the IEICE, “VLD97-77, IC”
D97-173, CPSY97-66, FTS87-0
4 (1997-10) "L in the sub-quarter micron era
SI design technology ".

Next, a second embodiment of the present invention will be described with reference to FIG. 4, which is a flowchart similar to FIG. 1 in which constituent elements common to FIG. The difference of this embodiment from the first embodiment is that the delay value of the placed macro is extracted from the wiring information F3 of the placed macro instead of the delay model creation step S12, Delay model F2 including the delay value of
A and a delay model creation step S12A for creating the macro A, and instead of the placement step S8 in the macro, the delay time between the clock output terminal of the clock net and the cell group in the placed macro in which the placement and routing has been completed is made equal. An arrangement step S8A in an unarranged macro for arranging a clock output terminal between a cell group in a macro whose arrangement has not been completed.

FIG. 5 is a block diagram showing a second example of the functional block to which the clock wiring characterizing this embodiment is applied, in which the same components as in FIG. Referring to this figure, the functional blocks of the present embodiment shown in this figure are different from the above-described first embodiment in the following points.
In addition to the unplaced macros 2 and 3 common to the first embodiment, a macro 4 which is a placed macro whose placement and wiring has been completed is further provided.

In this embodiment, since the terminal position of the macro 4 is already fixed, the process of determining the terminal position in step S1 is performed only for the macros 2 and 3. Also, since the placement and routing of the macro 4 has been completed and the delay value in the macro 4 has been determined, in step S12A, the delay calculation considering the delay value in the macro 4 extracted from the delay information F3 of the placed macro is performed. And a delay model F2A including the delay value of the macro 4 is created.

Here, the clock output terminal 11 and the macro 4
Since the delay up to the cell group 43 is determined, step S
At 8A, the delay between the clock output terminal 11 and the cell group 23 and the cell group 33 becomes equal to the delay between the clock output terminal 11 and the cell group 43. Clock output terminal 11 and cell group 2
Wiring of each of 3, 33 is performed.

As a result, even if one macro in the functional block has been arranged and wired, the clock terminal 11 and the cell group 2
3 and the cell group 33 and the cell group 43 have equal delay, and skew can be reduced.

As described above, according to the present embodiment, even in the case of a placed macro (placed in a white box and can be treated as a hard macro) in which placement and wiring in a certain macro is completed, the clock net in the placed macro is The skew after the placement and routing is completed can be reduced by making the delay to the cell group connected to the clock net in the unplaced macro coincide with the delay to the cell group connected to the unplaced macro.

Next, a third example of a functional block to which clock wiring is applied, which characterizes the third embodiment of the present invention, will be described with common reference characters / numerals added to components common to FIG. Similarly, referring to FIG. 6 which is shown as a block, the difference between the functional block of the present embodiment shown in this figure and the first embodiment described above is that the clock output terminal 11 and the macro 2,
3 has a buffer 5 inserted between each of the clock terminals 21 and 31.

The distance between the clock output terminal 11 and the clock terminals 21 and 31 of the macro is long, and the driving capability of the clock net output block 1 requires the buffer 2 added in the macro.
2 and 32 cannot be driven, the clock output terminal 11 and the clock terminals 21 and 31 of the macros 2 and 3 respectively.
The buffer 5 capable of sufficiently driving the buffers 22 and 32 is added between the first and second embodiments, so that the top-level delay calculation can be accurately performed as in the first and second embodiments in which the buffer 5 is not added. And skew after placement and routing can be reduced.

Further, even when a plurality of buffers exist between the clock output terminal 11 and the macro clock terminals 21 and 31, the top-level delay calculation can be performed accurately.

Accordingly, the top-level delay difference can be calculated accurately, and skew can be reduced by performing clock wiring in the macro in consideration of the delay difference.

Further, in order to reduce power, even when a cell to which a logic for stopping a clock is input under a preset operating condition is added to a clock net, top-level delay calculation can be performed.

The fourth example of the functional block to which the above-described logic for power reduction which characterizes the fourth embodiment of the present invention is added is shown by adding common reference characters / numerals to components common to FIG. Similarly, referring to FIG. 7 indicated by a block, the difference between the present embodiment shown in FIG. 7 and the first embodiment is that the preset operation conditions are set, and in this example, the operation of the macro 2 is performed. A control circuit 9 for reducing the power under the above-mentioned operating conditions by fixing the clock signal supplied to the macro 2 to 1 or 0 when stopping, and a logic circuit 6 controlled by the control circuit 9 That is, it is added to the input side of the clock terminal 21 of the macro 2.

In this example, an AND circuit is used as the logic circuit 6, and when the control circuit 9 outputs 0, the logic circuit 6 stops the operation of the macro 2 by fixing the clock supplied to the clock terminal 21 to 0. Let it.

The operation of the macro 3 may be stopped by providing the logic circuit 6 on the input side of the clock terminal 31 of the macro 3.
Alternatively, the operation of both macros 2 and 3 may be controlled by providing the logic circuit 6 at both inputs of the clock terminals 21 and 31.

In any case, the top-level delay calculation can be performed accurately.

Therefore, the top-level delay difference can be accurately calculated, and skew can be reduced by performing clock wiring in the macro in consideration of the delay difference.

[0088]

As described above, according to the clock wiring designing method of the present invention, a macro delay model is created in advance,
By performing top-level delay calculation using this delay model, it becomes possible to accurately calculate the clock delay of each of a plurality of clock supply target macros in a functional block to be designed. Has the effect that the clock skew between the two can be reduced.

Further, when the clock wiring at the top level is performed with the equal wiring length, it is possible to take into account the delay variation due to the capacitance of the adjacent wiring, and there is an effect that the clock skew between macros can be accurately calculated.

Also, when wiring is not performed with an equal wiring length,
Similarly, since the clock skew between the macros can be accurately calculated, the clock skew between the macros at the top level becomes an accurate value, and the clock skew after executing the CTS in the macro can be reduced.

Even when a layout change in a macro of a part of macros occurs, a buffer having the same driving capability corresponding to the buffer logic added when the delay model was created is added to the clock terminal in the macro, and the layout is changed. Since the delay value in the top-level and unchanged macros does not change by arranging them near the clock terminal when performing this, there is no need to change the layout in these top-level and unchanged macros, and the layout is re-designed. There is also an effect that the processing time to be performed can be reduced.

Further, the clock wiring designing method of the present embodiment has an effect that the layout design efficiency of a recent highly integrated LSI can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a first embodiment of a clock wiring designing method according to the present invention.

FIG. 2 is a block diagram schematically illustrating a first example of a functional block to be applied, determination of a terminal position, and modeling of a macro for explaining an example of an operation in a clock wiring designing method according to the present embodiment; It is.

FIG. 3 is a block diagram schematically showing a state after layout in a macro of a first functional block for explaining an example of an operation in a clock wiring designing method according to the present embodiment;

FIG. 4 is a flowchart showing a second embodiment of the clock wiring designing method of the present invention.

FIG. 5 is a block diagram schematically showing a functional block of a second example to which the present embodiment is characterized;

FIG. 6 is a block diagram schematically showing a functional block of a third example to be applied which characterizes a third embodiment of the clock wiring designing method according to the present invention;

FIG. 7 is a block diagram schematically showing a functional block of a fourth example to which the fourth embodiment of the clock wiring designing method according to the present invention is characterized;

FIG. 8 is a block diagram schematically illustrating a function block to be applied, a terminal position determination, and macro modeling for explaining a conventional first clock wiring design method.

FIG. 9 is a flowchart illustrating an example of a conventional second clock wiring design method.

[Explanation of symbols]

 Reference Signs List 1 clock net output block 2, 3, 4 macro 2M, 3M delay model 6 logic circuit 7, 8 straight line 9 control circuit 11 output terminal 21, 31, 201, 302 clock terminal 22M, 32M buffer logic 5, 22, 32 buffer 23 , 33, 43 Cell group 25, 35 Center F1, F101, F102 RC information F2 Delay model (file) F3 Delay information of placed macro

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) G06F 17/50 668 G06F 17/50 668M 668X H01L 21/82 B H01L 27/04 C 21/822 27/04 DF term (reference) 5B046 AA08 BA06 JA03 KA06 5F038 CD06 CD08 CD09 CD12 CD13 EZ09 EZ20 5F064 AA06 BB07 BB26 DD02 DD04 DD25 EE02 EE03 EE08 EE42 EE43 EE47 EE54 HH06 HH12

Claims (10)

[Claims] 1. A hierarchical design method in which functional blocks are divided into two hierarchies, that is, a top level which is an upper hierarchy and a macro which is a lower hierarchy, and the layout is individually performed in each of the top level and the macro. In a clock wiring design method in a layout design of a top-down LSI in which a top-level layout is first used, a delay model of the macro is created in advance, and the top-level delay is calculated using the delay model. A method of designing a clock wiring, wherein the clock skew between each of a plurality of macros to be supplied with clocks in a functional block to be designed is reduced. 2. A delay model of the macro is created by adding buffer logic of a library cell description file to a clock terminal in the netlist in the macro, and at the time of layout of the macro, the same logic corresponding to the buffer logic is created. 2. The method according to claim 1, wherein a buffer having a driving capability is arranged near the clock terminal. 3. A hierarchical design method in which functional blocks are hierarchized by being divided into two hierarchies, that is, a top level which is an upper hierarchy and a macro which is a lower hierarchy, and layouts in the top level and in the macro are individually performed. In the method of designing a clock wiring in a layout design of a top-down type LSI in which a top-level layout is firstly used, a clock of each of unplaced first and second macros, each of which is not arranged and wired in a macro, is used. A clock terminal determining step of setting a clock terminal receiving the supply of the clock signal; and a schematic wiring between the clock output terminal and each of the first and second clock terminals set in the macro clock terminal determining step. Determining a wiring route to determine a wiring route to be performed; and determining the wiring route. Top-level wiring for performing wiring between the clock output terminal and each of the first and second clock terminals based on the wiring path determined in step 1, and extracting RC information that is information on resistance and capacitance of each wiring A delay model creating step of creating a delay model for each of the first and second macros; and a clock output terminal and each of the first and second clock terminals based on the RC information and the delay model. A top-level delay calculating step of performing static timing analysis between the first and second macros and calculating first and second delay values that are clock delay values between the clock output terminal and the first and second macros, respectively. Calculating a delay difference between a clock output terminal and each of the first and second macros from the first and second delay values; A buffer arranging step of arranging a buffer having the same driving capability corresponding to a buffer logic near each of the first and second clock terminals during layout in each of the first and second macros; An intra-macro arranging step of arranging each of the first and second macros; and a clock wiring in the macro for performing clock wiring by a clock tree synthesis method in each of the first and second macros in consideration of the clock delay difference. And a method for designing a clock wiring. 4. The method according to claim 1, wherein the step of determining the clock terminal of the macro comprises the steps of:
First and second straight lines connecting the centers of the macros of the first and second macros are drawn, and first and second intersections between the first and second straight lines and the periphery of each of the first and second macros are drawn. 4. The clock wiring according to claim 3, wherein an intersection is determined, and first and second clock terminals of each of the first and second macros are set at each of the first and second intersections. Design method. 5. The delay model creating step includes adding buffer logic of a group of cells in a library cell description file to a clock terminal in a macro netlist of the first and second macros. 4. The method according to claim 3, wherein a delay model is created for each of the two macros. 6. A clock net having an output block provided with a clock output terminal for the clock output, wherein the functional block includes a first and a second clock terminal for the clock input. 4. The clock wiring design method according to claim 3, further comprising: a second macro; and a clock wiring from the output block as the top-level wiring to each of the first and second macros. 7. A hierarchical design method in which functional blocks are hierarchized by being divided into two hierarchies, a top level as an upper hierarchy and a macro as a lower hierarchy, and a layout in each of the top level and in the macro is individually performed. In the clock wiring design method in the layout design of a top-down type LSI in which the top-level layout is firstly used, the first and second macros and the macros in the macros which are not arranged and wired in the macros are respectively arranged. A clock terminal determining step of setting a clock terminal to receive a clock supplied from each of the arranged and routed third macros; and a step of determining the clock output terminal and the macro clock terminal determining step. , The second and third clock terminals, and roughly determine the wiring path by performing the wiring. A wiring path determining step; and wiring between the clock output terminal and each of the first and second clock terminals based on the wiring path determined in the wiring path determining step, and a resistance and a capacitance of each wiring. A top-level wiring step of extracting RC information, which is information of the first macro and a delay model of each of the first and second macros, and a delay value of the third macro from the wiring information of the third macro A delay model creating step of creating a delay model including the delay value of the third macro, and a clock output terminal and the first and second clock terminals based on the RC information and the delay model. A static timing analysis between the first and second macros is performed, and first and second delays, which are clock delay values between the clock output terminal and the first and second macros, respectively, are performed. A top-level delay calculation step for calculating respective values; a delay difference calculation step for calculating a clock delay difference between the clock output terminal and each of the first and second macros from the first and second delay values; A buffer arranging step of arranging a buffer having the same driving capability corresponding to a buffer logic near each of the first and second clock terminals during layout in each of the first and second macros; A macro arranging step of arranging each of the first and second macros so as to be equal to a delay value between a cell group in the macro and the clock output terminal; A clock wiring step for performing clock wiring by a clock tree synthesizing method in each of the first and second macros. A method of designing a click wiring. 8. A clock net having an output block including a clock output terminal for the clock output, and the first block including each of the first and second clock terminals for the clock input. And a third macro already placed and routed in a macro having a second macro and a third clock terminal; and the first, second and third macros from the output block which is the top level wiring. 8. The clock wiring design method according to claim 7, further comprising a clock wiring for each macro. 9. A first and a second clock terminal added to each of the first and second clock terminals inserted between the clock output terminal and the first and second clock terminals, wherein the clock wiring is provided. 9. The clock wiring design method according to claim 6, further comprising a third buffer for driving the buffer. 10. A clock net having an output block having a clock output terminal for the clock output, and the first functional block having each of the first and second clock terminals for the clock input. And a second macro, a clock wiring from the output block, which is the top-level wiring, to each of the first and second macros, and a control circuit for outputting a control signal in accordance with setting of a predetermined operating condition Wherein the clock wiring comprises a logic circuit for stopping the passage of the clock in response to the supply of the control signal to one or both input sides of the first and second macros. The clock wiring design method according to claim 3 or 8, wherein: