JPH1065106A - Clock distribution circuit for integrated circuits - Google Patents

Abstract

(57) [PROBLEMS] To suppress clock skew and suppress occurrence of electromigration in an integrated circuit laid out using standard cells. SOLUTION: In a block 1 in which a plurality of cell rows ROW are arranged in cascade, a plurality of power supply bridge cells 3 are arranged in a vertical direction. A first buffer 5 to which a clock signal is input is arranged near the power supply bridge cell. The first buffer drives a second buffer 6 located below the same power bridge cell. As the first buffer, cells according to the number of ROWs are selected. As the second buffer, cells according to the number of flip-flops 4 to be connected are selected.
A dummy load for the second buffer is arranged in the power supply bridge cell having the short interval L2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock distribution circuit in an integrated circuit.

[0002]

2. Description of the Related Art In a conventional integrated circuit, when designing a clock, clock skew has been suppressed by driving n flip-flops with one clock buffer.

[0003]

However, in recent years,
Since the clock frequency of a processor has increased dramatically, it has become difficult to suppress clock skew. Advances in semiconductor technology have reduced clock delays on a gate-by-gate basis, but the rate of reduction in propagation delays caused by parasitic capacitance and resistance in interconnects is small. Therefore, the relative weight of the propagation delay in the wiring is relatively increased with respect to the entire delay.

In such a situation, when designing a clock, by driving n flip-flops with one clock buffer as in the prior art, the clock skew is suppressed and the clock skew corresponding to the frequency is reduced. It was difficult to realize. Further, in an integrated circuit, a problem such as electromigration of a power supply wiring has occurred. This problem is particularly problematic in power supply wiring in clock circuits that constantly consume current.

[0005] The present invention relates to an integrated circuit block laid out by arranging and wiring standard cells.
An object of the present invention is to suppress clock skew inside a block and to suppress clock skew between blocks. Another object of the present invention is to suppress the occurrence of electromigration in blocks of an integrated circuit laid out by arranging and wiring standard cells.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to achieve the above object. In the present invention, a standard cell is laid out by arranging and wiring,
In a clock distribution circuit of an integrated circuit formed by arranging a plurality of cell columns in a cascade and arranging a plurality of power bridge cells in a vertical direction with respect to the cell columns, a power supply bridge is provided at an uppermost or lowermost stage of the plurality of cell columns A first buffer to which a clock signal is input is arranged near the cell, and a second buffer is arranged below the power bridge cell in each cell column.

In order to drive each second buffer by the first buffer, an output of the first buffer is connected to an input of a second buffer arranged in one column arranged close to the first buffer. Are connected by the first wiring, and the clock terminals of the flip-flops which are in the same cell column as the second buffers and exist up to the next second buffer are driven. A second wiring connects between the output and the flip-flop.

With the above configuration, the clock skew is suppressed and the occurrence of electromigration is suppressed. Further, in the present invention, the clock skew between the blocks can be suppressed by using, as the first buffer, a buffer having a drive capacity corresponding to the number of stages of the cell row of the block.

In the present invention, by connecting a gate for load adjustment as a load to the second buffers in accordance with the number of flip-flops to be driven, the number of flip-flops driven by each second buffer is reduced. The resulting clock skew can be suppressed. In the present invention, the power supply bridge cells are arranged at specified intervals, but the power supply bridge cells may be arranged at intervals shorter than the interval specified by the block size. Between the shortly spaced power bridge cells, the second buffer
A gate for load adjustment corresponding to the short interval is connected as a load. As a result, it is possible to suppress the occurrence of clock skew due to the difference in the power supply bridge cell interval.

[0010] In the present invention, the first wiring and the second wiring are shielded by a power supply line and wired, whereby clock skew generated due to the relationship with the power supply line can be suppressed. It can be strong against noise such as crosstalk.

[0011]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an integrated circuit. In FIG. 1, reference numeral 1 denotes a block laid out by arranging and wiring standard cells. A plurality of blocks as shown in FIG. 1 are arranged on the integrated circuit. RO
W is a cell row in which a plurality of cells are arranged in a row. In the illustrated example, the cell rows ROW are provided in five stages of ROW0 to ROW4.

Reference numeral 3 denotes a power bridge cell, and each cell row RO
W are arranged at equal intervals L1 in the vertical direction with respect to W. The interval L1 is, for example, 400 μm. However, the space L2 between the power supply bridge cell 3 on the right end and the power supply bridge cell 3 on the left side thereof may be shortened depending on the horizontal dimension of the block 1. The interval L2 is, for example, 200 μm.

Reference numeral 4 denotes a flip-flop arranged on the cell column 2. Reference numeral 5 denotes a first buffer, which is arranged in the uppermost cell row ROW0 for each power supply bridge cell 3 in close proximity to the power supply bridge cell 3. The first buffer 5 may be arranged in the lowermost cell row ROW4, or may be arranged in the uppermost and lowermost cell rows ROW0 and ROW4.
It can also be located at W4.

Reference numeral 6 denotes a second buffer, which is arranged below each power supply bridge cell 3 in each cell column 2. 7 is
This is a dummy load disposed below the power supply bridge cell 3 at the right end. FIG. 2 shows a circuit of the block 1 in FIG. A clock supplied from the outside is supplied to the first buffer 5 from the input terminals CKIN1 to CKINn. First buffer 5
Drives the second buffer 6 in one column arranged below the adjacent power supply bridge cell 3. Reference numeral 8 denotes a first wiring connecting between the first buffer 5 and the second buffer 6. The second buffer 6 is on the same cell row ROW,
The clock terminal CK of the flip-flop 4 existing up to the second buffer 6 in the next vertical column is driven. Reference numeral 9 denotes a second wiring connecting between the second buffer 6 and the flip-flop 4.

Here, the first buffer 5 selects and uses a cell having a drive capacity corresponding to the number of ROW stages. This is to suppress the clock skew generated between other blocks. FIG. 3 shows an example of cell selection. 3A shows the case where the number of ROW stages is 1 to 2, FIG. 3B shows the case where the number of ROW stages is 3 to 5, and FIG.
In the case of 10, (d) is when the number of ROW stages is 11 to 19,
(E) shows the case where the number of ROW stages is 20 to 28. (B)
(E) shows a state in which a buffer having a drive capacity corresponding to the number of ROW stages is used. In (a), the delay amount is adjusted by connecting a plurality of buffers having the minimum drive capability in series.

If the number of rows is 29 or more, the uppermost cell row ROW0 of the vertically arranged cell rows is set.
And the first buffer 5 in both the lowermost cell row ROW4.
Place. In this case, each first buffer 5 selects a cell based on the criteria shown in FIG. By selecting the cells of the first buffer in this way, it is possible to equalize the amount of delay caused by the first buffer in each block 1 arranged on the same integrated circuit. Therefore, the clock skew by the first buffer can be reduced.

As the second buffer, a cell including a gate (dummy load) for load adjustment according to the number of flip-flops 4 to be driven is used. This suppresses clock skew generated according to the number of flip-flops 4 to be driven. One example of the selection criteria is shown in FIG. FIG.
(A) is a case where there are eight flip-flops and does not include a dummy load. (B) to (i) increase the capacity of the dummy load as the number of flip-flops to be driven decreases. (B) shows a case where there are seven flip-flops.
(C) is a case where there are six flip-flops, (d) is a case where there are five flip-flops, (e) is a case where there are four flip-flops, (f) is a case where there are three flip-flops, and (g) ) Shows the case where there are two flip-flops, (h) shows the case where there is one flip-flop, and (i) shows the case where there is no flip-flop.

In the case of the second buffer 6, it is necessary to use a load adjusting cell depending on the distance between the power supply bridge cells 3. Although the interval L1 between the power supply bridge cells 3 is specified to be equal, depending on the horizontal dimension of the block 1, the interval between the power supply bridge cell 3 on the right end and the power supply bridge cell 3 on the left side thereof (L2 in FIG. 1). , May be shorter than other intervals. Therefore, the clock skew to the clock terminal 7 of the flip-flop 4 within the short interval L2 increases.

In order to avoid this, a dummy load 7 corresponding to the distance between the rightmost power supply bridge cell 3 and the leftmost power supply bridge cell 3 is arranged below the rightmost power supply bridge cell 3 to provide a second load. Buffer load. FIG. 5 shows an example of the criteria for selecting the dummy load. FIG. 5A shows that the interval is 2
In the case of 00 to 300 μm, (b) shows an interval of 100 to 2
In the case of 00 μm, (c) shows a case where the interval is up to 100 μm, and a dummy load having a larger capacity is used as the interval becomes shorter. 4 and 5 use a MOS transistor as a capacitor C.

This embodiment further has means for suppressing clock skew due to clock wiring. In this example, the clock wiring is shielded and wired by the power supply line. FIG. 6 is a cross-sectional view taken along the line AA of FIG. 2 and shows a shield configuration of the first wiring 8 connecting the first buffer 5 and the second buffer. In FIG. 6, illustration of an insulating layer and the like is omitted for easy understanding. In FIG.
11 is a MOS transistor, 12 is a first layer wiring, 13
Is a second layer wiring, and 14 is a third layer wiring. The first buffer 5 is provided between the power supply lines 15 and 16 in the second layer wiring.
A clock wiring 8 is arranged between the first buffer 6 and the second buffer 6.

FIG. 7 is a cross-sectional view taken along the line BB of FIG. 2, and shows the shield configuration of the second wiring 9 connecting the second buffer 6 and the flip-flop 4. FIG.
In the figure, 21 is a MOS transistor, 22 is a first-layer wiring, 23 is a second-layer wiring, and 24 is a third-layer wiring. The wiring of the third layer includes the second wiring between the power supply lines 25 and 26.
The clock wiring 9 between the buffer 5 and the flip-flop 4 is arranged.

The clock wirings 8 and 9 are connected to the same layers 13 and 23
And runs parallel to the power supply lines 15, 16, 25, 26, so that the capacitance between the power supply lines 15, 16, 25, 26 becomes constant. This reduces clock skew due to wiring. The clock wires 8 and 9 are connected to the power supply lines 15 and 1
6, 25, 26, it is strong against noise such as crosstalk.

Next, the clock cell of the second buffer 6 is used in common with the power bridge cell 3. Therefore, the clock cell that consumes the most current among the standard cells in the block is placed immediately below the power bridge cell. Therefore, the occurrence of electromigration can be suppressed. An automatic placement and routing system for realizing the present clock distribution circuit will be described with reference to FIG.

In step S1, a net list storing logic information for design is prepared. In step S2, gates such as flip-flops are arranged. Step S
At 3, the number of power supply bridge cells is determined. Step S
At 4, the netlist is updated by adding the first and second buffers according to the arrangement of the power bridge cells. At this time, the drive capability of the first buffer is determined by the number of ROW stages as described above with reference to FIG.

In steps S5 to S8, placement, layout improvement, and wiring are determined in the same manner as in a normal design. Step S
At 9, a dummy load is added as described above with reference to FIGS. 4 and 5, and layout data is obtained at step S10. Since a uniform clock skew can be realized by the automatic placement and routing system, a designer can design a layout without being conscious of clock skew.

[0026]

According to the present invention, in a block of an integrated circuit laid out by arranging and wiring standard cells, it is possible to suppress a clock skew inside a block and a clock skew between blocks. It becomes possible. Further, according to the present invention, it is possible to suppress the occurrence of electromigration in blocks of an integrated circuit laid out by arranging and wiring standard cells.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a clock distribution circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of the clock distribution circuit of FIG. 1;

FIG. 3 is a diagram showing an example of criteria for selecting a cell of a first buffer in FIGS. 1 and 2;

FIG. 4 is a diagram showing an example of a criterion for selecting a cell of a second buffer in FIGS. 1 and 2;

FIG. 5 is a diagram showing an example of a criterion for selecting a cell of a second buffer at the right end in FIGS.

FIG. 6 is a sectional view taken along line AA of FIG. 2;

FIG. 7 is a sectional view taken along line BB of FIG. 2;

FIG. 8 is a flowchart showing an automatic design system of the clock distribution circuit of FIGS.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Block 3 ... Power bridge cell 4 ... Flip-flop 5 ... First buffer 6 ... Second buffer 7 ... Dummy load 8 ... First wiring 9 ... Second wiring 11 and 21 ... MOS transistors 12,22 ... 1st layer wiring 13,23 ... 2nd layer wiring 14,24 ... 3rd layer wiring 15,16,25,26 ... power line CKIN ... clock terminal ROW ... cell column

Claims (6)

[Claims] 1. A clock of an integrated circuit formed by arranging and arranging standard cells, arranging a plurality of cell columns in a column, and arranging a plurality of power supply bridge cells in a vertical direction with respect to the cell columns. In the distribution circuit, a first buffer, which is arranged in close proximity to the power supply bridge cell at an uppermost stage or a lowermost stage of the plurality of cell columns and receives a clock signal, is disposed below the power supply bridge cell in each of the cell columns. The second buffer arranged in the first buffer and the second buffer are driven by the first buffer, the output of the first buffer and the first buffer arranged in close proximity to the first buffer. A first wiring connecting between the inputs of the second buffers of the column, and a first wiring of each flip-flop in the same cell column as the second buffers and existing up to the next second buffer; A clock distribution circuit, comprising: a second wiring connecting between an output of a second buffer and the flip-flop for each cell column to drive a clock terminal. 2. The clock distribution circuit according to claim 1, wherein the first buffer has a drive capacity corresponding to the number of stages of the cell row. 3. The clock distribution circuit according to claim 1, wherein the second buffer is connected as a load with a gate for load adjustment according to the number of flip-flops to be driven. 4. The power supply bridge cells are arranged at a specified interval, and a second buffer between the power supply bridge cells arranged at a shorter interval than the specified interval is:
2. The clock distribution circuit according to claim 1, wherein a gate for load adjustment according to the short interval is connected as a load. 5. The clock distribution circuit according to claim 1, wherein said first wiring is wired by being shielded by a power supply line. 6. The clock distribution circuit according to claim 1, wherein said second wiring is wired by being shielded by a power supply line.