JP2003338546A - Method for designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the retracing of designing owing to the alteration of a logic or the like upon optimizing timing in a semiconductor integrated circuit, and hence prevent a design period from extending. <P>SOLUTION: There are provided: a cell disposition process for disposing a logic cell based upon circuit design information; a wiring process 102 for wiring among terminals of the logic cell; a delay time calculation process 103 for calculating the wiring delay time of a wired signal line; a timing restriction violation extraction process 104 for extracting a signal line which cause violation against restriction for timing on the basis of the result of the delay time calculation process 103; and a timing restriction violation optimization process 105 for solving the violation against the restriction of the timing of a signal line extracted by the timing restriction violation extraction process 104. In the timing restriction violation optimization process 105, there is solved the violation against the restriction of timing by increasing and decreasing a capacity between wirings by adjusting a wiring interval between the signal line which causes the violation against the restriction of timing and another signal line adjoining the former signal line. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a semiconductor integrated circuit device, and more particularly to a technique for optimizing a semiconductor integrated circuit device for satisfying delay time design constraints.

[0002]

2. Description of the Related Art Timing optimization is performed everywhere in the design process of a semiconductor integrated circuit device. RT as an optimization method
L modification, replacement of logic cells, addition of logic cells are mainly performed. However, such modification causes design retrogression such as re-logic synthesis and re-function verification, which requires man-hours. Is coming.

[0003]

As described above, the timing optimization in the conventional design method has a problem in that a backtracking of the design occurs, the man-hour loss is large, and the design period is increased.

The present invention has been made to solve the above conventional problems, and an object of the present invention is to provide a method for designing a semiconductor integrated circuit device which can suppress the backtracking of the design and prevent an increase in the design period. To do.

[0005]

According to a first aspect of the present invention, there is provided a method for designing a semiconductor integrated circuit device comprising: a cell arranging step for arranging a plurality of logic cells based on circuit design information; Wiring process, wiring delay time calculation process for calculating the wiring delay time of the routed signal line, and timing constraint violation for extracting the signal line causing the timing constraint violation based on the result of the delay time calculation process Extraction step and timing constraint violation optimization step for eliminating timing constraint violation by increasing or decreasing the inter-wiring capacitance between the signal line extracted by the timing constraint violation extraction step and another signal line adjacent to this signal line It includes and.

According to the method of the first aspect, the violation of the timing constraint is eliminated by increasing or decreasing the inter-wiring capacitance between the signal line in which the timing constraint is violated and another signal line adjacent thereto. Therefore, for example, it is possible to increase or decrease the inter-wiring capacitance by adjusting the wiring interval. In this way, by only correcting the wiring, the timing constraint violation is eliminated and the circuit is optimized. As a result, there is no logical change and the like, it is possible to suppress the backtracking of the design, reduce the verification man-hours, and prevent an increase in the design period.

According to a second aspect of the present invention, there is provided a method of designing a semiconductor integrated circuit device according to the first aspect, wherein the timing constraint violation optimizing step causes a timing constraint violation. It is characterized in that the inter-wiring capacitance is increased by narrowing the wiring interval between the existing signal line and another signal line adjacent thereto.

According to the method of claim 2, by narrowing the wiring interval between the signal line in which the timing constraint is violated and another signal line adjacent thereto, the inter-wiring capacitance is increased and the timing constraint is violated. I am trying to eliminate.
In this way, by only correcting the wiring and solving the timing constraint violation and optimizing the circuit, it is possible to reduce the number of verification steps by suppressing the backtracking of the design without logical changes. It is possible to prevent the period from increasing.

According to a third aspect of the present invention, there is provided a method for designing a semiconductor integrated circuit device according to the first aspect, wherein the timing constraint violation optimizing step causes a timing constraint violation. It is characterized in that the inter-wiring capacitance is reduced by widening the wiring distance between the existing signal line and another signal line adjacent thereto.

According to the method of claim 3, by widening the wiring interval between the signal line in which the timing constraint is violated and another signal line adjacent thereto, the inter-wiring capacitance is reduced and the timing constraint is violated. I am trying to eliminate.
In this way, by only correcting the wiring and solving the timing constraint violation and optimizing the circuit, it is possible to suppress the backtracking of the design and reduce the verification man-hour without logical changes. It is possible to prevent the period from increasing.

Further, according to a fourth aspect of the present invention, there is provided a method for designing a semiconductor integrated circuit device, comprising: a cell arranging step for arranging a plurality of logic cells based on circuit design information; and a wiring for wiring terminals of the plurality of logic cells. A step, a delay time calculating step of calculating a wiring delay time of the wired signal line, a timing constraint violation extracting step of extracting a signal line causing a timing constraint violation based on the result of the delay time calculating step, A timing constraint violation optimizing step of eliminating a timing constraint violation by arranging a dummy signal line independent of the circuit operation adjacent to the signal line extracted by the timing constraint violation extraction step.

According to the method of claim 4, the dummy signal line is arranged adjacent to the signal line in which the timing constraint is violated, so that the capacitance of the signal line in which the timing constraint is violated is held. I am trying to increase the number and solve the timing constraint violation. In this way, by adding a dummy signal line that is independent of the circuit operation, the timing constraint violation is resolved and the circuit is optimized, so that there is no logical change, the backtracking of the design is suppressed, and the verification man-hour is reduced. This makes it possible to prevent an increase in design period.

According to a fifth aspect of the present invention, there is provided a method for designing a semiconductor integrated circuit device, including a cell arranging step of arranging a plurality of logic cells based on circuit design information, and a wiring for wiring terminals of the plurality of logic cells. A step, a delay time calculating step of calculating a wiring delay time of the wired signal line, a timing constraint violation extracting step of extracting a signal line causing a timing constraint violation based on the result of the delay time calculating step, A first signal line is extracted between the first signal line extracted by the timing constraint violation extraction step and the second signal line adjacent to this signal line.
The first signal by arranging an insulating wire along the signal line of (1) and using an insulating material different from the insulating layer to be provided between the first signal line and the second signal line. And a timing constraint violation optimizing step of eliminating the timing constraint violation by increasing or decreasing the inter-wiring capacitance between the line and the second signal line as compared with the case where the insulated line is not arranged.

According to the method of claim 5, between the first signal line in which the timing constraint is violated and the second signal line adjacent thereto, insulation different from the insulating layer provided therebetween is provided. By arranging the insulated wire made of material,
The inter-wiring capacitance between the first signal line and the second signal line can be finely increased / decreased, and the violation of the timing constraint is solved. By eliminating the timing constraint violation and optimizing the circuit just by adding the insulation line in this way, there is no logical change etc.
It is possible to reduce the number of verification steps and prevent an increase in design period.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a flowchart showing a method for designing a semiconductor integrated circuit device according to this embodiment.

The design method according to the present embodiment includes a cell placement step 10 for placing a logic cell based on the circuit design information.
1 and a wiring step 102 for wiring between the terminals of the logic cell,
A delay time calculating step 103 for calculating a wiring delay time of the wired signal line, and a timing constraint violation extracting step 104 for extracting a signal line causing a timing constraint violation based on the result of the delay time calculating step 103. A timing constraint violation optimizing step 105 for eliminating the timing constraint violation of the signal line extracted by the timing constraint violation extracting step 107.

The above steps will be described in detail below.

FIG. 2 shows an example of a state in which logic cells are placed in the logic cell placement step 101 and wiring between terminals of the logic cell is completed in the wiring step 102, and is a top view of the wiring seen from above.

Delay time calculation step 1 based on this wiring information
As a result of calculating the delay time by 03, it is assumed that the signal line 201 of FIG. 2 is extracted as the signal line in which the timing constraint violation has occurred in the timing constraint violation extraction step 104. The signal line 202 is a signal line horizontally adjacent to the signal line 201. Reference numeral 203 indicates a via hole connected to a terminal (not shown) of the logic cell.

The timing constraint violation here is an error relating to setup and hold times. The setup error is an error that cannot secure enough time to hold the data before the clock signal change, and the hold time error is that the data signal propagates faster than the clock signal change and latches the data correctly. It refers to an error that cannot secure enough time to do so. In either case, the error can be avoided by controlling the wiring delay time of the data signal or the clock signal.

For example, it is assumed that timing constraint violation occurs in the circuit shown in FIG. In FIG. 9, 90
1, 903 and 904 are registers, and 902 is a logic cell. Further, reference numerals 905 and 906 denote signal lines, which are assumed to be wired adjacent to each other in terms of layout.
5 is 201 in FIG. 2 or 5 in FIG. 5 described later.
The signal line 906 corresponds to the signal line 01 in FIG.
02 or a signal line 502 in FIG. 5 described later.

Here, from the register 901 to the logic cell 90
It is assumed that a timing constraint violation has occurred in the path to the register 903 via 2. If this timing constraint violation is a setup error, it is necessary to adjust the delay time of the path earlier, and if it is a hold time error, it is necessary to adjust the delay time. As the adjusting method, for example, by adjusting the wiring interval between the signal lines 905 and 906, the wiring capacitance can be changed and the delay time can be adjusted. FIG. 10 is a timing chart of the circuit of FIG. 9 in which a hold time error has occurred, and FIG. 11 is a timing chart after the delay time is adjusted.

Considering the wiring delay time using a linear model as an example, the wiring delay time is expressed by the following equation: wiring delay time = wiring resistance × (total pin capacitance + total wiring capacitance). It

From this, it is possible to increase or decrease the wiring delay time by increasing or decreasing the capacitance, and as a result, it is possible to eliminate the timing constraint violation.

A specific example will be shown below.

The first example will be described with reference to FIGS. 2 and 3.
FIG. 3 shows an example of a state in which the timing constraint violation is eliminated by adjusting the wiring interval from the state of FIG. 2 by the timing constraint violation optimization step 105. Signal line 20 of FIG.
The wiring interval with the signal line 202 adjacent to 1 is partially narrowed to increase the wiring capacitance. A signal line 301 corresponds to the signal line 201 in which the timing constraint violation has occurred. Reference numeral 302 is an adjustment of the wiring route of the signal line 202 adjacent to the signal line 201. 303
Is a via hole and corresponds to the via hole 203.

A second example will be described with reference to FIGS. 2 and 4. Similar to FIG. 3, FIG. 4 shows an example of the timing constraint violation optimizing step 105 in which the wiring interval is adjusted from the state of FIG. 2 to eliminate the timing constraint violation.
Unlike the case of FIG. 3, the wiring interval between the signal line 202 adjacent to the signal line 201 of FIG. 2 is partially widened, and the inter-wiring capacitance is reduced. A signal line 401 corresponds to the signal line 201 in which the timing constraint violation has occurred. Reference numeral 402 denotes a signal line 202 which is adjacent to the signal line 201.
The wiring route of is adjusted. A via hole 403 corresponds to the via hole 203.

As described above, according to the first and second examples, the signal line 201 in which the timing constraint is violated.
And the signal line 202 adjacent to this in the horizontal direction is narrowed or widened to adjust the wiring interval to increase or decrease the inter-wiring capacitance, thereby adjusting the signal propagation speed and eliminating the timing constraint violation. I am trying to do it. In this way, by only correcting the wiring and solving the timing constraint violation and optimizing the circuit, it is possible to reduce the number of verification steps by suppressing the backtracking of the design without logical changes. It is possible to prevent the period from increasing.

Next, a third example will be described with reference to FIGS. 5 and 6.

FIG. 5 shows an example of a state in which logic cells are arranged in the logic cell arranging step 101 and wiring between terminals of the logic cell is completed in the wiring step 102, and is a side view of the wiring as viewed from the side. As a result of calculating the delay time in the delay time calculating step 103 based on this wiring information, it is assumed that the signal line 501 is extracted as the signal line in which the timing constraint violation occurs in the timing constraint violation extracting step 104. The signal line 502 is a signal line adjacent to the signal line 501 in the vertical direction. Reference numeral 503 is a via hole connected to a terminal (not shown) of the logic cell.

FIG. 6 is a timing constraint violation optimization step 10.
5 shows an example of a state in which the wiring interval is adjusted from the state of FIG. 5 and the timing constraint violation is eliminated. The wiring interval between the signal line 501 and the signal line 502 adjacent to the signal line 501 is partially narrowed to increase the inter-wiring capacitance. Reference numeral 601 denotes a signal line, and the signal line 5 in which the timing constraint violation has occurred
Corresponds to 01. Further, reference numeral 602 is an adjustment of the wiring route of the signal line 502 adjacent to the signal line 501.
A via hole 603 corresponds to the via hole 503.

A fourth example will be described with reference to FIGS. 5 and 7. 7 is similar to FIG. 6, the wiring interval is adjusted from the state of FIG. 5 by the timing constraint violation optimization step 105,
It shows an example of a state in which a timing constraint violation is resolved. The wiring interval between the signal line 501 and the signal line 502 adjacent to the signal line 501 is partially widened to reduce the inter-wiring capacitance. 70
Reference numeral 1 represents a signal line, which corresponds to the signal line 501 in which the timing constraint violation has occurred. 702 is a signal line 501
The wiring path of the signal line 502 that was adjacent to is adjusted. A via hole 703 corresponds to the via hole 503.

According to the above third and fourth examples,
Propagation of signals by narrowing or widening the wiring interval between the signal line 501 causing the timing constraint violation and the signal line 502 vertically adjacent to the signal line 501 to adjust the wiring interval to increase or decrease the inter-wiring capacitance. The speed is adjusted to eliminate the timing constraint violation. Also in this case, the first and second
Similar to the example, by only correcting the wiring and solving the timing constraint violation and optimizing the circuit, there is no logical change, it is possible to suppress the backtracking of the design and reduce the verification man-hours. The design period can be prevented from increasing.

Next, a fifth example will be described with reference to FIGS. 2 and 8. FIG. 8 shows an example of a state in which the timing constraint violation is eliminated from the state of FIG. 2 by the timing constraint violation optimization step 105. A signal line 801 corresponds to the signal line 201 in which the timing constraint violation has occurred. 80
2 corresponds to the signal line 202 adjacent to the signal line 201.

In this example, in order to eliminate the timing constraint violation of the signal line 801, the dummy wiring 803 is arranged adjacent to the signal line 801. The dummy wiring 803 is independent of the operation of the circuit. The dummy wiring 803 is made of the same material as the signal lines 801 and 802. With this wiring, the inter-wiring capacitance with the dummy wiring 803 is added to the signal line 801, and as a result, the capacitance of the signal line 801 can be increased, the signal propagation speed is adjusted, and the timing is adjusted. The constraint violation can be resolved. In this way, by only adding the dummy wiring 803 independent of the circuit operation, the violation of the timing constraint is solved and the circuit is optimized, so that there is no logical change, the backtracking of the design is suppressed, and the verification man-hour is reduced. This makes it possible to prevent the design period from increasing.

Next, a sixth example will be described. In the fifth example,
Although 803 in FIG. 8 is a dummy wiring, in the sixth example, 803 in FIG. 8 is an insulating wire. This insulated wire 80
For 3, an insulating material (dielectric) different from the insulating layer normally formed between the signal lines 801 and 802 is used.

Table 1 shows the relative permittivity of insulating materials mainly used in semiconductor integrated circuit devices.

[0039]

[Table 1]

Here, the relative dielectric constant of an ordinary inter-wiring insulating layer is ε ₁ , the dielectric constant of a vacuum is ε ₀ , and the interwiring capacitance in that case is C.
Set to 1.

C1 = (ε ₀ × ε ₁ × S) / d (Equation 2) Here, S represents a unit area, and d represents a wiring interval.

Consider a case where a dielectric having a relative permittivity of ε ₂ is inserted between the wirings. Here, for the sake of simplification, the case where a dielectric material is filled in between the wirings is considered, and the capacitance between the wirings at this time is defined as C2.

C2 = (ε ₀ × ε ₂ × S) / d (Equation 3) From Equation 2 and Equation 3, C2 / C1 = ε ₂ / ε ₁ , and C2 is ε ₂ / ε ₁ of C1. Doubled.

If, for example, silicon is used as a normal inter-wiring insulating layer and alumina is used as a dielectric having a relative permittivity of ε ₂ , from Table 1, ε ₂ / ε ₁ = 9.5 / 3.9 = 2 .44, and the inter-wiring capacitance is 2.44 times. From this, it is understood that the capacitance between wirings can be increased or decreased by changing the insulating material between wirings.

According to this sixth example, a normal insulating layer (not shown) provided between the signal line 801 violating the timing constraint and the signal line 802 adjacent to the signal line 801 is different. By arranging the insulating wire 803 made of an insulating material, it is possible to finely increase or decrease the inter-wiring capacitance and solve the timing constraint violation. By eliminating the timing constraint violation and optimizing the circuit simply by adding the insulated line 803 in this way, it is possible to reduce the number of verification steps by suppressing the backtracking of the design without logical changes. It is possible to prevent an increase in design period. A fine process requires fine timing adjustment, but this method enables fine timing adjustment.

The insulating wire 803 may be made of other dielectric material besides alumina.

[0047]

As described above, according to the present invention, by increasing / decreasing the capacity of the signal line in which the timing constraint is violated, the optimization mainly on the timing is performed, and the correction and the change of the narrow wiring are performed. Since it does not include logic change and cell change at all, it can reduce the verification items required after wiring modification / change and reduce the man-hours caused by backtracking of the design, increasing the design period. Can be prevented.

[Brief description of drawings]

FIG. 1 is a flowchart showing a method for designing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a top view of an example after completion of a wiring process in the embodiment of the present invention.

FIG. 3 is a top view of the first example of the embodiment of the present invention after the wiring interval is partially narrowed.

FIG. 4 is a top view of the second example in the exemplary embodiment of the present invention after wiring is partially widened.

FIG. 5 is a side view of an example after completion of the wiring process in the embodiment of the present invention.

FIG. 6 is a side view of the third example in the exemplary embodiment of the present invention after the wiring interval is partially narrowed.

FIG. 7 is a side view of the fourth example in the exemplary embodiment of the present invention after the wiring interval is partially widened.

FIG. 8 is a top view after a dummy wiring is arranged between the wirings in the fifth example of the exemplary embodiment of the present invention.

FIG. 9 is a diagram showing a circuit example for explaining a timing constraint violation.

10 is a timing chart showing a state where a hold time error occurs in the circuit of FIG.

11 is a timing chart showing a state in which a hold time error is eliminated by the circuit of FIG.

[Explanation of symbols]

101 Cell Placement Process 102 Wiring Process 103 Delay Time Calculation Process 104 Timing Constraint Violation Extraction Process 105 Timing Constraint Violation Optimization Process 201 Signal Line 202 Violating Timing Constraint Signal Line 203 Horizontally Adjacent to 201 201 Via Hole 301 Timing Constraint Signal line 302 violating signal 301 horizontally adjacent to signal line 303 via hole 401 Signal line 402 violating timing constraint signal line horizontally adjoining 401 signal 403 via hole 501 Signal violating timing constraint A signal line 601 vertically adjacent to the line 502 501 A signal line 701 vertically adjacent to the timing constraint violation 602 A signal line 701 vertically adjacent to the timing constraint 602 Vertically adjacent to a signal line 702 701 causing the timing constraint violation Signal line 803 dummy wiring or insulating lines 804 via holes adjacent in the horizontal direction to the signal line 802 801 undergoing signal line 801 timing constraint violations

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B046 AA08 BA06                 5F038 CD05 CD09 CD12 CD13 EZ20                 5F064 BB07 BB19 EE02 EE03 EE19                       EE42 EE43 EE47 HH06 HH10

Claims (5)

[Claims] 1. A cell arranging step of arranging a plurality of logic cells based on circuit design information, a wiring step of wiring between terminals of the plurality of logic cells, and a delay for calculating a wiring delay time of a wired signal line. A time calculation step, a timing constraint violation extraction step of extracting a signal line in which a timing constraint violation has occurred based on the result of the delay time calculation step, a signal line extracted by the timing constraint violation extraction step, and this signal A method of designing a semiconductor integrated circuit device, comprising: a timing constraint violation optimizing step of eliminating a timing constraint violation by increasing or decreasing an inter-wiring capacitance with another signal line adjacent to the line. 2. The timing constraint violation optimizing step increases the inter-wiring capacity by narrowing a wiring interval between a signal line violating the timing constraint and another signal line adjacent to the signal line. The method for designing a semiconductor integrated circuit device according to claim 1. 3. The timing constraint violation optimizing step reduces the inter-wiring capacitance by widening a wiring interval between a signal line violating the timing constraint and another signal line adjacent to the signal line. The method for designing a semiconductor integrated circuit device according to claim 1. 4. A cell arranging step of arranging a plurality of logic cells based on circuit design information, a wiring step of wiring between terminals of the plurality of logic cells, and a delay for calculating a wiring delay time of a wired signal line. A time calculation step, a timing constraint violation extraction step of extracting a signal line in which a timing constraint violation has occurred based on the result of the delay time calculation step, and a signal line extracted by the timing constraint violation extraction step adjacent to the signal line. And a timing constraint violation optimizing step of eliminating a timing constraint violation by arranging a dummy signal line independent of the circuit operation. 5. A cell arranging step of arranging a plurality of logic cells based on circuit design information, a wiring step of wiring between terminals of the plurality of logic cells, and a delay for calculating a wiring delay time of a wired signal line. A time calculation step; a timing constraint violation extraction step of extracting a signal line in which a timing constraint violation has occurred based on the result of the delay time calculation step; and a first step extracted by the timing constraint violation extraction step.
An insulating line is arranged along the first signal line between the signal line of FIG. 1 and a second signal line adjacent to the signal line, and the insulating line is connected to the first signal line and the second signal line. By using an insulating material different from the insulating layer that is to be provided between the first signal line and the second signal line, the inter-wiring capacitance between the first signal line and the second signal line is increased as compared with the case where the insulated line is not arranged or And a timing constraint violation optimizing step of reducing the timing constraint violation and eliminating the timing constraint violation.