JP2000294651A - Layout method for reducing clock skew - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a layout method for reducing clock skew by which an appropriate design can be made by grasping accurate propagating delaying time and arranging position by easily performing simulation accompanying the layout of circuit elements. SOLUTION: In a layout method for reducing clock skew, clock skews are reduced by making the propagation delaying time uniform in such a way that a plurality of local buffers 3 is arranged around a global buffer 2 supplied with clock signals and the local buffers 3 are connected to the global buffer 2 through wires 4 having the same length. Then the flip flops 9 of many registers are arranged on bars (wires) 8 crossing the wires 7 extended by the same distance in a plurality of directions from the local buffers 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit element layout method for reducing clock distortion and delay (clock skew) for defining operation timing of gates and the like in a semiconductor device.

[0002]

2. Description of the Related Art In general, in a semiconductor device, the frequency of a clock for defining the operation timing of a circuit element has been increased in accordance with a demand for high-speed data processing. High-speed storage and the like have been realized. In addition, high-speed integration of data processing has been performed together with high-speed data processing.
For ICs, a narrower width of 0.35 μm or less is required.

When actually manufacturing a semiconductor device, when circuit elements are arranged and virtually wired in a design stage,
Simulations are performed to debug in advance the propagation delay time (delay time due to cells + delay time due to wiring) that may be generated internally as the operation speeds up.

The error between the propagation delay time obtained by simulating the virtual wiring with respect to the layout of the cells and the layout of the positions of the wirings connecting these cells and the propagation delay time of the actually manufactured wiring is described. It is desired to reduce as much as possible.

[0005]

In the above-described propagation delay time, if the conventional wiring width is an integrated scale of about 0.5 μm, the delay due to the circuit element (cell) is mainly used. Even if a slight error occurs in the propagation delay time due to the above, it did not cause a serious problem.

For example, FIG. 3 shows a connection relation of buffer insertion by a clock tree.

In this connection configuration, a clock signal input / output terminal (I / O) 11 is connected to a global buffer 12 and further to a plurality of local buffers 13. A large number of flip-flops (F / F) 14 serving as registers 14 are connected to each local buffer 13 via a clock bar 15.

As described above, the number of gates per chip has been significantly increased due to the progress of integration, and even if the simulation is performed by the conventional method, the error becomes large.
Verification was difficult. In this figure, particularly, when the wiring distance from the global buffer 12 to the local buffer 13 increases, the delay time due to the wiring increases.

The reason for this is that the propagation delay time due to the wiring has been increased due to the fact that the wiring width has been reduced and the wiring length has been increased, while the propagation delay time due to the cell has not changed or has been reduced. Is attributed to For this reason, the flip-flop (F
/ F) and the like, there is an increased possibility that a clock signal defining an operation timing may be shifted to cause a malfunction.

In particular, if the distance between the global buffer 12 and a number of local buffers 13 connected thereto is different, the difference in propagation delay time becomes large.

In the conventional layout method, a predetermined layout tool arbitrarily determines the number of connections, ie, calculates the load capacity, and inserts it. But actually,
The number of stages and the number of connections had to be checked manually to arrange and connect. Therefore, a complicated work requiring skill was required for a designer in charge of designating an arrangement position of an accurate propagation delay time.

Accordingly, the present invention provides a clock skew reduction layout method that facilitates a simulation accompanying the layout of circuit elements, ascertains an accurate propagation delay time and an arrangement position, and enables an appropriate design. With the goal.

[0013]

To achieve the above object, the present invention provides a layout method for mounting a module on a semiconductor chip, comprising: a global buffer disposed on the semiconductor chip and supplied with a clock signal;
A plurality of local buffers arranged at positions connectable by wires of the same length around the global buffer, wherein wiring distances from the global buffer to the plurality of local buffers are equalized This provides a layout method for reducing the clock skew by equalizing the propagation delay time of the clock signal by each wiring.

[0014] Further, there is further provided a plurality of registers formed of flip-flops arranged on a bar line intersecting a line extending an equal distance from the local buffer in a plurality of directions.

In the clock skew reduction layout method as described above, the wiring distances from the global buffer to a large number of local buffers are equal, and the propagation delay time due to the wiring is equal. This eliminates one cause of clock skew and lays out circuit elements.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

The clock skew reduction layout method of the present invention is a method for reducing clock skew by connecting wiring to each module in a chip with equal length wiring.

FIG. 1 is a diagram conceptually showing an example of a layout when a module is mounted on a semiconductor chip according to an embodiment to which the present invention is applied.

In this layout, a global buffer 2 is arranged on a semiconductor chip 1. A plurality of local buffers 3 are arranged at equal wiring lengths around the global buffer 2, and each is connected to the global buffer 2 by a wiring 4 having an equal length. Also,
The global buffer 2 is connected to a clock input / output terminal (I / O terminal) 5 for supplying a clock signal from the outside via a wiring 6.

The position of the equal-length wiring in the present embodiment does not mean that the distance (for example, a straight line distance) from the global buffer 2 to the local buffer 3 is equal, but that the wiring provided for connecting the same can be equalized. Means

FIG. 2 shows an example of the arrangement of registers (flip-flops) in the local buffer 3. The above-described cell propagation delay time is greatly affected by the number of cell stages. Therefore, it is necessary to consider the arrangement of cells.

Therefore, as shown in FIG. 2, for example, a register 10 composed of a large number of flip-flops 9 is arranged on a bar (wiring) 8 intersecting a wiring 7 extending an equal distance from the local buffer 3 in a plurality of directions. When the flip-flops 9 are arranged at these positions, the propagation delay time can be made uniform.

Next, a design process for forming such a semiconductor chip layout using a placement / wiring tool will be described.

First, a power supply line and a ground line (not shown) are formed on the semiconductor chip 1.

Next, the clock buffer 2 is assigned. First, the global buffer 2 is arranged at an arbitrary position on the semiconductor chip 1, and the global buffer 2 is provided at the end of the semiconductor chip.
The wiring 6 connecting the / O terminal 5 is formed.

Thereafter, the position of the local buffer 3 is selected and arranged so that the wiring distance between the global buffer 2 and the global buffer 2 becomes the above-described equal-length wiring.
Then, a wiring 4 for connecting to the local buffer 3 is formed.
Flip-flops 9 of a large number of registers are arranged and formed on a bar 8 intersecting a wiring 7 extending an equal distance from the local buffer 3 in a plurality of directions.

As described above, according to the present embodiment, the wiring distances from the global buffer to a number of local buffers are equal, and the propagation delay time due to the wiring is equal. As a result, it is possible to realize a layout that eliminates the cause of clock skew that occurs when achieving high integration of semiconductor chips and high-speed data processing.

In this embodiment, a flip-flop of a register has been described as an example. However, the present invention is not limited to this, and circuit elements and modules driven by a clock signal and a timing signal can be easily applied. It can be applied, and malfunctions due to clock skew can be eliminated.

[0029]

As described above in detail, according to the present invention, it is possible to easily carry out a simulation associated with the layout of circuit elements, to grasp an accurate propagation delay time and an arrangement position, and to carry out an appropriate design. A clock skew reduction layout method can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram conceptually showing an example of a layout when a module is mounted on a semiconductor chip according to an embodiment to which the present invention is applied.

FIG. 2 is a diagram illustrating an example of a register (flip-flop) arranged in a local buffer according to the embodiment.

FIG. 3 is a diagram showing a connection relationship of buffer insertion using a conventional clock tree.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2 ... Global buffer 3 ... Local buffer 4, 6, 7 ... Wiring 5 ... Clock input / output terminal (I / O terminal) 8 ... Bar (wiring) 9 ... Flip-flop 10 ... Register

Claims (2)

[Claims] 1. A layout method for mounting a module on a semiconductor chip, comprising: a global buffer arranged on the semiconductor chip to which a clock signal is supplied; And a plurality of local buffers arranged at positions connectable by the wirings, and by making wiring distances from the global buffer to the plurality of local buffers equal, the propagation delay of the clock signal by each wiring A clock skew reduction layout method characterized in that clock skew is reduced by equalizing time. 2. The layout method according to claim 1, further comprising a plurality of registers arranged on a bar line intersecting a line extending an equal distance from the local buffer in a plurality of directions. Clock skew reduction layout method.