JPH08320894A - Method and device for adjusting wiring delay time - Google Patents

Abstract

PURPOSE: To satisfy a given delay time and reduce design man-hours and cost by providing a step wherein arrangement and wiring are performed so that restrictions of the delay time are satisfied, a step wherein the delay time is calculated, and a step wherein cell arrangement and wiring paths are recognized. CONSTITUTION: The circuit designing of VLSI, etc., consists of a step 11 wherein the restrictions of the delay time of wires between terminals of standard cells are set, a step 12 wherein the cell arrangement and wiring paths of function blocks composed of the standard cells are outputted, the step 13 wherein the delay time of the wires between the terminals of the standard cells is calculated, and the step 15 wherein the delay time of the wires is calculated according to the given restrictions. In a data input step 11, data required for arrangement wiring and delay calculation and the restrictions of the delay time given to a path between the terminals or a path passing plural cells are inputted. Then the arrangement and wiring are performed in an arrangement and wiring step 12 with a general timing driven layout.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to adjustment of wiring delay time in circuit design of semiconductor VLSI and the like.

[0002]

2. Description of the Related Art In recent years, LSI timing design has become more and more important as process miniaturization, higher integration, and higher processing speed. Delay between terminals between an output terminal of a cell and an input terminal of a cell. A time-driven layout in which time constraints and delay time constraints of paths connecting input / output terminals of multiple cells are applied, and placement and routing are performed within the given delay time constraints, and clock signals reach multiple flip-flop cells. In order to minimize the clock skew value, which is the difference between the shortest time and the longest time required for clocking, clock tree synthesis is commonly used in which the buffer cells for adjusting the delay time are inserted in a tree pattern in the clock wiring. There is.

[0003]

However, in the timing driven layout, it is general that the placement and routing are performed so that the delay time given as a constraint is not exceeded, and the placement and routing is done beyond the given delay time. What you do is not common. Therefore, it is not possible to deal with the case where the placement and routing must be performed over a given delay time as in the scan routing. Therefore, there is a problem that the design man-hours are increased and the area of the block is also increased, such as manually adjusting the length of the wiring or changing to a wiring having a large resistance.

In the clock tree synthesis, the buffer cells and flip-flops are arranged and wired so as to minimize the skew of the clock wiring. Therefore, the skew value may be larger than the design constraint.

In this case, it is necessary to reexamine the circuit configuration of the worst clock, the design period is not long, and there is a problem in design man-hours and cost.

In view of the above problems, the present invention adjusts the delay time without affecting the area of the block as much as possible, thereby satisfying the given delay time and reducing the design man-hours and costs.

[0007]

In a circuit design of VLSI or the like, a step of giving a restriction on a delay time of wiring between terminals of a standard cell, a cell layout of a functional block constituted by the standard cell and a wiring route are output. The wiring delay time adjusting method includes a step, a step of calculating a wiring delay time between terminals of a standard cell, and a step of adjusting the wiring delay time according to a given constraint.

Further, in a circuit design of VLSI or the like, a device for restricting a delay time of wiring between terminals of a standard cell, a device for outputting a cell layout and a wiring route of a functional block composed of standard cells, and a standard device. A wiring delay time adjusting device configured by a device that calculates a delay time of a wiring between terminals of a cell and a device that adjusts the delay time of the wiring according to a given constraint.

[0009]

By adjusting the delay time of the wiring without affecting the increase in the area of the VLSI chip, the given delay time constraint is satisfied and the design man-hours and costs are reduced.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 3 shows a delay adjustment cell for adjusting a wiring delay time.

In FIG. 3, reference numeral 21 is a spacer cell for securing a space for passing a vertical wiring,
The width of the cell is W. All cells have the same height, and all cells have a width that is a multiple of W.

The wiring of the wiring layer of M0 having a large wiring resistance value (for example, polysilicon) added for adjusting the wiring delay time has a minimum line width of W / 3 and a minimum interval of W / 3. Since these values depend on the process, they do not necessarily have the above ratios, but since the ratio of the minimum line width and the minimum interval to W is larger than that of the actual process, it is less than that of the actual process. The space for adding the wiring of the wiring layer of M0 is reduced.

In FIG. 3, 22 is M0 in the spacer cell.
2 is a delay adjustment cell to which wiring of the wiring layer is added. P1
And P2 are terminals for connecting to other wiring.

In FIG. 3, the reference numeral 23 is similar to the reference numeral 22, and the wiring of the wiring layer of M0 is added to the double width of the spacer cell.
It is a delay adjustment cell having a delay of about 2 times.

Since the wiring delay can be increased by increasing the width of the cell, it is only necessary to prepare a delay adjustment cell having a necessary wiring delay value according to the wiring delay value.

In FIGS. 4 to 6, ROW1 is a column of standard cells. Cell1 to Cell3 are standard cells. FEED1 to FEED3 are spacer cells 21, FEED4 is a delay adjustment cell 23, and FEED5 is a delay adjustment cell 24.

M01 to M05 are wires of the 0th wiring layer having a high resistance value such as polysilicon, M11 to M13 are wires of the first wiring layer having a low resistance value such as metal, and M21 to M24 are like metal. The wiring of the second wiring layer having a low resistance value. VI
A011 to VIA013 are contacts connecting the 0th wiring layer and the first wiring layer, and VIA 1211 to VIA124 are contacts connecting the first wiring layer and the second wiring layer.

The flow of processing in the first embodiment is shown in FIG. In the data input step 10, data required for placement and routing, delay calculation, and terminals, or constraints on delay time given to a path passing through a plurality of cells are input. Next, in the placement and routing step 12, placement and routing is performed by a general timing driven layout. As a result, it is assumed that the result shown in FIG. 4 is obtained.

Next, the time required for the signal output from the output terminal of Cell1 shown in FIG.
If there is a delay time constraint that a given time must be exceeded, delay calculation step 1
The delay of 3 is calculated and it is verified whether the given constraint is satisfied.

If the constraint is not satisfied, Cell1
Of the wiring connecting the input terminal of Cell3 to the input terminal of Cell3 is calculated, and a new constraint is given to the wiring connecting the output terminal of Cell1 to the input terminal of Cell3.

Next, at the wiring route recognition step 14, Cel is performed.
A feed through cell that can be replaced with a delay adjustment cell is searched for between the wiring connecting the output terminal of 11 and the input terminal of Cell3. In the case of FIG. 4, Ce is output from the output terminal of Cell1.
Cell1 and Cell of the distribution path connecting the input terminals of ll3
It can be seen that the cells of FEED1 to FEED3 existing between 3 are all feedthrough cells 21 and can be replaced with delay adjustment cells.

Next, in the wiring delay adjusting step 15, the wiring route is determined from the increase time of the delay given in the delay calculating step 13, the number of feedthrough cells and the layout position recognized in the wiring route recognizing step 14. Since there is a high possibility that the area will become large if changed, the delay adjustment cell is added and the wiring route is changed so as not to change the wiring route as much as possible.

From the delay increase time given in the delay calculation step 13, FEED1 is replaced with the delay adjustment cell 22 and FEED2 and FEED3 are replaced with the delay adjustment cell 23 as shown in FIGS. Next, in order to connect Cell1 and FEED4, VIA122 is replaced with VIA011 and M22 is replaced with M01. Similarly, FEED
4 to connect FEED5, set M23 to M02, V
IA123 is replaced with VIA012, M12 is replaced with M13, and VIA013 and M03 are added. Similarly, F
M04, VIA to connect EED5 and Cell3
014, M13, and VIA015 are added.

The delay time of the wiring in which the delay adjustment cell is added and the wiring route is changed is calculated, and if the constraint is satisfied, the processing is terminated. If the constraint is not satisfied, M13 is raised as shown in FIG. Change to resistance wiring M05, VIA0
12 and VIA 013 are deleted.

The delay time of the wiring in which the delay adjustment cell is added and the wiring path is changed is calculated, and if the constraint is satisfied, the process is ended.

If the result of FIG. 6 does not satisfy the constraint,
A delay adjustment cell is further added between Cell1 and Cell3 and the same processing is performed. However, if too many delay adjustment cells are required, the block area will be greatly affected. Therefore, it is necessary to repeat the above processing from the cell arrangement so that the distance between Cell1 and Cell3 becomes large.

As described above, according to the present invention, since it is not necessary to make a large change in the wiring path, it is possible to easily adjust the wiring delay time without affecting the area of the block. Then, it is possible to satisfy the constraint of the given delay time.

In the present invention, in order to adjust the clock skew and the timing of the scan wiring and to reduce the power consumption, the timing of the signal input to the input terminal is adjusted to reduce the glitch, and the delay value of the wiring is slightly increased. This is effective for processing that requires adjustment when wiring is delayed.

(Embodiment 2) FIG. 2 shows the configuration of the apparatus of this embodiment and the flow of processing.

The data input device 101 performs the process of the data input step 11. The placement and routing apparatus 102 performs the process of placement and routing step 12.

The delay calculation device 103 performs the process of the delay calculation step 13. The wiring route recognition device 104 performs the processing of the wiring route recognition step 14.

The wiring delay adjusting device 105 performs the processing of the wiring route recognition step 15. Data output device 106
Writes the layout and wiring result as a file in the hard disk and displays the result on a display or the like.

Also in the case of this embodiment, the same effect as that of the above-mentioned embodiment 1 is obtained.

[0035]

According to the wiring delay time adjusting method of the present invention, the wiring delay time can be adjusted without affecting the increase in the VLSI chip area. Therefore, it becomes possible to satisfy the given delay time constraint and reduce the design man-hours and costs.

[Brief description of drawings]

FIG. 1 is a diagram showing a processing flow of a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a delay adjustment cell in the first embodiment.

FIG. 4 is a diagram showing a result of placing and routing in a placing and routing step in the example.

FIG. 5 is a view showing a result of adding a delay adjustment cell and changing a wiring route in the embodiment.

FIG. 6 is a diagram for explaining the processing when the wiring delay time does not satisfy the constraint condition as a result of the processing of FIG. 5 in the embodiment.

[Explanation of symbols]

 11 data input step 12 placement and routing step 13 delay calculation step 14 wiring route recognition step 15 wiring delay adjustment step 101 data input device 102 placement and routing device 103 delay calculation device 104 wiring route recognition device 105 wiring delay adjustment device 106 data output device

Claims (2)

[Claims] 1. In a circuit design using a functional block composed of standard cells (referred to as cells), a step of placing and routing so as to satisfy a delay time constraint, a step of calculating a delay time, and a cell placement A method of adjusting a wiring delay time, comprising a step of recognizing a wiring route and a step of adjusting a wiring delay time according to a given constraint. 2. A device for arranging and wiring so as to satisfy delay time constraint, a device for recognizing cell layout and wiring route, and a device for calculating delay time in a circuit design using a functional block composed of standard cells. And a device for adjusting a wiring delay time according to a given constraint.