JPH11232311A - Clock tree and synthesis method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To have a clock skew value of a route where a clock skew value may exceed a range of a predicated value set within a range of the predicted value by once an arrangement wiring. SOLUTION: A clock tree 10 has each of driving buffers set a buffer 41 of a reference driving capability and an adjustment buffer 71 for the driving capability different from the reference driving capability arranged nearby the buffer 41, and selects as a driving buffer either the buffer 41 or the adjustment buffer 71 so that a clock skew is within a specified range in accordance with a simulation result after synthetic of the clock tree.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock tree and a method for synthesizing the same, and more particularly, to a large-scale semiconductor integrated circuit (LS).
The present invention relates to a clock tree having a function of adjusting clock skew for a logic circuit built in I) and a method of synthesizing the same.

[0002]

2. Description of the Related Art Clock tree synthesis (clock tree synthesis) is an LSI based on computer-aided design (CAD).
Is used to reduce the clock skew value of a clock tree which is a clock distribution circuit in an LSI chip.

In the conventional design of a clock tree for a logic circuit inside an LSI, in order to reduce the clock skew value, the number and input capacity of flip-flops, which are loads to be connected, are investigated, and each connected to the clock tree. The number of each flip-flop of the load flip-flop group is distributed so that the load capacity becomes equal, and each of the distributed load flip-flop groups is branched by a buffer having the same driving capability. These tasks were designed manually.

However, in recent years, as the speed of transistors as circuit elements has increased, the ratio of delay due to wiring has increased as compared with the delay in a circuit block using these circuit elements. Even if the clock tree is designed so that the input capacitances become equal, the clock skew value becomes large due to wiring delay after placement and wiring, and the timing is often unsatisfactory.
In addition, since the circuit scale has been increased, it has been difficult to adjust the clock skew value by re-designing the circuit or correcting the arrangement and wiring data.

Therefore, in the clock tree synthesis, the layout and wiring design of the logic circuit is designed in advance so as to minimize the clock skew value, so that the clock skew value increases after the layout and wiring, and the circuit design is redone and the layout and wiring data is corrected. Was thought to eliminate.

In a general conventional clock tree synthesizing method, a predicted value of a clock skew is set based on the driving capability of a buffer used in circuit design and the number of flip-flops. At the time of circuit design, a design is performed using the predicted value so as to satisfy the timing standard.

Referring to FIG. 8, which shows a block diagram of a conventional clock tree 100 to be synthesized with a clock tree, the conventional clock tree 100 includes a first-stage buffer 1 connected to a clock input terminal TC1 to which a clock CK is input. , A buffer group 2 composed of a cascade-connected second to (n-2) th (n is an integer) buffer groups each including a plurality of buffers having the same driving capability and receiving the output of the buffer 1; , A plurality of buffers 31, 32, 32,.
, And a plurality of buffers 4 having the same driving capability receiving the output of the buffer group 3
, Including the n-th or final stage buffer group 4 including 1, 42,..., And receiving a supply of the clock CKD output from each of the buffer groups 4.
The flip-flop group 5 including the flip-flops 52, 53,.

Next, a conventional method for synthesizing a clock tree will be described with reference to FIG. 9 and FIG. 9 which is a flowchart showing the clock tree synthesizing process of FIG. 8 and FIG. 10 which is a layout diagram showing a layout result. The synthesis process of the clock tree 100 is performed. Clock tree 10
All the circuit blocks except 0 are arranged, and a flip-flop group 5 serving as a load of each buffer of the clock tree 100
The clock tree 100 is synthesized such that the clock skew value is reduced based on the number, input capacity, and arrangement position of each flip-flop (step F1).

Next, arrangement and wiring are performed. At this time, in order to reduce the clock skew value, the number of flip-flops, the input capacity of the flip-flops, and the capacity predicted from the arrangement position are calculated, and a plurality of flip-flops are determined in advance so that the capacities become equal. Each group is divided into groups, and one buffer having the same driving capability is arranged at the center of each group. Next, the groups are grouped into groups each having a predetermined number, and one buffer having the same driving capability is arranged in each group. This process is continued until the number of groups becomes one. Thereafter, wiring is performed (steps F2 to F4). In this way, the clock tree 100 is automatically synthesized so that the clock skew is reduced. Next, a clock skew value is calculated (step F5), and it is determined whether the clock skew value is within the range of the predicted value (step F6). If the result of this determination is that the clock skew value is within the range of the predicted value, the clock tree 100 is completed and the process ends.

If the result of determination in step F6 is that the clock skew value exceeds the range of the predicted value, the process proceeds to step F7, where it is determined whether or not the correction can be made by manual wiring correction. If the result of this determination is that correction is possible, wiring correction is executed (step F).
7) Return to step F5 and execute steps F5 and F6 again.

If the result of determination in step F7 is that correction is not possible, the process proceeds to step F9, where a circuit change is performed, and thereafter, this processing is performed again from step F1.

However, this conventional technique has the following problems. The first problem is that the clock skew value often exceeds the predicted value.
The reason is that, even if the clock skew value exceeds the range of the predicted value after the synthesis of the clock tree, there is no means / step for correcting the clock skew value within the range of the predicted value. Due to recent improvements in manufacturing technology, miniaturization has progressed, and the dependence of delay values on wiring has been increasing. For this reason, simply arranging the buffers in a well-balanced manner causes the delay values of the wirings to vary and the clock skew value to increase. The second problem is that when the clock skew exceeds the range of the predicted value, the wiring and arrangement of the clock tree, correction of the block arrangement and wiring other than the clock tree, or all the arrangement and wiring are performed again. Must be within the range of predicted values. In the worst case, the predicted value must be reviewed and the circuit design started again. Therefore, the design period becomes long. The reason for this is that since all the placement and wiring have been completed, there is no more space for placement even if a new buffer is to be inserted.

[0013]

The above-mentioned conventional clock tree and its synthesizing method correct the clock skew value within the expected value range even if the clock skew value exceeds the expected value range after the clock tree synthesis. Since there is no means or processing procedure for performing this, there is a disadvantage that the clock skew value often exceeds the predicted value.

Further, when the clock skew exceeds the range of the predicted value, it is necessary to correct the wiring and arrangement of the clock tree and the peripheral circuits, or to redo all the arrangement and wiring. There is a drawback that the value of the value needs to be re-examined and the circuit design needs to be redone, thus lengthening the design period.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock tree capable of containing a clock skew value of a path whose clock skew value may exceed or fall below a range of a predicted value within the predicted value by a single placement and wiring. An object of the present invention is to provide a synthesis method.

[0016]

SUMMARY OF THE INVENTION A clock tree according to the present invention comprises a plurality of buffer groups each comprising a plurality of buffers cascaded to distribute a clock for operating a logic circuit incorporated in a large-scale integrated circuit. In a clock tree in which a last-stage buffer group composed of a driving buffer drives the logic circuit, each of the driving buffers constituting the last-stage buffer group is a reference buffer having a predetermined first driving capability. A buffer for adjusting a second driving capability different from the first driving capability disposed in the vicinity of the reference buffer, wherein the reference skew is within a predetermined range according to a simulation result after the synthesis of the clock tree. One of the buffer and the adjusting buffer is selected as the driving buffer.

According to the clock tree synthesizing method of the present invention, in order to distribute a clock for operating a logic circuit incorporated in a large-scale integrated circuit, a plurality of stages of buffer groups composed of a plurality of buffers are cascade-connected to form a plurality of driving buffers. In the clock tree synthesizing method in which the final-stage buffer group synthesizes a clock tree for driving the logic circuit, each of the driving buffers constituting the final-stage buffer group has a predetermined first driving capability. A reference buffer and a buffer for adjusting a second driving capability different from the first driving capability disposed near the reference buffer are prepared, and the clock skew is within a predetermined range according to a simulation result after the clock tree synthesis. So that one of the reference buffer and the adjustment buffer is selected as the driving buffer. It is an butterfly.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a clock tree 10 to be synthesized according to an embodiment of the present invention is shown in the same manner as FIG. Referring to FIG. 1, a clock tree 10 of the present embodiment shown in FIG.
A first-stage buffer 1 connected to a clock input terminal TC1 to which K is input, and a cascade-connected second to (n-2) th stages each including a plurality of buffers having the same driving capability, receiving the output of the buffer 1 (N is an integer) buffer group 2 and a plurality of buffers 3 having the same driving capability, receiving the outputs of the buffer group of the (n-2) th stage of the buffer group 2.
, A plurality of buffers having the same driving capability (reference driving capability) receiving the output of the buffer group 3 in place of the buffer group 4 in addition to the (n-1) -th stage buffer group 3 including 1, 32,. 41, 42,... And these buffers 41,
, The driving capacity of each of the buffers 41, 42
Adjustment buffers 61, 62,.
. And a buffer group 6 of the n-th stage, that is, the final stage, which has low driving capability adjusting buffers 71, 72,... Having low driving capability lower than the buffers 41, 42 in the vicinity. Clock CKD output from each of groups 6
Flip-flops 51, 52, 5 receiving the
The flip-flop group 5 including 3,... Is driven.

That is, in the vicinity of the buffer 41, a high driving ability buffer 61 and a low driving ability adjusting buffer 71 are provided.
In the vicinity of the buffer 42, an adjusting buffer 62 having a high driving ability and an adjusting buffer 72 having a low driving ability are arranged. The same applies to the buffer 43 and thereafter.

The adjusting buffer 61 drives, for example, m transistors (m is an integer) of the same size as the output transistor of the buffer 41 having the reference driving capability, or the size of the output transistor of the buffer 41 is m.
It can be realized by using a transistor of twice the size.

Similarly, the adjusting buffer 71 can be realized by using a transistor having a size which is 1 / m times the size of the output transistor of the buffer 41 having the reference driving capability. Further, the output transistor of the buffer 41 may be configured by driving m output transistors of the adjustment buffer 71 in parallel.

As is well known, when the load including the load capacity of the output buffer is constant, the signal delay changes in accordance with the magnitude of the driving capability of the buffer. That is, when the buffer driving capability is low, the signal delay increases, and when the driving capability is high, the signal delay decreases.

Therefore, in the present embodiment, as described below, first, a clock tree is synthesized using a buffer 41 (a typical example) having a reference driving capability, and then a clock skew is calculated. When the queue is larger than the predicted value, the buffer 41 is changed to the buffer 61 having a high driving capability, and when the queue is smaller than the predicted value, the buffer 41 is changed to the buffer 71 having a low driving capability, whereby the clock skew is changed to a predetermined value. It is within the range.

The clock tree synthesizing process according to the present embodiment is denoted by the same reference characters / numbers as those of FIG. .. F5, the buffers 41, 42,.
The adjustment buffer setting step A1 for setting the adjustment buffers 61 and 62 for the high and low drive ability with respect to the reference drive ability for each of the above, and one of the adjustment buffers 61 and 71 set in the step A1 is selectively arranged. An adjusting buffer arranging step A2, a skew value judging step A3 for judging whether or not the clock skew is within a range of a predicted value, and extracting a flip-flop and a buffer for driving the flip-flop outside the range of the predicted skew value. Prediction value out-of-range extraction step A4, change calculation step A5 for calculating the clock skew value when the extraction location is changed, and wiring correction for changing the connection and correcting the wiring so that the clock skew value is within the prediction value range Step A6 and an unused buffer deletion step of deleting unused buffers in the adjustment buffer arranged in step A2. And a flop A7.

Next, the method of synthesizing the clock tree according to the present embodiment will be described with reference to FIGS. 1 and 2 and FIG. 3 showing a layout result in a layout diagram. Perform the combining process. All the blocks except the clock tree 10 are arranged, and the number of flip-flops of each flip-flop group 5 serving as a load of each buffer of the clock tree 10, input capacity,
The clock tree 10 is synthesized so that the clock skew value becomes smaller from the arrangement position (step F1).

Next, with respect to all the buffers 41, 42,... Of the buffer group 6 in the final stage of the clock tree 10 synthesized in step F1, an adjustment buffer 61 for adjustment of high driving capability is provided. , 62,... And low drive capability adjustment buffers 71, 72,.

Next, as in the prior art, the clock tree 10
Are arranged (step F2).

Next, the adjustment buffers 61, 62,... For adjusting the high driving ability and the adjustment buffers 71, 72,. All corresponding buffers 41, 42,.
.. are arranged near each other (step A
2). FIG. 3 shows that the adjustment buffers 61 and 71 are arranged near the buffer 41.

Next, the clock tree 10 and the wiring for the clock input of the flip-flop group 12 are respectively wired (step F3), and the clock skew value is calculated (step F5).

From the calculation result, a flip-flop in which the clock skew value of the flip-flop group 5 is out of the range of the predicted value is extracted, and the wiring connected to the clock input of the flip-flop and the clock tree connected to the previous stage are extracted. One set of two adjustment buffers of high driving ability and low driving ability set in step A2 and extracted in the vicinity of one of the buffers of the ten final-stage buffer group 6 and the vicinity thereof are extracted (step A4).

Next, the connection at the extraction point in step A4 is set for all the combinations that can be changed, and all the clock skew values when the connection is changed are calculated (step A5).

From the result, a connection in which the clock skew value falls within the range of the predicted value is selected (when there are two or more types of connection changes that fall within the range of the predicted value, the connection in which the clock skew becomes the smallest) is selected. The wiring is modified to change the connection (step A6).

Next, the input of the unused adjustment buffer is deleted (step A7).

Finally, connections other than the clock tree are wired (step F4).

Next, the operation of the present invention will be described in detail using a specific example with reference to FIGS. 4 and 5, which show connection change plan data corresponding to the use of the adjusting buffer. As an example, it is assumed that the clock skew value of the flip-flop 53 of the flip-flop group 5 exceeds the predicted value.

In step A4, the buffer 41, the adjusting buffers 61 and 71, and the wiring 8 are extracted. Step A5
4A, 4B, and 5C, and FIG.
With reference to all the connection change plan data shown in (A), (B), and (C), the clock skew value when each change plan is implemented is determined based on the arrangement positions of the buffers 41, 61, and 71 and the wired state. Each calculation is performed using the wiring capacitance of the wiring 8. In this example, the connection change plan data D1 includes FIG.
Six examples of (B), (C), and FIGS. 5 (A), (B), and (C) are set.

In step A6, based on the calculation result, the clock skew value in the connection change plan data is within the range of the predicted value, and the connection in FIG. , The connection using the adjustment buffer 61 is selected, and the connection between the buffers 41 and 61 and the clock input of the flip-flop 53 is changed. Therefore, the wiring is corrected only at the changed location.

In step A7, the input of the unused adjustment buffer 71 among the adjustment buffers 61 and 71 arranged in step A2 is deleted. Next, according to the second embodiment of the present invention, the clock tree 10 to be synthesized with the clock tree 10 will be described.
FIG. 6, in which A is denoted by common reference characters / numerals for the same components as in FIG. 1 and is similarly shown in a block diagram, is referred to as FIG. 6. The difference is that the last-stage buffer group 6A instead of the last-stage buffer group 6 has buffers 41, 42,.
.. Has only one type of adjusting buffer having a different driving capability from the buffers 41 and 42 for each of the buffers. In this example, only the adjusting buffers 71, 72,. That is, the adjusting buffer 61 having a high driving capability,
62,...

The operation of this embodiment is the same as that of the first embodiment shown in FIG. In this embodiment, since there is only one type of buffer for adjusting clock skew, the arrangement time of the clock tree (step A2) and all combinations that can change the connection of the extraction location are set and changed. The processing time for calculating all the clock skew values (step A5) can be reduced.

As described above, the present invention can also be realized by providing one or more clock skew adjustment buffers having the same or different driving capabilities in advance for one final-stage buffer.

Next, a third embodiment of the present invention will be described with reference to the flowchart of FIG.
Referring to FIG. 1, the first embodiment of the present embodiment shown in FIG.
The difference from the embodiment is that a change calculation step B5 for calculating a clock skew value by a preset number instead of the change calculation step A5 for calculating the clock skew value for all changeable combinations, An attempt is made to keep the clock skew within the predicted value.

In the present embodiment, several types of change proposals (here, FIGS. 4 (A), (B),
(C), and the clock skew value is calculated according to the proposed change.

From the calculation results of the three types of changes, the one with the smallest clock skew value is selected, the connection is changed, and the wiring is corrected.

Therefore, there is a new effect that the processing time for setting the clock skew value within the range of the predicted value is reduced.

As described above, the present invention can also be realized by setting several kinds of correction methods in advance when the clock skew value is out of the range of the predicted value.

[0046]

As described above, according to the clock tree and the method of synthesizing the same according to the present invention, each of the driving buffers includes:
A reference buffer; and a buffer for adjusting different driving capacities arranged in the vicinity of the reference buffer, wherein the reference buffer and the adjustment buffer are arranged such that a clock skew is within a predetermined range according to a simulation result after clock tree synthesis. By selecting one of the two as the driving buffer, the clock skew can be kept within the range of the predicted value at one time, so that there is no need for correction due to the clock skew exceeding the range of the predicted value. There is.

Further, there is an effect that even if the clock skew exceeds the range of the predicted value, the clock skew can be easily adjusted.

Furthermore, since there is no wiring other than the clock tree at the time of wiring correction for adjusting the clock skew, there is an effect that the correction is easy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a clock tree of the present invention.

FIG. 2 is a flowchart illustrating an example of a process in a clock tree synthesizing method according to the embodiment;

FIG. 3 is a layout diagram illustrating an example of a clock tree obtained as a result of synthesis by the clock tree synthesis method according to the present embodiment;

FIG. 4 is a diagram illustrating a first and a second corresponding to a specific usage method of the adjusting buffer in the clock tree synthesizing method according to the present embodiment.
FIG. 13 is a circuit diagram showing third connection change proposal data. It is a circuit diagram which shows connection change proposal data.

FIG. 5 is a diagram illustrating a fourth example of the adjustment buffer used in the method of synthesizing the clock tree according to the embodiment;
FIG. 16 is a circuit diagram showing a sixth connection change proposal data.

FIG. 6 is a block diagram illustrating a clock tree according to a second embodiment of the present invention;

FIG. 7 is a flowchart illustrating an example of a process in a clock tree synthesizing method according to a third embodiment of the present invention.

FIG. 8 is a block diagram illustrating an example of a conventional clock tree.

FIG. 9 is a flowchart illustrating an example of processing in a conventional clock tree synthesis method.

FIG. 10 is a layout diagram illustrating an example of a clock tree obtained as a result of synthesis according to a conventional clock tree synthesis method.

[Explanation of symbols]

 1, 31, 32, 41, 42 Buffer 2, 3, 4, 6, 6A Buffer group 5 Flip-flop group 8 Wiring 51, 52, 53 Flip-flop 61, 71 Adjustment buffer 100, 10, 10A Clock tree

Claims (10)

[Claims] 1. A cascade connection of a plurality of buffer groups of a plurality of buffers for distributing an operation clock of a logic circuit built in a large-scale integrated circuit, and a final-stage buffer group of a plurality of driving buffers. In the clock tree for driving the logic circuit, each of the driving buffers constituting the last-stage buffer group includes a reference buffer having a predetermined first drive capability and a first buffer arranged near the reference buffer. And a buffer for adjusting a second driving ability different from the driving ability of the reference tree, wherein one of the reference buffer and the adjusting buffer is adjusted so that a clock skew is within a predetermined range according to a simulation result after clock tree synthesis. A clock tree selected as the driving buffer. 2. The clock tree according to claim 1, wherein said adjusting buffer is a first adjusting buffer having a higher driving ability than said reference buffer. 3. The clock tree according to claim 1, wherein the adjusting buffer is a second adjusting buffer having a lower driving ability and a lower driving ability than the reference buffer. 4. A first adjusting buffer having a high driving capability higher than the reference buffer and a second adjusting buffer having a low driving capability lower than the reference buffer.
2. An adjusting buffer according to claim 1, further comprising:
Clock tree described. 5. A cascade connection of a plurality of buffer groups of a plurality of buffers for distributing an operation clock of a logic circuit built in a large-scale integrated circuit, and a final-stage buffer group of a plurality of driving buffers is provided. In a clock tree synthesizing method for synthesizing a clock tree for driving the logic circuit, each of the driving buffers constituting the last-stage buffer group includes a reference buffer having a predetermined first driving capability, and the reference buffer. And a buffer for adjusting a second driving capability different from the first driving capability, which is arranged near the reference buffer, and the reference buffer and the buffer are adjusted so that the clock skew is within a predetermined range according to the simulation result after the synthesis of the clock tree. A method for synthesizing a clock tree, wherein one of the adjusting buffers is selected as the driving buffer. . 6. The clock tree synthesizing method according to claim 5, wherein the adjusting buffer is a first adjusting buffer having a higher driving ability than the reference buffer. 7. The clock tree synthesizing method according to claim 5, wherein said adjusting buffer is a second adjusting buffer having a low driving ability lower in driving ability than said reference buffer. 8. A first adjustment buffer having a high driving ability higher than the reference buffer and a second adjusting buffer having a lower driving ability lower than the reference buffer.
6. An adjusting buffer according to claim 1, further comprising:
The described clock tree synthesis method. 9. An adjusting buffer setting step of setting the adjusting buffer for each of the reference buffers of the last-stage buffer group, and an adjusting step of arranging the adjusting buffer set in the adjusting buffer setting step. Buffer arranging step; skew value judging step of judging whether clock skew is within a range of a predicted value; and prediction for extracting a logic circuit to be driven and a buffer for driving the circuit outside the range of the predicted value of the clock skew. A value-out-of-value extraction step; a change calculation step of calculating a clock skew when the driving buffer at the extraction location extracted in the prediction value-out extraction step is changed to the adjustment buffer; and A wiring correction step of changing the connection and correcting the wiring so as to fall within the value range; 6. The clock tree synthesizing method according to claim 5, further comprising: an unused buffer deleting step of deleting an unused buffer in the adjustment buffer arranged in the buffer arranging step. 10. The clock tree synthesizing method according to claim 9, wherein said change calculation step calculates the clock skew for a predetermined number of cases.